[llvm] r210719 - [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.

[Eric Christopher]

Testcase.

-eric

On Wed, Jun 11, 2014 at 4:10 PM, Juergen Ributzka <juergen at apple.com> wrote:
> Author: ributzka
> Date: Wed Jun 11 18:10:58 2014
> New Revision: 210719
>
> URL: http://llvm.org/viewvc/llvm-project?rev=210719&view=rev
> Log:
> [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86FastISel.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=210719&r1=210718&r2=210719&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Jun 11 18:10:58 2014
> @@ -1896,31 +1896,39 @@ bool X86FastISel::FastLowerArguments() {
>      return false;
>
>    // Only handle simple cases. i.e. Up to 6 i32/i64 scalar arguments.
> +  unsigned GPRCnt = 0;
> +  unsigned FPRCnt = 0;
>    unsigned Idx = 1;
> -  for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
> -       I != E; ++I, ++Idx) {
> -    if (Idx > 6)
> -      return false;
> -
> +  for (auto const &Arg : F->args()) {
>      if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
>          F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
>          F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
>          F->getAttributes().hasAttribute(Idx, Attribute::Nest))
>        return false;
>
> -    Type *ArgTy = I->getType();
> +    Type *ArgTy = Arg.getType();
>      if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
>        return false;
>
>      EVT ArgVT = TLI.getValueType(ArgTy);
>      if (!ArgVT.isSimple()) return false;
>      switch (ArgVT.getSimpleVT().SimpleTy) {
> +    default: return false;
>      case MVT::i32:
>      case MVT::i64:
> +      ++GPRCnt;
>        break;
> -    default:
> -      return false;
> +    case MVT::f32:
> +    case MVT::f64:
> +      ++FPRCnt;
> +        break;
>      }
> +
> +    if (GPRCnt > 6)
> +      return false;
> +
> +    if (FPRCnt > 8)
> +      return false;
>    }
>
>    static const MCPhysReg GPR32ArgRegs[] = {
> @@ -1929,24 +1937,33 @@ bool X86FastISel::FastLowerArguments() {
>    static const MCPhysReg GPR64ArgRegs[] = {
>      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
>    };
> +  static const MCPhysReg XMMArgRegs[] = {
> +    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
> +    X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
> +  };
>
> -  Idx = 0;
> -  const TargetRegisterClass *RC32 = TLI.getRegClassFor(MVT::i32);
> -  const TargetRegisterClass *RC64 = TLI.getRegClassFor(MVT::i64);
> -  for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
> -       I != E; ++I, ++Idx) {
> -    bool is32Bit = TLI.getValueType(I->getType()) == MVT::i32;
> -    const TargetRegisterClass *RC = is32Bit ? RC32 : RC64;
> -    unsigned SrcReg = is32Bit ? GPR32ArgRegs[Idx] : GPR64ArgRegs[Idx];
> +  unsigned GPRIdx = 0;
> +  unsigned FPRIdx = 0;
> +  for (auto const &Arg : F->args()) {
> +    MVT VT = TLI.getSimpleValueType(Arg.getType());
> +    const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
> +    unsigned SrcReg;
> +    switch (VT.SimpleTy) {
> +    default: llvm_unreachable("Unexpected value type.");
> +    case MVT::i32: SrcReg = GPR32ArgRegs[GPRIdx++]; break;
> +    case MVT::i64: SrcReg = GPR64ArgRegs[GPRIdx++]; break;
> +    case MVT::f32: // fall-through
> +    case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break;
> +    }
>      unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
>      // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
>      // Without this, EmitLiveInCopies may eliminate the livein if its only
>      // use is a bitcast (which isn't turned into an instruction).
>      unsigned ResultReg = createResultReg(RC);
>      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
> -            TII.get(TargetOpcode::COPY),
> -            ResultReg).addReg(DstReg, getKillRegState(true));
> -    UpdateValueMap(I, ResultReg);
> +            TII.get(TargetOpcode::COPY), ResultReg)
> +      .addReg(DstReg, getKillRegState(true));
> +    UpdateValueMap(&Arg, ResultReg);
>    }
>    return true;
>  }
>
>
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