[llvm] r210656 - [mips][mips64r6] Improve tests affected by the changes to multiplies and divides
Daniel Sanders
daniel.sanders at imgtec.com
Wed Jun 11 08:48:01 PDT 2014
Author: dsanders
Date: Wed Jun 11 10:48:00 2014
New Revision: 210656
URL: http://llvm.org/viewvc/llvm-project?rev=210656&view=rev
Log:
[mips][mips64r6] Improve tests affected by the changes to multiplies and divides
Summary:
MIPS32r6/MIPS64r6 support has not been added yet.
inlineasm-cnstrnt-reg.ll:
Explicitly specify the CPU since it will not work on MIPS32r6/MIPS64r6
when -integrated-as is the default. We can't change the mnemonic since the
LO register is an implicit def of mtlo and MIPS32r6/MIPS64r6 has no
instructions that use LO.
2008-08-01-AsmInline.ll:
Explicitly specify the CPU since MIPS32r6/MIPS64r6 will correctly emit
different code and this is a regression test.
mips64instrs.ll and mips64muldiv.ll
Check registers and the way the multiply is used in m1
divrem.ll
Check registers and use multiple filecheck prefixes to limit redundancy
Reviewers: vmedic, jkolek, zoran.jovanovic, matheusalmeida
Reviewed By: matheusalmeida
Subscribers: matheusalmeida
Differential Revision: http://reviews.llvm.org/D3894
Modified:
llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll
llvm/trunk/test/CodeGen/Mips/divrem.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll
Modified: llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll?rev=210656&r1=210655&r2=210656&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll Wed Jun 11 10:48:00 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
%struct.DWstruct = type { i32, i32 }
Modified: llvm/trunk/test/CodeGen/Mips/divrem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/divrem.ll?rev=210656&r1=210655&r2=210656&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/divrem.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/divrem.ll Wed Jun 11 10:48:00 2014
@@ -1,77 +1,121 @@
-; RUN: llc -march=mips -verify-machineinstrs < %s |\
-; RUN: FileCheck %s -check-prefix=TRAP
-; RUN: llc -march=mips -mno-check-zero-division < %s |\
-; RUN: FileCheck %s -check-prefix=NOCHECK
-
-; TRAP-LABEL: sdiv1:
-; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
-; TRAP: teq $[[R0]], $zero, 7
-; TRAP: mflo
-
-; NOCHECK-LABEL: sdiv1:
-; NOCHECK-NOT: teq
-; NOCHECK: .end sdiv1
+; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC -check-prefix=TRAP
+; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC -check-prefix=NOCHECK
+
+; FileCheck Prefixes:
+; ALL - All targets
+; ACC - Accumulator based multiply/divide. I.e. All ISA's before MIPS32r6
+; TRAP - Division must be explicitly checked for divide by zero
+; NOCHECK - Division by zero will not be detected
@g0 = common global i32 0, align 4
@g1 = common global i32 0, align 4
define i32 @sdiv1(i32 %a0, i32 %a1) nounwind readnone {
entry:
+; ALL-LABEL: sdiv1:
+
+; ACC: div $zero, $4, $5
+
+; TRAP: teq $5, $zero, 7
+; NOCHECK-NOT: teq
+
+; ACC: mflo $2
+
+; ALL: .end sdiv1
+
%div = sdiv i32 %a0, %a1
ret i32 %div
}
-; TRAP-LABEL: srem1:
-; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
-; TRAP: teq $[[R0]], $zero, 7
-; TRAP: mfhi
-
define i32 @srem1(i32 %a0, i32 %a1) nounwind readnone {
entry:
+; ALL-LABEL: srem1:
+
+; ACC: div $zero, $4, $5
+
+; TRAP: teq $5, $zero, 7
+; NOCHECK-NOT: teq
+
+; ACC: mfhi $2
+
+; ALL: .end srem1
+
%rem = srem i32 %a0, %a1
ret i32 %rem
}
-; TRAP-LABEL: udiv1:
-; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
-; TRAP: teq $[[R0]], $zero, 7
-; TRAP: mflo
-
define i32 @udiv1(i32 %a0, i32 %a1) nounwind readnone {
entry:
+; ALL-LABEL: udiv1:
+
+; ACC: divu $zero, $4, $5
+
+; TRAP: teq $5, $zero, 7
+; NOCHECK-NOT: teq
+
+; ACC: mflo $2
+
+; ALL: .end udiv1
%div = udiv i32 %a0, %a1
ret i32 %div
}
-; TRAP-LABEL: urem1:
-; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
-; TRAP: teq $[[R0]], $zero, 7
-; TRAP: mfhi
-
define i32 @urem1(i32 %a0, i32 %a1) nounwind readnone {
entry:
+; ALL-LABEL: urem1:
+
+; ACC: divu $zero, $4, $5
+
+; TRAP: teq $5, $zero, 7
+; NOCHECK-NOT: teq
+
+; ACC: mfhi $2
+
+; ALL: .end urem1
+
%rem = urem i32 %a0, %a1
ret i32 %rem
}
-; TRAP: div $zero,
define i32 @sdivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind {
entry:
+; ALL-LABEL: sdivrem1:
+
+; ACC: div $zero, $4, $5
+; TRAP: teq $5, $zero, 7
+; NOCHECK-NOT: teq
+; ACC: mflo $2
+; ACC: mfhi $[[R0:[0-9]+]]
+; ACC: sw $[[R0]], 0(${{[0-9]+}})
+
+; ALL: .end sdivrem1
+
%rem = srem i32 %a0, %a1
store i32 %rem, i32* %r, align 4
%div = sdiv i32 %a0, %a1
ret i32 %div
}
-; TRAP: divu $zero,
define i32 @udivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind {
entry:
+; ALL-LABEL: udivrem1:
+
+; ACC: divu $zero, $4, $5
+; TRAP: teq $5, $zero, 7
+; NOCHECK-NOT: teq
+; ACC: mflo $2
+; ACC: mfhi $[[R0:[0-9]+]]
+; ACC: sw $[[R0]], 0(${{[0-9]+}})
+
+; ALL: .end udivrem1
+
%rem = urem i32 %a0, %a1
store i32 %rem, i32* %r, align 4
%div = udiv i32 %a0, %a1
ret i32 %div
}
+; FIXME: It's not clear what this is supposed to test.
define i32 @killFlags() {
entry:
%0 = load i32* @g0, align 4
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll?rev=210656&r1=210655&r2=210656&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll Wed Jun 11 10:48:00 2014
@@ -1,6 +1,7 @@
; Positive test for inline register constraints
;
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
define i32 @main() nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll?rev=210656&r1=210655&r2=210656&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64instrs.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64instrs.ll Wed Jun 11 10:48:00 2014
@@ -1,99 +1,115 @@
-; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS4 %s
-; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS64 %s
+; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
+; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 %s
@gll0 = common global i64 0, align 8
@gll1 = common global i64 0, align 8
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: daddu
+; ALL-LABEL: f0:
+; ALL: daddu $2, ${{[45]}}, ${{[45]}}
%add = add nsw i64 %a1, %a0
ret i64 %add
}
define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: dsubu
+; ALL-LABEL: f1:
+; ALL: dsubu $2, $4, $5
%sub = sub nsw i64 %a0, %a1
ret i64 %sub
}
define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: and
+; ALL-LABEL: f4:
+; ALL: and $2, ${{[45]}}, ${{[45]}}
%and = and i64 %a1, %a0
ret i64 %and
}
define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: or
+; ALL-LABEL: f5:
+; ALL: or $2, ${{[45]}}, ${{[45]}}
%or = or i64 %a1, %a0
ret i64 %or
}
define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: xor
+; ALL-LABEL: f6:
+; ALL: xor $2, ${{[45]}}, ${{[45]}}
%xor = xor i64 %a1, %a0
ret i64 %xor
}
define i64 @f7(i64 %a0) nounwind readnone {
entry:
-; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, 20
+; ALL-LABEL: f7:
+; ALL: daddiu $2, $4, 20
%add = add nsw i64 %a0, 20
ret i64 %add
}
define i64 @f8(i64 %a0) nounwind readnone {
entry:
-; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, -20
+; ALL-LABEL: f8:
+; ALL: daddiu $2, $4, -20
%sub = add nsw i64 %a0, -20
ret i64 %sub
}
define i64 @f9(i64 %a0) nounwind readnone {
entry:
-; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 20
+; ALL-LABEL: f9:
+; ALL: andi $2, $4, 20
%and = and i64 %a0, 20
ret i64 %and
}
define i64 @f10(i64 %a0) nounwind readnone {
entry:
-; CHECK: ori ${{[0-9]+}}, ${{[0-9]+}}, 20
+; ALL-LABEL: f10:
+; ALL: ori $2, $4, 20
%or = or i64 %a0, 20
ret i64 %or
}
define i64 @f11(i64 %a0) nounwind readnone {
entry:
-; CHECK: xori ${{[0-9]+}}, ${{[0-9]+}}, 20
+; ALL-LABEL: f11:
+; ALL: xori $2, $4, 20
%xor = xor i64 %a0, 20
ret i64 %xor
}
define i64 @f12(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: mult
+; ALL-LABEL: f12:
+; ALL: mult ${{[45]}}, ${{[45]}}
%mul = mul nsw i64 %b, %a
ret i64 %mul
}
define i64 @f13(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: mult
+; ALL-LABEL: f13:
+; ALL: mult ${{[45]}}, ${{[45]}}
%mul = mul i64 %b, %a
ret i64 %mul
}
define i64 @f14(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK-LABEL: f14:
-; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
-; CHECK: teq $[[R0]], $zero, 7
-; CHECK: mflo
+; ALL-LABEL: f14:
+; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
+; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
+; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
+; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
+; ALL: ddiv $zero, $[[T0]], $[[T1]]
+; ALL: teq $[[T1]], $zero, 7
+; ALL: mflo $2
%0 = load i64* @gll0, align 8
%1 = load i64* @gll1, align 8
%div = sdiv i64 %0, %1
@@ -102,10 +118,14 @@ entry:
define i64 @f15() nounwind readnone {
entry:
-; CHECK-LABEL: f15:
-; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
-; CHECK: teq $[[R0]], $zero, 7
-; CHECK: mflo
+; ALL-LABEL: f15:
+; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
+; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
+; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
+; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
+; ALL: ddivu $zero, $[[T0]], $[[T1]]
+; ALL: teq $[[T1]], $zero, 7
+; ALL: mflo $2
%0 = load i64* @gll0, align 8
%1 = load i64* @gll1, align 8
%div = udiv i64 %0, %1
@@ -114,20 +134,20 @@ entry:
define i64 @f16(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK-LABEL: f16:
-; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
-; CHECK: teq $[[R0]], $zero, 7
-; CHECK: mfhi
+; ALL-LABEL: f16:
+; ALL: ddiv $zero, $4, $5
+; ALL: teq $5, $zero, 7
+; ALL: mfhi $2
%rem = srem i64 %a, %b
ret i64 %rem
}
define i64 @f17(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK-LABEL: f17:
-; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
-; CHECK: teq $[[R0]], $zero, 7
-; CHECK: mfhi
+; ALL-LABEL: f17:
+; ALL: ddivu $zero, $4, $5
+; ALL: teq $5, $zero, 7
+; ALL: mfhi $2
%rem = urem i64 %a, %b
ret i64 %rem
}
@@ -136,24 +156,24 @@ declare i64 @llvm.ctlz.i64(i64, i1) noun
define i64 @f18(i64 %X) nounwind readnone {
entry:
-; CHECK-LABEL: f18:
+; ALL-LABEL: f18:
; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
-; MIPS4-NOT: dclz
+; MIPS4-NOT: dclz
-; MIPS64: dclz $2, $4
+; MIPS64: dclz $2, $4
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
}
define i64 @f19(i64 %X) nounwind readnone {
entry:
-; CHECK-LABEL: f19:
+; ALL-LABEL: f19:
; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
-; MIPS4-NOT: dclo
+; MIPS4-NOT: dclo
-; MIPS64: dclo $2, $4
+; MIPS64: dclo $2, $4
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1
@@ -161,8 +181,8 @@ entry:
define i64 @f20(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK-LABEL: f20:
-; CHECK: nor
+; ALL-LABEL: f20:
+; ALL: nor $2, ${{[45]}}, ${{[45]}}
%or = or i64 %b, %a
%neg = xor i64 %or, -1
ret i64 %neg
Modified: llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll?rev=210656&r1=210655&r2=210656&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll Wed Jun 11 10:48:00 2014
@@ -1,50 +1,64 @@
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL
define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: dmult
-; CHECK: mflo
+; ALL-LABEL: m0:
+; ALL: dmult ${{[45]}}, ${{[45]}}
+; ALL: mflo $2
%mul = mul i64 %a1, %a0
ret i64 %mul
}
define i64 @m1(i64 %a) nounwind readnone {
entry:
-; CHECK: dmult
-; CHECK: mfhi
+; ALL-LABEL: m1:
+; ALL: lui $[[T0:[0-9]+]], 21845
+; ALL: addiu $[[T0]], $[[T0]], 21845
+; ALL: dsll $[[T0]], $[[T0]], 16
+; ALL: addiu $[[T0]], $[[T0]], 21845
+; ALL: dsll $[[T0]], $[[T0]], 16
+; ALL: addiu $[[T0]], $[[T0]], 21846
+; ALL: dmult ${{[45]}}, $[[T0]]
+; ALL: mfhi $[[T1:[0-9]+]]
+; ALL: dsrl $2, $[[T1]], 63
+; ALL: daddu $2, $[[T1]], $2
%div = sdiv i64 %a, 3
ret i64 %div
}
define i64 @d0(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: ddivu
-; CHECK: mflo
+; ALL-LABEL: d0:
+; ALL: ddivu $zero, $4, $5
+; ALL: mflo $2
%div = udiv i64 %a0, %a1
ret i64 %div
}
define i64 @d1(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: ddiv
-; CHECK: mflo
+; ALL-LABEL: d1:
+; ALL: ddiv $zero, $4, $5
+; ALL: mflo $2
%div = sdiv i64 %a0, %a1
ret i64 %div
}
define i64 @d2(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: ddivu
-; CHECK: mfhi
+; ALL-LABEL: d2:
+; ALL: ddivu $zero, $4, $5
+; ALL: mfhi $2
%rem = urem i64 %a0, %a1
ret i64 %rem
}
define i64 @d3(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK: ddiv
-; CHECK: mfhi
+; ALL-LABEL: d3:
+; ALL: ddiv $zero, $4, $5
+; ALL: mfhi $2
%rem = srem i64 %a0, %a1
ret i64 %rem
}
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