[llvm] r210525 - AArch64: disallow x30 & x29 as the destination for indirect tail calls

Tim Northover tnorthover at apple.com
Tue Jun 10 03:50:24 PDT 2014


Author: tnorthover
Date: Tue Jun 10 05:50:24 2014
New Revision: 210525

URL: http://llvm.org/viewvc/llvm-project?rev=210525&view=rev
Log:
AArch64: disallow x30 & x29 as the destination for indirect tail calls

As Ana Pazos pointed out, these have to be restored to their incoming values
before a function returns; i.e. before the tail call. So they can't be used
correctly as the destination register.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
    llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td?rev=210525&r1=210524&r2=210525&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td Tue Jun 10 05:50:24 2014
@@ -175,7 +175,7 @@ def GPR64all : RegisterClass<"AArch64",
 // This is for indirect tail calls to store the address of the destination.
 def tcGPR64 : RegisterClass<"AArch64", [i64], 64, (sub GPR64common, X19, X20, X21,
                                                      X22, X23, X24, X25, X26,
-                                                     X27, X28)>;
+                                                     X27, X28, FP, LR)>;
 
 // GPR register classes for post increment amount of vector load/store that
 // has alternate printing when Rm=31 and prints a constant immediate value

Modified: llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll?rev=210525&r1=210524&r2=210525&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/regress-tail-livereg.ll Tue Jun 10 05:50:24 2014
@@ -17,3 +17,17 @@ define void @foo() {
 ; CHECK: br {{x([0-79]|1[0-8])}}
        ret void
 }
+
+; No matter how tempting it is, LLVM should not use x30 since that'll be
+; restored to its incoming value before the "br".
+define void @test_x30_tail() {
+; CHECK-LABEL: test_x30_tail:
+; CHECK: mov [[DEST:x[0-9]+]], x30
+; CHECK: br [[DEST]]
+  %addr = call i8* @llvm.returnaddress(i32 0)
+  %faddr = bitcast i8* %addr to void()*
+  tail call void %faddr()
+  ret void
+}
+
+declare i8* @llvm.returnaddress(i32)





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