[llvm] r210520 - AArch64: teach FastISel how to handle offset FrameIndices

[Tim Northover]

Author: tnorthover
Date: Tue Jun 10 04:52:44 2014
New Revision: 210520

URL: http://llvm.org/viewvc/llvm-project?rev=210520&view=rev
Log:
AArch64: teach FastISel how to handle offset FrameIndices

Previously we were abandonning the attempt, leading to some combination of
extra work (when selection of a load/store fails completely) and inferior code
(when this leads to a real memcpy call instead of inlining).

rdar://problem/17187463

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
    llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=210520&r1=210519&r2=210520&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Tue Jun 10 04:52:44 2014
@@ -463,11 +463,18 @@ bool AArch64FastISel::SimplifyAddress(Ad
     break;
   }
 
-  // FIXME: If this is a stack pointer and the offset needs to be simplified
-  // then put the alloca address into a register, set the base type back to
-  // register and continue. This should almost never happen.
+  //If this is a stack pointer and the offset needs to be simplified then put
+  // the alloca address into a register, set the base type back to register and
+  // continue. This should almost never happen.
   if (needsLowering && Addr.getKind() == Address::FrameIndexBase) {
-    return false;
+    unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
+            ResultReg)
+        .addFrameIndex(Addr.getFI())
+        .addImm(0)
+        .addImm(0);
+    Addr.setKind(Address::RegBase);
+    Addr.setReg(ResultReg);
   }
 
   // Since the offset is too large for the load/store instruction get the

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll?rev=210520&r1=210519&r2=210520&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll Tue Jun 10 04:52:44 2014
@@ -136,9 +136,13 @@ define void @t8() {
 
 define void @test_distant_memcpy(i8* %dst) {
 ; ARM64-LABEL: test_distant_memcpy:
-; ARM64: bl _memcpy
+; ARM64: mov [[ARRAY:x[0-9]+]], sp
+; ARM64: movz [[OFFSET:x[0-9]+]], #0x1f40
+; ARM64: add x[[ADDR:[0-9]+]], [[ARRAY]], [[OFFSET]]
+; ARM64: ldrb [[BYTE:w[0-9]+]], [x[[ADDR]]]
+; ARM64: strb [[BYTE]], [x0]
   %array = alloca i8, i32 8192
   %elem = getelementptr i8* %array, i32 8000
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %elem, i64 4, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %elem, i64 1, i32 1, i1 false)
   ret void
 }