Author: mcrosier
Date: Sun Jun 8 20:25:51 2014
New Revision: 210445
URL: http://llvm.org/viewvc/llvm-project?rev=210445&view=rev
Log:
[AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift
plus add. The shift can be folded into the add. This only effects codegen
when the constant is 3.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=210445&r1=210444&r2=210445&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Sun Jun 8 20:25:51 2014
@@ -6344,15 +6344,6 @@ static SDValue performMulCombine(SDNode
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
APInt Value = C->getAPIntValue();
EVT VT = N->getValueType(0);
- APInt VP1 = Value + 1;
- if (VP1.isPowerOf2()) {
- // Multiplying by one less than a power of two, replace with a shift
- // and a subtract.
- SDValue ShiftedVal =
- DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
- DAG.getConstant(VP1.logBase2(), MVT::i64));
- return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
- }
APInt VM1 = Value - 1;
if (VM1.isPowerOf2()) {
// Multiplying by one more than a power of two, replace with a shift
@@ -6362,6 +6353,15 @@ static SDValue performMulCombine(SDNode
DAG.getConstant(VM1.logBase2(), MVT::i64));
return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
}
+ APInt VP1 = Value + 1;
+ if (VP1.isPowerOf2()) {
+ // Multiplying by one less than a power of two, replace with a shift
+ // and a subtract.
+ SDValue ShiftedVal =
+ DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
+ DAG.getConstant(VP1.logBase2(), MVT::i64));
+ return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
+ }
}
return SDValue();
}
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll?rev=210445&r1=210444&r2=210445&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll Sun Jun 8 20:25:51 2014
@@ -260,3 +260,11 @@ define i64 @f3(i64 %a) nounwind readnone
%res = mul nsw i64 %a, 17
ret i64 %res
}
+
+define i32 @f4(i32 %a) nounwind readnone ssp {
+; CHECK-LABEL: f4:
+; CHECK-NEXT: add w0, w0, w0, lsl #1
+; CHECK-NEXT: ret
+ %res = mul i32 %a, 3
+ ret i32 %res
+}