[llvm] r210401 - Fix typos

[Alp Toker]

Author: alp
Date: Sat Jun  7 16:23:09 2014
New Revision: 210401

URL: http://llvm.org/viewvc/llvm-project?rev=210401&view=rev
Log:
Fix typos

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
    llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
    llvm/trunk/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
    llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll
    llvm/trunk/test/DebugInfo/X86/gnu-public-names.ll
    llvm/trunk/test/MC/AArch64/arm64-system-encoding.s

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp?rev=210401&r1=210400&r2=210401&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp Sat Jun  7 16:23:09 2014
@@ -1414,7 +1414,7 @@ void DwarfUnit::applySubprogramAttribute
   if (DISubprogram SPDecl = SP.getFunctionDeclaration()) {
     DeclDie = getDIE(SPDecl);
     assert(DeclDie && "This DIE should've already been constructed when the "
-                      "definition DIE was creaeted in "
+                      "definition DIE was created in "
                       "getOrCreateSubprogramDIE");
     DeclLinkageName = SPDecl.getLinkageName();
   }

Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=210401&r1=210400&r2=210401&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Sat Jun  7 16:23:09 2014
@@ -160,7 +160,7 @@ bool PEI::runOnMachineFunction(MachineFu
   replaceFrameIndices(Fn);
 
   // If register scavenging is needed, as we've enabled doing it as a
-  // post-pass, scavenge the virtual registers that frame index elimiation
+  // post-pass, scavenge the virtual registers that frame index elimination
   // inserted.
   if (TRI->requiresRegisterScavenging(Fn) && FrameIndexVirtualScavenging)
     scavengeFrameVirtualRegs(Fn);

Modified: llvm/trunk/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXImageOptimizer.cpp?rev=210401&r1=210400&r2=210401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXImageOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXImageOptimizer.cpp Sat Jun  7 16:23:09 2014
@@ -146,7 +146,7 @@ bool NVPTXImageOptimizer::replaceIsTypeP
 void NVPTXImageOptimizer::replaceWith(Instruction *From, ConstantInt *To) {
   // We implement "poor man's DCE" here to make sure any code that is no longer
   // live is actually unreachable and can be trivially eliminated by the
-  // unreachable block elimiation pass.
+  // unreachable block elimination pass.
   for (CallInst::use_iterator UI = From->use_begin(), UE = From->use_end();
        UI != UE; ++UI) {
     if (BranchInst *BI = dyn_cast<BranchInst>(*UI)) {

Modified: llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll?rev=210401&r1=210400&r2=210401&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll Sat Jun  7 16:23:09 2014
@@ -3,7 +3,7 @@
 ; clang -Oz -c test1.cpp -emit-llvm -S -o
 ; Verify that we generate shld insruction when we are optimizing for size,
 ; even for X86_64 processors that are known to have poor latency double 
-; precision shift instuctions.
+; precision shift instructions.
 ; uint64_t lshift10(uint64_t a, uint64_t b)
 ; {
 ;     return (a << 10) | (b >> 54);
@@ -25,7 +25,7 @@ attributes #0 = { minsize nounwind optsi
 ; clang -Os -c test2.cpp -emit-llvm -S
 ; Verify that we generate shld insruction when we are optimizing for size,
 ; even for X86_64 processors that are known to have poor latency double
-; precision shift instuctions.
+; precision shift instructions.
 ; uint64_t lshift11(uint64_t a, uint64_t b)
 ; {
 ;     return (a << 11) | (b >> 53);
@@ -46,7 +46,7 @@ attributes #1 = { nounwind optsize readn
 ; clang -O2 -c test2.cpp -emit-llvm -S
 ; Verify that we do not generate shld insruction when we are not optimizing
 ; for size for X86_64 processors that are known to have poor latency double
-; precision shift instuctions.
+; precision shift instructions.
 ; uint64_t lshift12(uint64_t a, uint64_t b)
 ; {
 ;     return (a << 12) | (b >> 52);

Modified: llvm/trunk/test/DebugInfo/X86/gnu-public-names.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/gnu-public-names.ll?rev=210401&r1=210400&r2=210401&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/gnu-public-names.ll (original)
+++ llvm/trunk/test/DebugInfo/X86/gnu-public-names.ll Sat Jun  7 16:23:09 2014
@@ -123,7 +123,7 @@
 ; CHECK:     NULL
 ; CHECK-NOT: {{DW_TAG|NULL}}
 ; FIXME: We probably shouldn't bother describing the implicit
-; import of the preceeding anonymous namespace. This should be fixed
+; import of the preceding anonymous namespace. This should be fixed
 ; in clang.
 ; CHECK:     DW_TAG_imported_module
 ; CHECK-NOT: {{DW_TAG|NULL}}

Modified: llvm/trunk/test/MC/AArch64/arm64-system-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-system-encoding.s?rev=210401&r1=210400&r2=210401&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/arm64-system-encoding.s (original)
+++ llvm/trunk/test/MC/AArch64/arm64-system-encoding.s Sat Jun  7 16:23:09 2014
@@ -4,7 +4,7 @@
 foo:
 
 ;-----------------------------------------------------------------------------
-; Simple encodings (instuctions w/ no operands)
+; Simple encodings (instructions w/ no operands)
 ;-----------------------------------------------------------------------------
 
   nop