[PATCH] Fixing inst-combine not to drops nsw when combining adds into mul (PR19263)

[Dinesh Dwivedi]

Yes, now WillNotOverflowSignedAdd can handle cases where 
one of LHS and RHS is power of 2 and other has known zero 
after high bit in first one. I will update test accordingly or if you
think that should go as independent patch I can surely do that.

For you other comment, I think we can not have nsw in addition
of 2 variables even if any one of them is not known to have nsw.
So I think nsw in add is wrong. But I may be wrong.

How about this input
a = 0x2aaa
b = 0x5554
c = 0x7ffe
d = 0xd552

b and c are ok here as mul instructions does not guaranty either
(overflow and no overflow) but add instruction guaranties no sign
overflow but d is overflowing.

http://reviews.llvm.org/D3799