[llvm] r210167 - Add a subtarget hook: enablePostMachineScheduler.
Andrew Trick
atrick at apple.com
Wed Jun 4 22:19:19 PDT 2014
On Jun 4, 2014, at 12:05 PM, Eric Christopher <echristo at gmail.com> wrote:
> Worth doing this for the other MISched options?
This is a big one because it activates/deactivates the pass. I would put it in Passes.cpp if that weren’t verboten.
The only other option that looks like a hook candidate to me is MacroFusion. There’s already a hook but it’s evaluated on all instructions currently which could take a little extra time. Anyone is welcome to add an umbrella hook for it.
-Andy
>
> -eric
>
> On Wed, Jun 4, 2014 at 12:06 AM, Andrew Trick <atrick at apple.com> wrote:
>> Author: atrick
>> Date: Wed Jun 4 02:06:27 2014
>> New Revision: 210167
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=210167&view=rev
>> Log:
>> Add a subtarget hook: enablePostMachineScheduler.
>>
>> As requested by AArch64 subtargets.
>>
>> Note that this will have no effect until the
>> AArch64 target actually enables the pass like this:
>> substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
>>
>> As soon as armv7 switches over, PostMachineScheduler will become the
>> default postRA scheduler, so this won't be necessary any more.
>> Targets using the old postRA schedule would then do:
>> substitutePass(&PostMachineSchedulerID, &PostRASchedulerID);
>>
>> Modified:
>> llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
>> llvm/trunk/lib/CodeGen/MachineScheduler.cpp
>> llvm/trunk/lib/CodeGen/Passes.cpp
>> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>> llvm/trunk/lib/Target/ARM/ARMSubtarget.h
>> llvm/trunk/lib/Target/TargetSubtargetInfo.cpp
>>
>> Modified: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=210167&r1=210166&r2=210167&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)
>> +++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Wed Jun 4 02:06:27 2014
>> @@ -66,6 +66,13 @@ public:
>> /// scheduler. It does not yet disable the postRA scheduler.
>> virtual bool enableMachineScheduler() const;
>>
>> + /// \brief True if the subtarget should run PostMachineScheduler.
>> + ///
>> + /// This only takes effect if the target has configured the
>> + /// PostMachineScheduler pass to run, or if the global cl::opt flag,
>> + /// MISchedPostRA, is set.
>> + virtual bool enablePostMachineScheduler() const;
>> +
>> /// \brief Override generic scheduling policy within a region.
>> ///
>> /// This is a convenient way for targets that don't provide any custom
>>
>> Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=210167&r1=210166&r2=210167&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Wed Jun 4 02:06:27 2014
>> @@ -333,6 +333,12 @@ bool PostMachineScheduler::runOnMachineF
>> if (skipOptnoneFunction(*mf.getFunction()))
>> return false;
>>
>> + const TargetSubtargetInfo &ST =
>> + mf.getTarget().getSubtarget<TargetSubtargetInfo>();
>> + if (!ST.enablePostMachineScheduler()) {
>> + DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
>> + return false;
>> + }
>> DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
>>
>> // Initialize the context of the pass.
>>
>> Modified: llvm/trunk/lib/CodeGen/Passes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Passes.cpp?rev=210167&r1=210166&r2=210167&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/Passes.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/Passes.cpp Wed Jun 4 02:06:27 2014
>> @@ -92,9 +92,9 @@ PrintMachineInstrs("print-machineinstrs"
>>
>> // Temporary option to allow experimenting with MachineScheduler as a post-RA
>> // scheduler. Targets can "properly" enable this with
>> -// substitutePass(&PostRASchedulerID, &MachineSchedulerID); Ideally it wouldn't
>> -// be part of the standard pass pipeline, and the target would just add a PostRA
>> -// scheduling pass wherever it wants.
>> +// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); Ideally it
>> +// wouldn't be part of the standard pass pipeline, and the target would just add
>> +// a PostRA scheduling pass wherever it wants.
>> static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
>> cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
>>
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=210167&r1=210166&r2=210167&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Jun 4 02:06:27 2014
>> @@ -352,6 +352,13 @@ bool ARMSubtarget::hasSinCos() const {
>> !getTargetTriple().isOSVersionLT(7, 0);
>> }
>>
>> +// Enable the PostMachineScheduler if the target selects it instead of
>> +// PostRAScheduler. Currently only available on the command line via
>> +// -misched-postra.
>> +bool ARMSubtarget::enablePostMachineScheduler() const {
>> + return PostRAScheduler;
>> +}
>> +
>> bool ARMSubtarget::enablePostRAScheduler(
>> CodeGenOpt::Level OptLevel,
>> TargetSubtargetInfo::AntiDepBreakMode& Mode,
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=210167&r1=210166&r2=210167&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Jun 4 02:06:27 2014
>> @@ -396,6 +396,9 @@ public:
>> /// compiler runtime or math libraries.
>> bool hasSinCos() const;
>>
>> + /// True for some subtargets at > -O0.
>> + bool enablePostMachineScheduler() const;
>> +
>> /// enablePostRAScheduler - True at 'More' optimization.
>> bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
>> TargetSubtargetInfo::AntiDepBreakMode& Mode,
>>
>> Modified: llvm/trunk/lib/Target/TargetSubtargetInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSubtargetInfo.cpp?rev=210167&r1=210166&r2=210167&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/TargetSubtargetInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/TargetSubtargetInfo.cpp Wed Jun 4 02:06:27 2014
>> @@ -43,6 +43,10 @@ bool TargetSubtargetInfo::enableMachineS
>> return false;
>> }
>>
>> +bool TargetSubtargetInfo::enablePostMachineScheduler() const {
>> + return false;
>> +}
>> +
>> bool TargetSubtargetInfo::enablePostRAScheduler(
>> CodeGenOpt::Level OptLevel,
>> AntiDepBreakMode& Mode,
>>
>>
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