[llvm] r209746 - InstCombine: Improvement to check if signed addition overflows.

[Rafael Espíndola]

>
> I updated my patch with the test cases. Can you please check if this is
> correct?
>
> If it looks good to you, can you please commit it on my behalf?
>
>
>
> My patch also handles the case, where  one of the operand has only 1 bit
> that is not known to
>
> be zero, but it is also not know to be one.
>
> ((~RHSKnownZero).countpopulation == 1) will be able to determine if only
> one of the bit is unkown (it may be 1 or 0).
>
>
>
> As far as the test case :
>
>
>
> *define i32 @foo(i32 %x, i32 %y) {*
> *  %v1 = and i32 %y, 1*
> *  %v2 = add i32 %x, %v1*
> *  ret i32 %v2*
> *}*
>
>
>
> We know that only one of the bit is unknown of one of the operand, it may
> be 1 or 0.
>
> But for the other operand, we do not know if it has 0 at any higher bit
> position. Hence we do not add 'nsw' in this case.
>
>
>
> Added this test case as well + test case to handle sext  i1(bitwidth = 1).
>
>
>
> Awaiting for your review.
>
>
The check for a bitwidth of one seems redundant. The updated computation
of Op1OnePosition handles that case too, no?

It looks like the tests can be simplified a bit further. They are still
using numbered instead of named instructions for example.

Please make sure the positive tests are cases that currently fail, so they
demonstrate the new optimization capabilities. For example, we already add
a nsw to  @ripple_nsw because of the current logic for handling both
operands having more than one sign bit.

Cheers,
Rafael
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