[llvm] r209746 - InstCombine: Improvement to check if signed addition overflows.

[suyog sarda]

On Tue, Jun 3, 2014 at 2:25 AM, Rafael Espíndola <rafael.espindola at gmail.com
> wrote:

> WillNotOverflowSignedAdd should return the correct result for any LHS
> and RHS. I agree that you found a case where it does not.  I think the
> issues is that
>
>  if (ComputeNumSignBits(LHS) > 1 && ComputeNumSignBits(RHS) > 1)
>     return true;
>

Yes, the culprit seems to above code this for your patch. i just checked it.


>
> Also needs to check that the sign bit is the same, not just hat LHS
> and RHS have more then one sign bit.  Checking if that is the root
> issue.
>
>
>
I am not sure if this is only applicable to operands having same sign bit.

As per comment above this code -


*Add has the property that adding any two 2's complement numbers can only
have one carry bit which can change a sign.  As such, if LHS and RHS each
have at least two sign bits, we know that the addition of the two values
will sign extend fine.*

Because, if we have one of the operand as 111xxxxx......and other operand
as 000xxxx....,
the code is perfectly applicable in such case even though their sign bit is
different. I am not sure if we should discard this case.

Awaiting for your analysis :)

-- 
With regards,
Suyog Sarda
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