[llvm] r209655 - [mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2
Zoran Jovanovic
zoran.jovanovic at imgtec.com
Tue May 27 05:55:40 PDT 2014
Author: zjovanovic
Date: Tue May 27 07:55:40 2014
New Revision: 209655
URL: http://llvm.org/viewvc/llvm-project?rev=209655&view=rev
Log:
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2
Differential Revision: http://reviews.llvm.org/D3824
Added:
llvm/trunk/test/MC/Mips/mips32r6/relocations.s
llvm/trunk/test/MC/Mips/mips64r6/relocations.s
Modified:
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=209655&r1=209654&r2=209655&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Tue May 27 07:55:40 2014
@@ -102,6 +102,22 @@ static unsigned adjustFixupValue(const M
if (!isIntN(16, Value) && Ctx)
Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
break;
+ case Mips::fixup_MIPS_PC21_S2:
+ Value -= 4;
+ // Forcing a signed division because Value can be negative.
+ Value = (int64_t) Value / 4;
+ // We now check if Value can be encoded as a 21-bit signed immediate.
+ if (!isIntN(21, Value) && Ctx)
+ Ctx->FatalError(Fixup.getLoc(), "out of range PC21 fixup");
+ break;
+ case Mips::fixup_MIPS_PC26_S2:
+ Value -= 4;
+ // Forcing a signed division because Value can be negative.
+ Value = (int64_t) Value / 4;
+ // We now check if Value can be encoded as a 26-bit signed immediate.
+ if (!isIntN(26, Value) && Ctx)
+ Ctx->FatalError(Fixup.getLoc(), "out of range PC26 fixup");
+ break;
}
return Value;
@@ -229,6 +245,8 @@ getFixupKindInfo(MCFixupKind Kind) const
{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
+ { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
@@ -286,6 +304,8 @@ getFixupKindInfo(MCFixupKind Kind) const
{ "fixup_Mips_GOT_LO16", 16, 16, 0 },
{ "fixup_Mips_CALL_HI16", 16, 16, 0 },
{ "fixup_Mips_CALL_LO16", 16, 16, 0 },
+ { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_26_S1", 6, 26, 0 },
{ "fixup_MICROMIPS_HI16", 16, 16, 0 },
{ "fixup_MICROMIPS_LO16", 16, 16, 0 },
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp?rev=209655&r1=209654&r2=209655&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Tue May 27 07:55:40 2014
@@ -193,6 +193,12 @@ unsigned MipsELFObjectWriter::GetRelocTy
case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
Type = ELF::R_MICROMIPS_TLS_TPREL_LO16;
break;
+ case Mips::fixup_MIPS_PC21_S2:
+ Type = ELF::R_MIPS_PC21_S2;
+ break;
+ case Mips::fixup_MIPS_PC26_S2:
+ Type = ELF::R_MIPS_PC26_S2;
+ break;
}
return Type;
}
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h?rev=209655&r1=209654&r2=209655&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h Tue May 27 07:55:40 2014
@@ -128,6 +128,12 @@ namespace Mips {
// resulting in - R_MIPS_CALL_LO16
fixup_Mips_CALL_LO16,
+ // resulting in - R_MIPS_PC21_S2
+ fixup_MIPS_PC21_S2,
+
+ // resulting in - R_MIPS_PC26_S2
+ fixup_MIPS_PC26_S2,
+
// resulting in - R_MICROMIPS_26_S1
fixup_MICROMIPS_26_S1,
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=209655&r1=209654&r2=209655&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Tue May 27 07:55:40 2014
@@ -258,7 +258,9 @@ getBranchTarget21OpValue(const MCInst &M
assert(MO.isExpr() &&
"getBranchTarget21OpValue expects only expressions or immediates");
- // TODO: Push 21 PC fixup.
+ const MCExpr *Expr = MO.getExpr();
+ Fixups.push_back(MCFixup::Create(0, Expr,
+ MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
return 0;
}
@@ -278,7 +280,9 @@ getBranchTarget26OpValue(const MCInst &M
assert(MO.isExpr() &&
"getBranchTarget26OpValue expects only expressions or immediates");
- // TODO: Push 26 PC fixup.
+ const MCExpr *Expr = MO.getExpr();
+ Fixups.push_back(MCFixup::Create(0, Expr,
+ MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
return 0;
}
Added: llvm/trunk/test/MC/Mips/mips32r6/relocations.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/relocations.s?rev=209655&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/relocations.s (added)
+++ llvm/trunk/test/MC/Mips/mips32r6/relocations.s Tue May 27 07:55:40 2014
@@ -0,0 +1,43 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
+# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP
+# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \
+# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
+#------------------------------------------------------------------------------
+# Check that the assembler can handle the documented syntax for fixups.
+#------------------------------------------------------------------------------
+# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
+# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
+# CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2
+# CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2
+# CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
+# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
+#------------------------------------------------------------------------------
+# Check that the appropriate relocations were created.
+#------------------------------------------------------------------------------
+# CHECK-ELF: Relocations [
+# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0
+# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0
+# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0
+# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
+# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF: ]
+
+ beqc $5, $6, bar
+ bnec $5, $6, bar
+ beqzc $9, bar
+ bnezc $9, bar
+ balc bar
+ bc bar
Added: llvm/trunk/test/MC/Mips/mips64r6/relocations.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/relocations.s?rev=209655&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/relocations.s (added)
+++ llvm/trunk/test/MC/Mips/mips64r6/relocations.s Tue May 27 07:55:40 2014
@@ -0,0 +1,43 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \
+# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP
+# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \
+# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
+#------------------------------------------------------------------------------
+# Check that the assembler can handle the documented syntax for fixups.
+#------------------------------------------------------------------------------
+# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
+# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
+# CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2
+# CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2
+# CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
+# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2
+#------------------------------------------------------------------------------
+# Check that the appropriate relocations were created.
+#------------------------------------------------------------------------------
+# CHECK-ELF: Relocations [
+# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0
+# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0
+# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0
+# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
+# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF: ]
+
+ beqc $5, $6, bar
+ bnec $5, $6, bar
+ beqzc $9, bar
+ bnezc $9, bar
+ balc bar
+ bc bar
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