[llvm] r209577 - AArch64/ARM64: move ARM64 into AArch64's place
Tim Northover
tnorthover at apple.com
Sat May 24 05:50:31 PDT 2014
Removed: llvm/trunk/test/CodeGen/ARM64/vaddv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vaddv.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vaddv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vaddv.ll (removed)
@@ -1,245 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
-
-define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
-; CHECK-LABEL: test_vaddv_s8:
-; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.saddv.i32.v8i8(<8 x i8> %a1)
- %0 = trunc i32 %vaddv.i to i8
- ret i8 %0
-}
-
-define signext i16 @test_vaddv_s16(<4 x i16> %a1) {
-; CHECK-LABEL: test_vaddv_s16:
-; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.saddv.i32.v4i16(<4 x i16> %a1)
- %0 = trunc i32 %vaddv.i to i16
- ret i16 %0
-}
-
-define i32 @test_vaddv_s32(<2 x i32> %a1) {
-; CHECK-LABEL: test_vaddv_s32:
-; 2 x i32 is not supported by the ISA, thus, this is a special case
-; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.saddv.i32.v2i32(<2 x i32> %a1)
- ret i32 %vaddv.i
-}
-
-define i64 @test_vaddv_s64(<2 x i64> %a1) {
-; CHECK-LABEL: test_vaddv_s64:
-; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
-; CHECK-NEXT: fmov x0, [[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i64 @llvm.arm64.neon.saddv.i64.v2i64(<2 x i64> %a1)
- ret i64 %vaddv.i
-}
-
-define zeroext i8 @test_vaddv_u8(<8 x i8> %a1) {
-; CHECK-LABEL: test_vaddv_u8:
-; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.uaddv.i32.v8i8(<8 x i8> %a1)
- %0 = trunc i32 %vaddv.i to i8
- ret i8 %0
-}
-
-define i32 @test_vaddv_u8_masked(<8 x i8> %a1) {
-; CHECK-LABEL: test_vaddv_u8_masked:
-; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.uaddv.i32.v8i8(<8 x i8> %a1)
- %0 = and i32 %vaddv.i, 511 ; 0x1ff
- ret i32 %0
-}
-
-define zeroext i16 @test_vaddv_u16(<4 x i16> %a1) {
-; CHECK-LABEL: test_vaddv_u16:
-; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.uaddv.i32.v4i16(<4 x i16> %a1)
- %0 = trunc i32 %vaddv.i to i16
- ret i16 %0
-}
-
-define i32 @test_vaddv_u16_masked(<4 x i16> %a1) {
-; CHECK-LABEL: test_vaddv_u16_masked:
-; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.uaddv.i32.v4i16(<4 x i16> %a1)
- %0 = and i32 %vaddv.i, 3276799 ; 0x31ffff
- ret i32 %0
-}
-
-define i32 @test_vaddv_u32(<2 x i32> %a1) {
-; CHECK-LABEL: test_vaddv_u32:
-; 2 x i32 is not supported by the ISA, thus, this is a special case
-; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.uaddv.i32.v2i32(<2 x i32> %a1)
- ret i32 %vaddv.i
-}
-
-define float @test_vaddv_f32(<2 x float> %a1) {
-; CHECK-LABEL: test_vaddv_f32:
-; CHECK: faddp.2s s0, v0
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call float @llvm.arm64.neon.faddv.f32.v2f32(<2 x float> %a1)
- ret float %vaddv.i
-}
-
-define float @test_vaddv_v4f32(<4 x float> %a1) {
-; CHECK-LABEL: test_vaddv_v4f32:
-; CHECK: faddp.4s [[REGNUM:v[0-9]+]], v0, v0
-; CHECK: faddp.2s s0, [[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call float @llvm.arm64.neon.faddv.f32.v4f32(<4 x float> %a1)
- ret float %vaddv.i
-}
-
-define double @test_vaddv_f64(<2 x double> %a1) {
-; CHECK-LABEL: test_vaddv_f64:
-; CHECK: faddp.2d d0, v0
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call double @llvm.arm64.neon.faddv.f64.v2f64(<2 x double> %a1)
- ret double %vaddv.i
-}
-
-define i64 @test_vaddv_u64(<2 x i64> %a1) {
-; CHECK-LABEL: test_vaddv_u64:
-; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
-; CHECK-NEXT: fmov x0, [[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i64 @llvm.arm64.neon.uaddv.i64.v2i64(<2 x i64> %a1)
- ret i64 %vaddv.i
-}
-
-define <1 x i64> @test_vaddv_u64_to_vec(<2 x i64> %a1) {
-; CHECK-LABEL: test_vaddv_u64_to_vec:
-; CHECK: addp.2d d0, v0
-; CHECK-NOT: fmov
-; CHECK-NOT: ins
-; CHECK: ret
-entry:
- %vaddv.i = tail call i64 @llvm.arm64.neon.uaddv.i64.v2i64(<2 x i64> %a1)
- %vec = insertelement <1 x i64> undef, i64 %vaddv.i, i32 0
- ret <1 x i64> %vec
-}
-
-define signext i8 @test_vaddvq_s8(<16 x i8> %a1) {
-; CHECK-LABEL: test_vaddvq_s8:
-; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.saddv.i32.v16i8(<16 x i8> %a1)
- %0 = trunc i32 %vaddv.i to i8
- ret i8 %0
-}
-
-define signext i16 @test_vaddvq_s16(<8 x i16> %a1) {
-; CHECK-LABEL: test_vaddvq_s16:
-; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.saddv.i32.v8i16(<8 x i16> %a1)
- %0 = trunc i32 %vaddv.i to i16
- ret i16 %0
-}
-
-define i32 @test_vaddvq_s32(<4 x i32> %a1) {
-; CHECK-LABEL: test_vaddvq_s32:
-; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
-; CHECK-NEXT: fmov w0, [[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.saddv.i32.v4i32(<4 x i32> %a1)
- ret i32 %vaddv.i
-}
-
-define zeroext i8 @test_vaddvq_u8(<16 x i8> %a1) {
-; CHECK-LABEL: test_vaddvq_u8:
-; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.uaddv.i32.v16i8(<16 x i8> %a1)
- %0 = trunc i32 %vaddv.i to i8
- ret i8 %0
-}
-
-define zeroext i16 @test_vaddvq_u16(<8 x i16> %a1) {
-; CHECK-LABEL: test_vaddvq_u16:
-; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.uaddv.i32.v8i16(<8 x i16> %a1)
- %0 = trunc i32 %vaddv.i to i16
- ret i16 %0
-}
-
-define i32 @test_vaddvq_u32(<4 x i32> %a1) {
-; CHECK-LABEL: test_vaddvq_u32:
-; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
-; CHECK-NEXT: fmov [[FMOVRES:w[0-9]+]], [[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddv.i = tail call i32 @llvm.arm64.neon.uaddv.i32.v4i32(<4 x i32> %a1)
- ret i32 %vaddv.i
-}
-
-declare i32 @llvm.arm64.neon.uaddv.i32.v4i32(<4 x i32>)
-
-declare i32 @llvm.arm64.neon.uaddv.i32.v8i16(<8 x i16>)
-
-declare i32 @llvm.arm64.neon.uaddv.i32.v16i8(<16 x i8>)
-
-declare i32 @llvm.arm64.neon.saddv.i32.v4i32(<4 x i32>)
-
-declare i32 @llvm.arm64.neon.saddv.i32.v8i16(<8 x i16>)
-
-declare i32 @llvm.arm64.neon.saddv.i32.v16i8(<16 x i8>)
-
-declare i64 @llvm.arm64.neon.uaddv.i64.v2i64(<2 x i64>)
-
-declare i32 @llvm.arm64.neon.uaddv.i32.v2i32(<2 x i32>)
-
-declare i32 @llvm.arm64.neon.uaddv.i32.v4i16(<4 x i16>)
-
-declare i32 @llvm.arm64.neon.uaddv.i32.v8i8(<8 x i8>)
-
-declare i32 @llvm.arm64.neon.saddv.i32.v2i32(<2 x i32>)
-
-declare i64 @llvm.arm64.neon.saddv.i64.v2i64(<2 x i64>)
-
-declare i32 @llvm.arm64.neon.saddv.i32.v4i16(<4 x i16>)
-
-declare i32 @llvm.arm64.neon.saddv.i32.v8i8(<8 x i8>)
-
-declare float @llvm.arm64.neon.faddv.f32.v2f32(<2 x float> %a1)
-declare float @llvm.arm64.neon.faddv.f32.v4f32(<4 x float> %a1)
-declare double @llvm.arm64.neon.faddv.f64.v2f64(<2 x double> %a1)
Removed: llvm/trunk/test/CodeGen/ARM64/variadic-aapcs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/variadic-aapcs.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/variadic-aapcs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/variadic-aapcs.ll (removed)
@@ -1,143 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false < %s | FileCheck %s
-
-%va_list = type {i8*, i8*, i8*, i32, i32}
-
- at var = global %va_list zeroinitializer, align 8
-
-declare void @llvm.va_start(i8*)
-
-define void @test_simple(i32 %n, ...) {
-; CHECK-LABEL: test_simple:
-; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
-; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
-
-; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
-
-; CHECK: stp x1, x2, [sp, #[[GR_BASE:[0-9]+]]]
-; ... omit middle ones ...
-; CHECK: str x7, [sp, #
-
-; CHECK: stp q0, q1, [sp]
-; ... omit middle ones ...
-; CHECK: stp q6, q7, [sp, #
-
-; CHECK: str [[STACK_TOP]], [x[[VA_LIST_HI]], :lo12:var]
-
-; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]]
-; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #56
-; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
-; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
-
-; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp
-; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128
-; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
-
-; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x37
-; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24]
-
-; CHECK: orr [[VR_OFFS:w[0-9]+]], wzr, #0xffffff80
-; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28]
-
- %addr = bitcast %va_list* @var to i8*
- call void @llvm.va_start(i8* %addr)
-
- ret void
-}
-
-define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
-; CHECK-LABEL: test_fewargs:
-; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
-; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
-
-; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
-
-; CHECK: stp x3, x4, [sp, #[[GR_BASE:[0-9]+]]]
-; ... omit middle ones ...
-; CHECK: str x7, [sp, #
-
-; CHECK: stp q1, q2, [sp]
-; ... omit middle ones ...
-; CHECK: str q7, [sp, #
-
-; CHECK: str [[STACK_TOP]], [x[[VA_LIST_HI]], :lo12:var]
-
-; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]]
-; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #40
-; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
-; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
-
-; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp
-; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112
-; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
-
-; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x27
-; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24]
-
-; CHECK: movn [[VR_OFFS:w[0-9]+]], #0x6f
-; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28]
-
- %addr = bitcast %va_list* @var to i8*
- call void @llvm.va_start(i8* %addr)
-
- ret void
-}
-
-define void @test_nospare([8 x i64], [8 x float], ...) {
-; CHECK-LABEL: test_nospare:
-
- %addr = bitcast %va_list* @var to i8*
- call void @llvm.va_start(i8* %addr)
-; CHECK-NOT: sub sp, sp
-; CHECK: mov [[STACK:x[0-9]+]], sp
-; CHECK: str [[STACK]], [{{x[0-9]+}}, :lo12:var]
-
- ret void
-}
-
-; If there are non-variadic arguments on the stack (here two i64s) then the
-; __stack field should point just past them.
-define void @test_offsetstack([10 x i64], [3 x float], ...) {
-; CHECK-LABEL: test_offsetstack:
-; CHECK: sub sp, sp, #80
-; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #96
-; CHECK: str [[STACK_TOP]], [{{x[0-9]+}}, :lo12:var]
-
- %addr = bitcast %va_list* @var to i8*
- call void @llvm.va_start(i8* %addr)
- ret void
-}
-
-declare void @llvm.va_end(i8*)
-
-define void @test_va_end() nounwind {
-; CHECK-LABEL: test_va_end:
-; CHECK-NEXT: BB#0
-
- %addr = bitcast %va_list* @var to i8*
- call void @llvm.va_end(i8* %addr)
-
- ret void
-; CHECK-NEXT: ret
-}
-
-declare void @llvm.va_copy(i8* %dest, i8* %src)
-
- at second_list = global %va_list zeroinitializer
-
-define void @test_va_copy() {
-; CHECK-LABEL: test_va_copy:
- %srcaddr = bitcast %va_list* @var to i8*
- %dstaddr = bitcast %va_list* @second_list to i8*
- call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
-
-; CHECK: add x[[SRC:[0-9]+]], {{x[0-9]+}}, :lo12:var
-
-; CHECK: ldr [[BLOCK:q[0-9]+]], [x[[SRC]]]
-; CHECK: add x[[DST:[0-9]+]], {{x[0-9]+}}, :lo12:second_list
-; CHECK: str [[BLOCK]], [x[[DST]]]
-
-; CHECK: ldr [[BLOCK:q[0-9]+]], [x[[SRC]], #16]
-; CHECK: str [[BLOCK]], [x[[DST]], #16]
- ret void
-; CHECK: ret
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vbitwise.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vbitwise.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vbitwise.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vbitwise.ll (removed)
@@ -1,91 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: rbit_8b:
-;CHECK: rbit.8b
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.rbit.v8i8(<8 x i8> %tmp1)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @rbit_16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: rbit_16b:
-;CHECK: rbit.16b
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.rbit.v16i8(<16 x i8> %tmp1)
- ret <16 x i8> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.rbit.v8i8(<8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.rbit.v16i8(<16 x i8>) nounwind readnone
-
-define <8 x i16> @sxtl8h(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: sxtl8h:
-;CHECK: sshll.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
- ret <8 x i16> %tmp2
-}
-
-define <8 x i16> @uxtl8h(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: uxtl8h:
-;CHECK: ushll.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
- ret <8 x i16> %tmp2
-}
-
-define <4 x i32> @sxtl4s(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: sxtl4s:
-;CHECK: sshll.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
- ret <4 x i32> %tmp2
-}
-
-define <4 x i32> @uxtl4s(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: uxtl4s:
-;CHECK: ushll.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
- ret <4 x i32> %tmp2
-}
-
-define <2 x i64> @sxtl2d(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: sxtl2d:
-;CHECK: sshll.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
- ret <2 x i64> %tmp2
-}
-
-define <2 x i64> @uxtl2d(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: uxtl2d:
-;CHECK: ushll.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
- ret <2 x i64> %tmp2
-}
-
-; Check for incorrect use of vector bic.
-; rdar://11553859
-define void @test_vsliq(i8* nocapture %src, i8* nocapture %dest) nounwind noinline ssp {
-entry:
-; CHECK-LABEL: test_vsliq:
-; CHECK-NOT: bic
-; CHECK: movi.2d [[REG1:v[0-9]+]], #0x0000ff000000ff
-; CHECK: and.16b v{{[0-9]+}}, v{{[0-9]+}}, [[REG1]]
- %0 = bitcast i8* %src to <16 x i8>*
- %1 = load <16 x i8>* %0, align 16
- %and.i = and <16 x i8> %1, <i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0>
- %2 = bitcast <16 x i8> %and.i to <8 x i16>
- %vshl_n = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
- %3 = or <8 x i16> %2, %vshl_n
- %4 = bitcast <8 x i16> %3 to <4 x i32>
- %vshl_n8 = shl <4 x i32> %4, <i32 16, i32 16, i32 16, i32 16>
- %5 = or <4 x i32> %4, %vshl_n8
- %6 = bitcast <4 x i32> %5 to <16 x i8>
- %7 = bitcast i8* %dest to <16 x i8>*
- store <16 x i8> %6, <16 x i8>* %7, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vclz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vclz.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vclz.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vclz.ll (removed)
@@ -1,109 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
-
-define <8 x i8> @test_vclz_u8(<8 x i8> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclz_u8:
- ; CHECK: clz.8b v0, v0
- ; CHECK-NEXT: ret
- %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
- ret <8 x i8> %vclz.i
-}
-
-define <8 x i8> @test_vclz_s8(<8 x i8> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclz_s8:
- ; CHECK: clz.8b v0, v0
- ; CHECK-NEXT: ret
- %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
- ret <8 x i8> %vclz.i
-}
-
-define <4 x i16> @test_vclz_u16(<4 x i16> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclz_u16:
- ; CHECK: clz.4h v0, v0
- ; CHECK-NEXT: ret
- %vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
- ret <4 x i16> %vclz1.i
-}
-
-define <4 x i16> @test_vclz_s16(<4 x i16> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclz_s16:
- ; CHECK: clz.4h v0, v0
- ; CHECK-NEXT: ret
- %vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
- ret <4 x i16> %vclz1.i
-}
-
-define <2 x i32> @test_vclz_u32(<2 x i32> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclz_u32:
- ; CHECK: clz.2s v0, v0
- ; CHECK-NEXT: ret
- %vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
- ret <2 x i32> %vclz1.i
-}
-
-define <2 x i32> @test_vclz_s32(<2 x i32> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclz_s32:
- ; CHECK: clz.2s v0, v0
- ; CHECK-NEXT: ret
- %vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
- ret <2 x i32> %vclz1.i
-}
-
-define <16 x i8> @test_vclzq_u8(<16 x i8> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclzq_u8:
- ; CHECK: clz.16b v0, v0
- ; CHECK-NEXT: ret
- %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
- ret <16 x i8> %vclz.i
-}
-
-define <16 x i8> @test_vclzq_s8(<16 x i8> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclzq_s8:
- ; CHECK: clz.16b v0, v0
- ; CHECK-NEXT: ret
- %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
- ret <16 x i8> %vclz.i
-}
-
-define <8 x i16> @test_vclzq_u16(<8 x i16> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclzq_u16:
- ; CHECK: clz.8h v0, v0
- ; CHECK-NEXT: ret
- %vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
- ret <8 x i16> %vclz1.i
-}
-
-define <8 x i16> @test_vclzq_s16(<8 x i16> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclzq_s16:
- ; CHECK: clz.8h v0, v0
- ; CHECK-NEXT: ret
- %vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
- ret <8 x i16> %vclz1.i
-}
-
-define <4 x i32> @test_vclzq_u32(<4 x i32> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclzq_u32:
- ; CHECK: clz.4s v0, v0
- ; CHECK-NEXT: ret
- %vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
- ret <4 x i32> %vclz1.i
-}
-
-define <4 x i32> @test_vclzq_s32(<4 x i32> %a) nounwind readnone ssp {
- ; CHECK-LABEL: test_vclzq_s32:
- ; CHECK: clz.4s v0, v0
- ; CHECK-NEXT: ret
- %vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
- ret <4 x i32> %vclz1.i
-}
-
-declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
-
-declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
-
-declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
-
-declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
-
-declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
-
-declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vcmp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vcmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vcmp.ll (removed)
@@ -1,236 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-
-define void @fcmltz_4s(<4 x float> %a, <4 x i16>* %p) nounwind {
-;CHECK-LABEL: fcmltz_4s:
-;CHECK: fcmlt.4s [[REG:v[0-9]+]], v0, #0
-;CHECK-NEXT: xtn.4h v[[REG_1:[0-9]+]], [[REG]]
-;CHECK-NEXT: str d[[REG_1]], [x0]
-;CHECK-NEXT: ret
- %tmp = fcmp olt <4 x float> %a, zeroinitializer
- %tmp2 = sext <4 x i1> %tmp to <4 x i16>
- store <4 x i16> %tmp2, <4 x i16>* %p, align 8
- ret void
-}
-
-define <2 x i32> @facge_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: facge_2s:
-;CHECK: facge.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.facge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @facge_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: facge_4s:
-;CHECK: facge.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.facge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @facge_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: facge_2d:
-;CHECK: facge.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.facge.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.facge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.facge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.facge.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <2 x i32> @facgt_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: facgt_2s:
-;CHECK: facgt.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.facgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @facgt_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: facgt_4s:
-;CHECK: facgt.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.facgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @facgt_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: facgt_2d:
-;CHECK: facgt.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.facgt.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.facgt.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.facgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.facgt.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define i32 @facge_s(float %A, float %B) nounwind {
-; CHECK-LABEL: facge_s:
-; CHECK: facge {{s[0-9]+}}, s0, s1
- %mask = call i32 @llvm.arm64.neon.facge.i32.f32(float %A, float %B)
- ret i32 %mask
-}
-
-define i64 @facge_d(double %A, double %B) nounwind {
-; CHECK-LABEL: facge_d:
-; CHECK: facge {{d[0-9]+}}, d0, d1
- %mask = call i64 @llvm.arm64.neon.facge.i64.f64(double %A, double %B)
- ret i64 %mask
-}
-
-declare i64 @llvm.arm64.neon.facge.i64.f64(double, double)
-declare i32 @llvm.arm64.neon.facge.i32.f32(float, float)
-
-define i32 @facgt_s(float %A, float %B) nounwind {
-; CHECK-LABEL: facgt_s:
-; CHECK: facgt {{s[0-9]+}}, s0, s1
- %mask = call i32 @llvm.arm64.neon.facgt.i32.f32(float %A, float %B)
- ret i32 %mask
-}
-
-define i64 @facgt_d(double %A, double %B) nounwind {
-; CHECK-LABEL: facgt_d:
-; CHECK: facgt {{d[0-9]+}}, d0, d1
- %mask = call i64 @llvm.arm64.neon.facgt.i64.f64(double %A, double %B)
- ret i64 %mask
-}
-
-declare i64 @llvm.arm64.neon.facgt.i64.f64(double, double)
-declare i32 @llvm.arm64.neon.facgt.i32.f32(float, float)
-
-define <8 x i8> @cmtst_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: cmtst_8b:
-;CHECK: cmtst.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %commonbits = and <8 x i8> %tmp1, %tmp2
- %mask = icmp ne <8 x i8> %commonbits, zeroinitializer
- %res = sext <8 x i1> %mask to <8 x i8>
- ret <8 x i8> %res
-}
-
-define <16 x i8> @cmtst_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: cmtst_16b:
-;CHECK: cmtst.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %commonbits = and <16 x i8> %tmp1, %tmp2
- %mask = icmp ne <16 x i8> %commonbits, zeroinitializer
- %res = sext <16 x i1> %mask to <16 x i8>
- ret <16 x i8> %res
-}
-
-define <4 x i16> @cmtst_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: cmtst_4h:
-;CHECK: cmtst.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %commonbits = and <4 x i16> %tmp1, %tmp2
- %mask = icmp ne <4 x i16> %commonbits, zeroinitializer
- %res = sext <4 x i1> %mask to <4 x i16>
- ret <4 x i16> %res
-}
-
-define <8 x i16> @cmtst_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: cmtst_8h:
-;CHECK: cmtst.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %commonbits = and <8 x i16> %tmp1, %tmp2
- %mask = icmp ne <8 x i16> %commonbits, zeroinitializer
- %res = sext <8 x i1> %mask to <8 x i16>
- ret <8 x i16> %res
-}
-
-define <2 x i32> @cmtst_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: cmtst_2s:
-;CHECK: cmtst.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %commonbits = and <2 x i32> %tmp1, %tmp2
- %mask = icmp ne <2 x i32> %commonbits, zeroinitializer
- %res = sext <2 x i1> %mask to <2 x i32>
- ret <2 x i32> %res
-}
-
-define <4 x i32> @cmtst_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: cmtst_4s:
-;CHECK: cmtst.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %commonbits = and <4 x i32> %tmp1, %tmp2
- %mask = icmp ne <4 x i32> %commonbits, zeroinitializer
- %res = sext <4 x i1> %mask to <4 x i32>
- ret <4 x i32> %res
-}
-
-define <2 x i64> @cmtst_2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: cmtst_2d:
-;CHECK: cmtst.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %commonbits = and <2 x i64> %tmp1, %tmp2
- %mask = icmp ne <2 x i64> %commonbits, zeroinitializer
- %res = sext <2 x i1> %mask to <2 x i64>
- ret <2 x i64> %res
-}
-
-define <1 x i64> @fcmeq_d(<1 x double> %A, <1 x double> %B) nounwind {
-; CHECK-LABEL: fcmeq_d:
-; CHECK: fcmeq {{d[0-9]+}}, d0, d1
- %tst = fcmp oeq <1 x double> %A, %B
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @fcmge_d(<1 x double> %A, <1 x double> %B) nounwind {
-; CHECK-LABEL: fcmge_d:
-; CHECK: fcmge {{d[0-9]+}}, d0, d1
- %tst = fcmp oge <1 x double> %A, %B
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @fcmle_d(<1 x double> %A, <1 x double> %B) nounwind {
-; CHECK-LABEL: fcmle_d:
-; CHECK: fcmge {{d[0-9]+}}, d1, d0
- %tst = fcmp ole <1 x double> %A, %B
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @fcmgt_d(<1 x double> %A, <1 x double> %B) nounwind {
-; CHECK-LABEL: fcmgt_d:
-; CHECK: fcmgt {{d[0-9]+}}, d0, d1
- %tst = fcmp ogt <1 x double> %A, %B
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @fcmlt_d(<1 x double> %A, <1 x double> %B) nounwind {
-; CHECK-LABEL: fcmlt_d:
-; CHECK: fcmgt {{d[0-9]+}}, d1, d0
- %tst = fcmp olt <1 x double> %A, %B
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @cmnez_d(<1 x i64> %A) nounwind {
-; CHECK-LABEL: cmnez_d:
-; CHECK: cmeq d[[EQ:[0-9]+]], d0, #0
-; CHECK: mvn.8b v0, v[[EQ]]
- %tst = icmp ne <1 x i64> %A, zeroinitializer
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vcnt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vcnt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vcnt.ll (removed)
@@ -1,56 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: cls_8b:
-;CHECK: cls.8b
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.cls.v8i8(<8 x i8> %tmp1)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @cls_16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: cls_16b:
-;CHECK: cls.16b
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.cls.v16i8(<16 x i8> %tmp1)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @cls_4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: cls_4h:
-;CHECK: cls.4h
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.cls.v4i16(<4 x i16> %tmp1)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @cls_8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: cls_8h:
-;CHECK: cls.8h
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.cls.v8i16(<8 x i16> %tmp1)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @cls_2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: cls_2s:
-;CHECK: cls.2s
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.cls.v2i32(<2 x i32> %tmp1)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @cls_4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: cls_4s:
-;CHECK: cls.4s
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.cls.v4i32(<4 x i32> %tmp1)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.cls.v8i8(<8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.cls.v16i8(<16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.cls.v4i16(<4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.cls.v8i16(<8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.cls.v2i32(<2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.cls.v4i32(<4 x i32>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vcombine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vcombine.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vcombine.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vcombine.ll (removed)
@@ -1,17 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-; LowerCONCAT_VECTORS() was reversing the order of two parts.
-; rdar://11558157
-; rdar://11559553
-define <16 x i8> @test(<16 x i8> %q0, <16 x i8> %q1, i8* nocapture %dest) nounwind {
-entry:
-; CHECK-LABEL: test:
-; CHECK: ins.d v0[1], v1[0]
- %0 = bitcast <16 x i8> %q0 to <2 x i64>
- %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> zeroinitializer
- %1 = bitcast <16 x i8> %q1 to <2 x i64>
- %shuffle.i4 = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer
- %shuffle.i3 = shufflevector <1 x i64> %shuffle.i, <1 x i64> %shuffle.i4, <2 x i32> <i32 0, i32 1>
- %2 = bitcast <2 x i64> %shuffle.i3 to <16 x i8>
- ret <16 x i8> %2
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vcvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vcvt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vcvt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vcvt.ll (removed)
@@ -1,686 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <2 x i32> @fcvtas_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtas_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtas.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.fcvtas.v2i32.v2f32(<2 x float> %A)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtas_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtas_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtas.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.fcvtas.v4i32.v4f32(<4 x float> %A)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtas_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtas_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtas.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.fcvtas.v2i64.v2f64(<2 x double> %A)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.fcvtas.v2i32.v2f32(<2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.fcvtas.v4i32.v4f32(<4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind readnone
-
-define <2 x i32> @fcvtau_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtau_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtau.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.fcvtau.v2i32.v2f32(<2 x float> %A)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtau_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtau_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtau.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.fcvtau.v4i32.v4f32(<4 x float> %A)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtau_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtau_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtau.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.fcvtau.v2i64.v2f64(<2 x double> %A)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone
-
-define <2 x i32> @fcvtms_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtms_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtms.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.fcvtms.v2i32.v2f32(<2 x float> %A)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtms_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtms_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtms.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.fcvtms.v4i32.v4f32(<4 x float> %A)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtms_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtms_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtms.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.fcvtms.v2i64.v2f64(<2 x double> %A)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.fcvtms.v2i32.v2f32(<2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.fcvtms.v4i32.v4f32(<4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind readnone
-
-define <2 x i32> @fcvtmu_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtmu_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtmu.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.fcvtmu.v2i32.v2f32(<2 x float> %A)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtmu_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtmu_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtmu.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.fcvtmu.v4i32.v4f32(<4 x float> %A)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtmu_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtmu_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtmu.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.fcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.fcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind readnone
-
-define <2 x i32> @fcvtps_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtps_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtps.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.fcvtps.v2i32.v2f32(<2 x float> %A)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtps_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtps_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtps.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.fcvtps.v4i32.v4f32(<4 x float> %A)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtps_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtps_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtps.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.fcvtps.v2i64.v2f64(<2 x double> %A)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.fcvtps.v2i32.v2f32(<2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.fcvtps.v4i32.v4f32(<4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind readnone
-
-define <2 x i32> @fcvtpu_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtpu_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtpu.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.fcvtpu.v2i32.v2f32(<2 x float> %A)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtpu_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtpu_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtpu.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.fcvtpu.v4i32.v4f32(<4 x float> %A)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtpu_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtpu_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtpu.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.fcvtpu.v2i64.v2f64(<2 x double> %A)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.fcvtpu.v2i32.v2f32(<2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.fcvtpu.v4i32.v4f32(<4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.fcvtpu.v2i64.v2f64(<2 x double>) nounwind readnone
-
-define <2 x i32> @fcvtns_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtns_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtns.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.fcvtns.v2i32.v2f32(<2 x float> %A)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtns_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtns_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtns.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.fcvtns.v4i32.v4f32(<4 x float> %A)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtns_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtns_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtns.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.fcvtns.v2i64.v2f64(<2 x double> %A)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.fcvtns.v2i32.v2f32(<2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.fcvtns.v4i32.v4f32(<4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.fcvtns.v2i64.v2f64(<2 x double>) nounwind readnone
-
-define <2 x i32> @fcvtnu_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtnu_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtnu.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtnu_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtnu_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtnu.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtnu_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtnu_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtnu.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.fcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.fcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.fcvtnu.v2i64.v2f64(<2 x double>) nounwind readnone
-
-define <2 x i32> @fcvtzs_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzs_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = fptosi <2 x float> %A to <2 x i32>
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtzs_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzs_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = fptosi <4 x float> %A to <4 x i32>
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtzs_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzs_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = fptosi <2 x double> %A to <2 x i64>
- ret <2 x i64> %tmp3
-}
-
-
-define <2 x i32> @fcvtzu_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzu_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = fptoui <2 x float> %A to <2 x i32>
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtzu_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzu_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = fptoui <4 x float> %A to <4 x i32>
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtzu_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzu_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = fptoui <2 x double> %A to <2 x i64>
- ret <2 x i64> %tmp3
-}
-
-define <2 x float> @frinta_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frinta_2s:
-;CHECK-NOT: ld1
-;CHECK: frinta.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.round.v2f32(<2 x float> %A)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frinta_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frinta_4s:
-;CHECK-NOT: ld1
-;CHECK: frinta.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x float> @llvm.round.v4f32(<4 x float> %A)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frinta_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frinta_2d:
-;CHECK-NOT: ld1
-;CHECK: frinta.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x double> @llvm.round.v2f64(<2 x double> %A)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.round.v2f32(<2 x float>) nounwind readnone
-declare <4 x float> @llvm.round.v4f32(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.round.v2f64(<2 x double>) nounwind readnone
-
-define <2 x float> @frinti_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frinti_2s:
-;CHECK-NOT: ld1
-;CHECK: frinti.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %A)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frinti_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frinti_4s:
-;CHECK-NOT: ld1
-;CHECK: frinti.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %A)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frinti_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frinti_2d:
-;CHECK-NOT: ld1
-;CHECK: frinti.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %A)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) nounwind readnone
-declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) nounwind readnone
-
-define <2 x float> @frintm_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintm_2s:
-;CHECK-NOT: ld1
-;CHECK: frintm.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.floor.v2f32(<2 x float> %A)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frintm_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintm_4s:
-;CHECK-NOT: ld1
-;CHECK: frintm.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x float> @llvm.floor.v4f32(<4 x float> %A)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frintm_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintm_2d:
-;CHECK-NOT: ld1
-;CHECK: frintm.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x double> @llvm.floor.v2f64(<2 x double> %A)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.floor.v2f32(<2 x float>) nounwind readnone
-declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone
-
-define <2 x float> @frintn_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintn_2s:
-;CHECK-NOT: ld1
-;CHECK: frintn.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.arm64.neon.frintn.v2f32(<2 x float> %A)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frintn_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintn_4s:
-;CHECK-NOT: ld1
-;CHECK: frintn.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x float> @llvm.arm64.neon.frintn.v4f32(<4 x float> %A)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frintn_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintn_2d:
-;CHECK-NOT: ld1
-;CHECK: frintn.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x double> @llvm.arm64.neon.frintn.v2f64(<2 x double> %A)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.frintn.v2f32(<2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.frintn.v4f32(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.frintn.v2f64(<2 x double>) nounwind readnone
-
-define <2 x float> @frintp_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintp_2s:
-;CHECK-NOT: ld1
-;CHECK: frintp.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.ceil.v2f32(<2 x float> %A)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frintp_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintp_4s:
-;CHECK-NOT: ld1
-;CHECK: frintp.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %A)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frintp_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintp_2d:
-;CHECK-NOT: ld1
-;CHECK: frintp.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %A)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone
-declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone
-
-define <2 x float> @frintx_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintx_2s:
-;CHECK-NOT: ld1
-;CHECK: frintx.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.rint.v2f32(<2 x float> %A)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frintx_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintx_4s:
-;CHECK-NOT: ld1
-;CHECK: frintx.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x float> @llvm.rint.v4f32(<4 x float> %A)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frintx_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintx_2d:
-;CHECK-NOT: ld1
-;CHECK: frintx.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x double> @llvm.rint.v2f64(<2 x double> %A)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.rint.v2f32(<2 x float>) nounwind readnone
-declare <4 x float> @llvm.rint.v4f32(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.rint.v2f64(<2 x double>) nounwind readnone
-
-define <2 x float> @frintz_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintz_2s:
-;CHECK-NOT: ld1
-;CHECK: frintz.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.trunc.v2f32(<2 x float> %A)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frintz_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintz_4s:
-;CHECK-NOT: ld1
-;CHECK: frintz.4s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %A)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frintz_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintz_2d:
-;CHECK-NOT: ld1
-;CHECK: frintz.2d v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x double> @llvm.trunc.v2f64(<2 x double> %A)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.trunc.v2f32(<2 x float>) nounwind readnone
-declare <4 x float> @llvm.trunc.v4f32(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone
-
-define <2 x float> @fcvtxn_2s(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtxn_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtxn v0.2s, v0.2d
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @fcvtxn_4s(<2 x float> %ret, <2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtxn_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtxn2 v0.4s, v1.2d
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
- %res = shufflevector <2 x float> %ret, <2 x float> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x float> %res
-}
-
-declare <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
-
-define <2 x i32> @fcvtzsc_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzsc_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2s v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %A, i32 1)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtzsc_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzsc_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.4s v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %A, i32 1)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtzsc_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzsc_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2d v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double> %A, i32 1)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double>, i32) nounwind readnone
-
-define <2 x i32> @fcvtzuc_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzuc_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2s v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %A, i32 1)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @fcvtzuc_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzuc_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.4s v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i32> @llvm.arm64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %A, i32 1)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @fcvtzuc_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzuc_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2d v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i64> @llvm.arm64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double> %A, i32 1)
- ret <2 x i64> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double>, i32) nounwind readnone
-
-define <2 x float> @scvtf_2sc(<2 x i32> %A) nounwind {
-;CHECK-LABEL: scvtf_2sc:
-;CHECK-NOT: ld1
-;CHECK: scvtf.2s v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.arm64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %A, i32 1)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @scvtf_4sc(<4 x i32> %A) nounwind {
-;CHECK-LABEL: scvtf_4sc:
-;CHECK-NOT: ld1
-;CHECK: scvtf.4s v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <4 x float> @llvm.arm64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %A, i32 1)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @scvtf_2dc(<2 x i64> %A) nounwind {
-;CHECK-LABEL: scvtf_2dc:
-;CHECK-NOT: ld1
-;CHECK: scvtf.2d v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x double> @llvm.arm64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %A, i32 1)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
-
-define <2 x float> @ucvtf_2sc(<2 x i32> %A) nounwind {
-;CHECK-LABEL: ucvtf_2sc:
-;CHECK-NOT: ld1
-;CHECK: ucvtf.2s v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x float> @llvm.arm64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %A, i32 1)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @ucvtf_4sc(<4 x i32> %A) nounwind {
-;CHECK-LABEL: ucvtf_4sc:
-;CHECK-NOT: ld1
-;CHECK: ucvtf.4s v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <4 x float> @llvm.arm64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %A, i32 1)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @ucvtf_2dc(<2 x i64> %A) nounwind {
-;CHECK-LABEL: ucvtf_2dc:
-;CHECK-NOT: ld1
-;CHECK: ucvtf.2d v0, v0, #1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x double> @llvm.arm64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %A, i32 1)
- ret <2 x double> %tmp3
-}
-
-
-;CHECK-LABEL: autogen_SD28458:
-;CHECK: fcvt
-;CHECK: ret
-define void @autogen_SD28458() {
- %Tr53 = fptrunc <8 x double> undef to <8 x float>
- store <8 x float> %Tr53, <8 x float>* undef
- ret void
-}
-
-;CHECK-LABEL: autogen_SD19225:
-;CHECK: fcvt
-;CHECK: ret
-define void @autogen_SD19225() {
- %A = load <8 x float>* undef
- %Tr53 = fpext <8 x float> %A to <8 x double>
- store <8 x double> %Tr53, <8 x double>* undef
- ret void
-}
-
-declare <2 x float> @llvm.arm64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vcvt_f.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vcvt_f.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vcvt_f.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vcvt_f.ll (removed)
@@ -1,82 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-; RUN: llc < %s -O0 -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
-; CHECK-LABEL: test_vcvt_f64_f32:
- %vcvt1.i = fpext <2 x float> %x to <2 x double>
-; CHECK: fcvtl v0.2d, v0.2s
- ret <2 x double> %vcvt1.i
-; CHECK: ret
-}
-
-define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp {
-; CHECK-LABEL: test_vcvt_high_f64_f32:
- %cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> <i32 2, i32 3>
- %vcvt1.i = fpext <2 x float> %cvt_in to <2 x double>
-; CHECK: fcvtl2 v0.2d, v0.4s
- ret <2 x double> %vcvt1.i
-; CHECK: ret
-}
-
-define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp {
-; CHECK-LABEL: test_vcvt_f32_f64:
- %vcvt1.i = fptrunc <2 x double> %v to <2 x float>
-; CHECK: fcvtn
- ret <2 x float> %vcvt1.i
-; CHECK: ret
-}
-
-define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
-; CHECK-LABEL: test_vcvt_high_f32_f64:
-
- %cvt = fptrunc <2 x double> %v to <2 x float>
- %vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK: fcvtn2
- ret <4 x float> %vcvt2.i
-; CHECK: ret
-}
-
-define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp {
-; CHECK-LABEL: test_vcvtx_f32_f64:
- %vcvtx1.i = tail call <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
-; CHECK: fcvtxn
- ret <2 x float> %vcvtx1.i
-; CHECK: ret
-}
-
-define <4 x float> @test_vcvtx_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
-; CHECK-LABEL: test_vcvtx_high_f32_f64:
- %vcvtx2.i = tail call <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
- %res = shufflevector <2 x float> %x, <2 x float> %vcvtx2.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK: fcvtxn2
- ret <4 x float> %res
-; CHECK: ret
-}
-
-
-declare <2 x double> @llvm.arm64.neon.vcvthighfp2df(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.vcvtfp2df(<2 x float>) nounwind readnone
-
-declare <2 x float> @llvm.arm64.neon.vcvtdf2fp(<2 x double>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.vcvthighdf2fp(<2 x float>, <2 x double>) nounwind readnone
-
-declare <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
-
-define i16 @to_half(float %in) {
-; CHECK-LABEL: to_half:
-; CHECK: fcvt h[[HALFVAL:[0-9]+]], s0
-; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}}
- %res = call i16 @llvm.convert.to.fp16(float %in)
- ret i16 %res
-}
-
-define float @from_half(i16 %in) {
-; CHECK-LABEL: from_half:
-; CHECK: fmov s[[HALFVAL:[0-9]+]], {{w[0-9]+}}
-; CHECK: fcvt s0, h[[HALFVAL]]
- %res = call float @llvm.convert.from.fp16(i16 %in)
- ret float %res
-}
-
-declare float @llvm.convert.from.fp16(i16) #1
-declare i16 @llvm.convert.to.fp16(float) #1
Removed: llvm/trunk/test/CodeGen/ARM64/vcvt_f32_su32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vcvt_f32_su32.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vcvt_f32_su32.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vcvt_f32_su32.ll (removed)
@@ -1,73 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <2 x float> @ucvt(<2 x i32> %a) nounwind readnone ssp {
-; CHECK-LABEL: ucvt:
-; CHECK: ucvtf.2s v0, v0
-; CHECK: ret
-
- %vcvt.i = uitofp <2 x i32> %a to <2 x float>
- ret <2 x float> %vcvt.i
-}
-
-define <2 x float> @scvt(<2 x i32> %a) nounwind readnone ssp {
-; CHECK-LABEL: scvt:
-; CHECK: scvtf.2s v0, v0
-; CHECK: ret
- %vcvt.i = sitofp <2 x i32> %a to <2 x float>
- ret <2 x float> %vcvt.i
-}
-
-define <4 x float> @ucvtq(<4 x i32> %a) nounwind readnone ssp {
-; CHECK-LABEL: ucvtq:
-; CHECK: ucvtf.4s v0, v0
-; CHECK: ret
- %vcvt.i = uitofp <4 x i32> %a to <4 x float>
- ret <4 x float> %vcvt.i
-}
-
-define <4 x float> @scvtq(<4 x i32> %a) nounwind readnone ssp {
-; CHECK-LABEL: scvtq:
-; CHECK: scvtf.4s v0, v0
-; CHECK: ret
- %vcvt.i = sitofp <4 x i32> %a to <4 x float>
- ret <4 x float> %vcvt.i
-}
-
-define <4 x float> @cvtf16(<4 x i16> %a) nounwind readnone ssp {
-; CHECK-LABEL: cvtf16:
-; CHECK: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: ret
- %vcvt1.i = tail call <4 x float> @llvm.arm64.neon.vcvthf2fp(<4 x i16> %a) nounwind
- ret <4 x float> %vcvt1.i
-}
-
-define <4 x float> @cvtf16_high(<8 x i16> %a) nounwind readnone ssp {
-; CHECK-LABEL: cvtf16_high:
-; CHECK: fcvtl2 v0.4s, v0.8h
-; CHECK-NEXT: ret
- %in = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %vcvt1.i = tail call <4 x float> @llvm.arm64.neon.vcvthf2fp(<4 x i16> %in) nounwind
- ret <4 x float> %vcvt1.i
-}
-
-
-
-define <4 x i16> @cvtf16f32(<4 x float> %a) nounwind readnone ssp {
-; CHECK-LABEL: cvtf16f32:
-; CHECK: fcvtn v0.4h, v0.4s
-; CHECK-NEXT: ret
- %vcvt1.i = tail call <4 x i16> @llvm.arm64.neon.vcvtfp2hf(<4 x float> %a) nounwind
- ret <4 x i16> %vcvt1.i
-}
-
-define <8 x i16> @cvtf16f32_high(<4 x i16> %low, <4 x float> %high_big) {
-; CHECK-LABEL: cvtf16f32_high:
-; CHECK: fcvtn2 v0.8h, v1.4s
-; CHECK-NEXT: ret
- %high = call <4 x i16> @llvm.arm64.neon.vcvtfp2hf(<4 x float> %high_big)
- %res = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-declare <4 x float> @llvm.arm64.neon.vcvthf2fp(<4 x i16>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.vcvtfp2hf(<4 x float>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vcvt_n.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vcvt_n.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vcvt_n.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vcvt_n.ll (removed)
@@ -1,49 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <2 x float> @cvtf32fxpu(<2 x i32> %a) nounwind readnone ssp {
-; CHECK-LABEL: cvtf32fxpu:
-; CHECK: ucvtf.2s v0, v0, #9
-; CHECK: ret
- %vcvt_n1 = tail call <2 x float> @llvm.arm64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %a, i32 9)
- ret <2 x float> %vcvt_n1
-}
-
-define <2 x float> @cvtf32fxps(<2 x i32> %a) nounwind readnone ssp {
-; CHECK-LABEL: cvtf32fxps:
-; CHECK: scvtf.2s v0, v0, #12
-; CHECK: ret
- %vcvt_n1 = tail call <2 x float> @llvm.arm64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %a, i32 12)
- ret <2 x float> %vcvt_n1
-}
-
-define <4 x float> @cvtqf32fxpu(<4 x i32> %a) nounwind readnone ssp {
-; CHECK-LABEL: cvtqf32fxpu:
-; CHECK: ucvtf.4s v0, v0, #18
-; CHECK: ret
- %vcvt_n1 = tail call <4 x float> @llvm.arm64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %a, i32 18)
- ret <4 x float> %vcvt_n1
-}
-
-define <4 x float> @cvtqf32fxps(<4 x i32> %a) nounwind readnone ssp {
-; CHECK-LABEL: cvtqf32fxps:
-; CHECK: scvtf.4s v0, v0, #30
-; CHECK: ret
- %vcvt_n1 = tail call <4 x float> @llvm.arm64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %a, i32 30)
- ret <4 x float> %vcvt_n1
-}
-define <2 x double> @f1(<2 x i64> %a) nounwind readnone ssp {
- %vcvt_n1 = tail call <2 x double> @llvm.arm64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %a, i32 12)
- ret <2 x double> %vcvt_n1
-}
-
-define <2 x double> @f2(<2 x i64> %a) nounwind readnone ssp {
- %vcvt_n1 = tail call <2 x double> @llvm.arm64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %a, i32 9)
- ret <2 x double> %vcvt_n1
-}
-
-declare <4 x float> @llvm.arm64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
-declare <2 x float> @llvm.arm64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
-declare <2 x float> @llvm.arm64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vcvt_su32_f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vcvt_su32_f32.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vcvt_su32_f32.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vcvt_su32_f32.ll (removed)
@@ -1,34 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <2 x i32> @c1(<2 x float> %a) nounwind readnone ssp {
-; CHECK: c1
-; CHECK: fcvtzs.2s v0, v0
-; CHECK: ret
- %vcvt.i = fptosi <2 x float> %a to <2 x i32>
- ret <2 x i32> %vcvt.i
-}
-
-define <2 x i32> @c2(<2 x float> %a) nounwind readnone ssp {
-; CHECK: c2
-; CHECK: fcvtzu.2s v0, v0
-; CHECK: ret
- %vcvt.i = fptoui <2 x float> %a to <2 x i32>
- ret <2 x i32> %vcvt.i
-}
-
-define <4 x i32> @c3(<4 x float> %a) nounwind readnone ssp {
-; CHECK: c3
-; CHECK: fcvtzs.4s v0, v0
-; CHECK: ret
- %vcvt.i = fptosi <4 x float> %a to <4 x i32>
- ret <4 x i32> %vcvt.i
-}
-
-define <4 x i32> @c4(<4 x float> %a) nounwind readnone ssp {
-; CHECK: c4
-; CHECK: fcvtzu.4s v0, v0
-; CHECK: ret
- %vcvt.i = fptoui <4 x float> %a to <4 x i32>
- ret <4 x i32> %vcvt.i
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/vcvtxd_f32_f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vcvtxd_f32_f64.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vcvtxd_f32_f64.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vcvtxd_f32_f64.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-define float @fcvtxn(double %a) {
-; CHECK-LABEL: fcvtxn:
-; CHECK: fcvtxn s0, d0
-; CHECK-NEXT: ret
- %vcvtxd.i = tail call float @llvm.arm64.sisd.fcvtxn(double %a) nounwind
- ret float %vcvtxd.i
-}
-
-declare float @llvm.arm64.sisd.fcvtxn(double) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vecCmpBr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vecCmpBr.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vecCmpBr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vecCmpBr.ll (removed)
@@ -1,207 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
-; ModuleID = 'arm64_vecCmpBr.c'
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
-target triple = "arm64-apple-ios3.0.0"
-
-
-define i32 @anyZero64(<4 x i16> %a) #0 {
-; CHECK: _anyZero64:
-; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
-; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
-; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
-; CHECK: [[LABEL]]:
-; CHECK-NEXT: b _bar
-entry:
- %0 = bitcast <4 x i16> %a to <8 x i8>
- %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
- %1 = trunc i32 %vminv.i to i8
- %tobool = icmp eq i8 %1, 0
- br i1 %tobool, label %if.then, label %return
-
-if.then: ; preds = %entry
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
- br label %return
-
-return: ; preds = %entry, %if.then
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-declare i32 @bar(...) #1
-
-define i32 @anyZero128(<8 x i16> %a) #0 {
-; CHECK: _anyZero128:
-; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
-; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
-; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
-; CHECK: [[LABEL]]:
-; CHECK-NEXT: b _bar
-
-entry:
- %0 = bitcast <8 x i16> %a to <16 x i8>
- %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
- %1 = trunc i32 %vminv.i to i8
- %tobool = icmp eq i8 %1, 0
- br i1 %tobool, label %if.then, label %return
-
-if.then: ; preds = %entry
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
- br label %return
-
-return: ; preds = %entry, %if.then
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @anyNonZero64(<4 x i16> %a) #0 {
-; CHECK: _anyNonZero64:
-; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
-; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
-; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
-; CHECK: [[LABEL]]:
-; CHECK-NEXT: movz w0, #0
-
-entry:
- %0 = bitcast <4 x i16> %a to <8 x i8>
- %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
- %1 = trunc i32 %vmaxv.i to i8
- %tobool = icmp eq i8 %1, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then: ; preds = %entry
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
- br label %return
-
-return: ; preds = %entry, %if.then
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @anyNonZero128(<8 x i16> %a) #0 {
-; CHECK: _anyNonZero128:
-; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
-; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
-; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
-; CHECK: [[LABEL]]:
-; CHECK-NEXT: movz w0, #0
-entry:
- %0 = bitcast <8 x i16> %a to <16 x i8>
- %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
- %1 = trunc i32 %vmaxv.i to i8
- %tobool = icmp eq i8 %1, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then: ; preds = %entry
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
- br label %return
-
-return: ; preds = %entry, %if.then
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @allZero64(<4 x i16> %a) #0 {
-; CHECK: _allZero64:
-; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
-; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
-; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
-; CHECK: [[LABEL]]:
-; CHECK-NEXT: b _bar
-entry:
- %0 = bitcast <4 x i16> %a to <8 x i8>
- %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
- %1 = trunc i32 %vmaxv.i to i8
- %tobool = icmp eq i8 %1, 0
- br i1 %tobool, label %if.then, label %return
-
-if.then: ; preds = %entry
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
- br label %return
-
-return: ; preds = %entry, %if.then
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @allZero128(<8 x i16> %a) #0 {
-; CHECK: _allZero128:
-; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
-; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
-; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
-; CHECK: [[LABEL]]:
-; CHECK-NEXT: b _bar
-entry:
- %0 = bitcast <8 x i16> %a to <16 x i8>
- %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
- %1 = trunc i32 %vmaxv.i to i8
- %tobool = icmp eq i8 %1, 0
- br i1 %tobool, label %if.then, label %return
-
-if.then: ; preds = %entry
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
- br label %return
-
-return: ; preds = %entry, %if.then
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @allNonZero64(<4 x i16> %a) #0 {
-; CHECK: _allNonZero64:
-; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
-; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
-; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
-; CHECK: [[LABEL]]:
-; CHECK-NEXT: movz w0, #0
-entry:
- %0 = bitcast <4 x i16> %a to <8 x i8>
- %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
- %1 = trunc i32 %vminv.i to i8
- %tobool = icmp eq i8 %1, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then: ; preds = %entry
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
- br label %return
-
-return: ; preds = %entry, %if.then
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @allNonZero128(<8 x i16> %a) #0 {
-; CHECK: _allNonZero128:
-; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
-; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
-; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
-; CHECK: [[LABEL]]:
-; CHECK-NEXT: movz w0, #0
-entry:
- %0 = bitcast <8 x i16> %a to <16 x i8>
- %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
- %1 = trunc i32 %vminv.i to i8
- %tobool = icmp eq i8 %1, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then: ; preds = %entry
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
- br label %return
-
-return: ; preds = %entry, %if.then
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-declare i32 @llvm.arm64.neon.umaxv.i32.v16i8(<16 x i8>) #2
-
-declare i32 @llvm.arm64.neon.umaxv.i32.v8i8(<8 x i8>) #2
-
-declare i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8>) #2
-
-declare i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8>) #2
-
-attributes #0 = { nounwind ssp "target-cpu"="cyclone" }
-attributes #1 = { "target-cpu"="cyclone" }
-attributes #2 = { nounwind readnone }
-attributes #3 = { nounwind }
-attributes #4 = { nobuiltin nounwind }
Removed: llvm/trunk/test/CodeGen/ARM64/vecFold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vecFold.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vecFold.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vecFold.ll (removed)
@@ -1,145 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple -o - %s| FileCheck %s
-
-define <16 x i8> @foov16i8(<8 x i16> %a0, <8 x i16> %b0) nounwind readnone ssp {
-; CHECK-LABEL: foov16i8:
- %vshrn_low_shift = lshr <8 x i16> %a0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
- %vshrn_low = trunc <8 x i16> %vshrn_low_shift to <8 x i8>
- %vshrn_high_shift = lshr <8 x i16> %b0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
- %vshrn_high = trunc <8 x i16> %vshrn_high_shift to <8 x i8>
-; CHECK: shrn.8b v0, v0, #5
-; CHECK-NEXT: shrn2.16b v0, v1, #5
-; CHECK-NEXT: ret
- %1 = bitcast <8 x i8> %vshrn_low to <1 x i64>
- %2 = bitcast <8 x i8> %vshrn_high to <1 x i64>
- %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
- %3 = bitcast <2 x i64> %shuffle.i to <16 x i8>
- ret <16 x i8> %3
-}
-
-define <8 x i16> @foov8i16(<4 x i32> %a0, <4 x i32> %b0) nounwind readnone ssp {
-; CHECK-LABEL: foov8i16:
- %vshrn_low_shift = lshr <4 x i32> %a0, <i32 5, i32 5, i32 5, i32 5>
- %vshrn_low = trunc <4 x i32> %vshrn_low_shift to <4 x i16>
- %vshrn_high_shift = lshr <4 x i32> %b0, <i32 5, i32 5, i32 5, i32 5>
- %vshrn_high = trunc <4 x i32> %vshrn_high_shift to <4 x i16>
-; CHECK: shrn.4h v0, v0, #5
-; CHECK-NEXT: shrn2.8h v0, v1, #5
-; CHECK-NEXT: ret
- %1 = bitcast <4 x i16> %vshrn_low to <1 x i64>
- %2 = bitcast <4 x i16> %vshrn_high to <1 x i64>
- %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
- %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
- ret <8 x i16> %3
-}
-
-define <4 x i32> @foov4i32(<2 x i64> %a0, <2 x i64> %b0) nounwind readnone ssp {
-; CHECK-LABEL: foov4i32:
- %vshrn_low_shift = lshr <2 x i64> %a0, <i64 5, i64 5>
- %vshrn_low = trunc <2 x i64> %vshrn_low_shift to <2 x i32>
- %vshrn_high_shift = lshr <2 x i64> %b0, <i64 5, i64 5>
- %vshrn_high = trunc <2 x i64> %vshrn_high_shift to <2 x i32>
-; CHECK: shrn.2s v0, v0, #5
-; CHECK-NEXT: shrn2.4s v0, v1, #5
-; CHECK-NEXT: ret
- %1 = bitcast <2 x i32> %vshrn_low to <1 x i64>
- %2 = bitcast <2 x i32> %vshrn_high to <1 x i64>
- %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
- %3 = bitcast <2 x i64> %shuffle.i to <4 x i32>
- ret <4 x i32> %3
-}
-
-define <8 x i16> @bar(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {
-; CHECK-LABEL: bar:
- %vaddhn2.i = tail call <4 x i16> @llvm.arm64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind
- %vaddhn2.i10 = tail call <4 x i16> @llvm.arm64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind
-; CHECK: addhn.4h v0, v0, v1
-; CHECK-NEXT: addhn2.8h v0, v2, v3
-; CHECK-NEXT: ret
- %1 = bitcast <4 x i16> %vaddhn2.i to <1 x i64>
- %2 = bitcast <4 x i16> %vaddhn2.i10 to <1 x i64>
- %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
- %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
- ret <8 x i16> %3
-}
-
-define <8 x i16> @baz(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {
-; CHECK-LABEL: baz:
- %vaddhn2.i = tail call <4 x i16> @llvm.arm64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind
- %vshrn_high_shift = ashr <4 x i32> %b0, <i32 5, i32 5, i32 5, i32 5>
- %vshrn_high = trunc <4 x i32> %vshrn_high_shift to <4 x i16>
-; CHECK: addhn.4h v0, v0, v1
-; CHECK-NEXT: shrn2.8h v0, v2, #5
-; CHECK-NEXT: ret
- %1 = bitcast <4 x i16> %vaddhn2.i to <1 x i64>
- %2 = bitcast <4 x i16> %vshrn_high to <1 x i64>
- %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
- %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
- ret <8 x i16> %3
-}
-
-define <8 x i16> @raddhn(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {
-; CHECK-LABEL: raddhn:
-entry:
-; CHECK: raddhn.4h v0, v0, v1
-; CHECK-NEXT: raddhn2.8h v0, v2, v3
-; CHECK-NEXT: ret
- %vraddhn2.i = tail call <4 x i16> @llvm.arm64.neon.raddhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind
- %vraddhn2.i10 = tail call <4 x i16> @llvm.arm64.neon.raddhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind
- %0 = bitcast <4 x i16> %vraddhn2.i to <1 x i64>
- %1 = bitcast <4 x i16> %vraddhn2.i10 to <1 x i64>
- %shuffle.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>
- %2 = bitcast <2 x i64> %shuffle.i to <8 x i16>
- ret <8 x i16> %2
-}
-
-define <8 x i16> @vrshrn(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %b0, <8 x i16> %b1) nounwind readnone ssp {
-; CHECK-LABEL: vrshrn:
-; CHECK: rshrn.8b v0, v0, #5
-; CHECK-NEXT: rshrn2.16b v0, v2, #6
-; CHECK-NEXT: ret
- %vrshrn_n1 = tail call <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16> %a0, i32 5)
- %vrshrn_n4 = tail call <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16> %b0, i32 6)
- %1 = bitcast <8 x i8> %vrshrn_n1 to <1 x i64>
- %2 = bitcast <8 x i8> %vrshrn_n4 to <1 x i64>
- %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
- %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
- ret <8 x i16> %3
-}
-
-define <8 x i16> @vrsubhn(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %b0, <8 x i16> %b1) nounwind readnone ssp {
-; CHECK-LABEL: vrsubhn:
-; CHECK: rsubhn.8b v0, v0, v1
-; CHECK: rsubhn2.16b v0, v2, v3
-; CHECK-NEXT: ret
- %vrsubhn2.i = tail call <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) nounwind
- %vrsubhn2.i10 = tail call <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) nounwind
- %1 = bitcast <8 x i8> %vrsubhn2.i to <1 x i64>
- %2 = bitcast <8 x i8> %vrsubhn2.i10 to <1 x i64>
- %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
- %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
- ret <8 x i16> %3
-}
-
-define <8 x i16> @noOpt1(<2 x i32> %a0, <2 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {
-; CHECK-LABEL: noOpt1:
- %vqsub2.i = tail call <2 x i32> @llvm.arm64.neon.sqsub.v2i32(<2 x i32> %a0, <2 x i32> %a1) nounwind
- %vaddhn2.i = tail call <4 x i16> @llvm.arm64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind
-; CHECK: sqsub.2s v0, v0, v1
-; CHECK-NEXT: addhn2.8h v0, v2, v3
- %1 = bitcast <2 x i32> %vqsub2.i to <1 x i64>
- %2 = bitcast <4 x i16> %vaddhn2.i to <1 x i64>
- %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
- %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
- ret <8 x i16> %3
-}
-
-declare <2 x i32> @llvm.arm64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-
-declare <8 x i8> @llvm.arm64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.addhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-
Removed: llvm/trunk/test/CodeGen/ARM64/vector-ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vector-ext.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vector-ext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vector-ext.ll (removed)
@@ -1,16 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-;CHECK: @func30
-;CHECK: ushll.4s v0, v0, #0
-;CHECK: movi.4s v1, #0x1
-;CHECK: and.16b v0, v0, v1
-;CHECK: str q0, [x0]
-;CHECK: ret
-
-%T0_30 = type <4 x i1>
-%T1_30 = type <4 x i32>
-define void @func30(%T0_30 %v0, %T1_30* %p1) {
- %r = zext %T0_30 %v0 to %T1_30
- store %T1_30 %r, %T1_30* %p1
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vector-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vector-imm.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vector-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vector-imm.ll (removed)
@@ -1,134 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
-; CHECK-LABEL: v_orrimm:
-; CHECK-NOT: mov
-; CHECK-NOT: mvn
-; CHECK: orr
- %tmp1 = load <8 x i8>* %A
- %tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
-; CHECK: v_orrimmQ
-; CHECK-NOT: mov
-; CHECK-NOT: mvn
-; CHECK: orr
- %tmp1 = load <16 x i8>* %A
- %tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
- ret <16 x i8> %tmp3
-}
-
-define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
-; CHECK-LABEL: v_bicimm:
-; CHECK-NOT: mov
-; CHECK-NOT: mvn
-; CHECK: bic
- %tmp1 = load <8 x i8>* %A
- %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
-; CHECK-LABEL: v_bicimmQ:
-; CHECK-NOT: mov
-; CHECK-NOT: mvn
-; CHECK: bic
- %tmp1 = load <16 x i8>* %A
- %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
- ret <16 x i8> %tmp3
-}
-
-define <2 x double> @foo(<2 x double> %bar) nounwind {
-; CHECK: foo
-; CHECK: fmov.2d v1, #1.0000000
- %add = fadd <2 x double> %bar, <double 1.0, double 1.0>
- ret <2 x double> %add
-}
-
-define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_4s_imm_t1:
-; CHECK: movi.4s v0, #0x4b
- ret <4 x i32> <i32 75, i32 75, i32 75, i32 75>
-}
-
-define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_4s_imm_t2:
-; CHECK: movi.4s v0, #0x4b, lsl #8
- ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200>
-}
-
-define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_4s_imm_t3:
-; CHECK: movi.4s v0, #0x4b, lsl #16
- ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200>
-}
-
-define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_4s_imm_t4:
-; CHECK: movi.4s v0, #0x4b, lsl #24
- ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
-}
-
-define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_8h_imm_t5:
-; CHECK: movi.8h v0, #0x4b
- ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75>
-}
-
-; rdar://11989841
-define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_8h_imm_t6:
-; CHECK: movi.8h v0, #0x4b, lsl #8
- ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200>
-}
-
-define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_4s_imm_t7:
-; CHECK: movi.4s v0, #0x4b, msl #8
-ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455>
-}
-
-define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_4s_imm_t8:
-; CHECK: movi.4s v0, #0x4b, msl #16
-ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735>
-}
-
-define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_16b_imm_t9:
-; CHECK: movi.16b v0, #0x4b
-ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75,
- i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75>
-}
-
-define <2 x i64> @movi_2d_imm_t10() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_2d_imm_t10:
-; CHECK: movi.2d v0, #0xff00ff00ff00ff
-ret <2 x i64> <i64 71777214294589695, i64 71777214294589695>
-}
-
-define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_4s_imm_t11:
-; CHECK: fmov.4s v0, #-0.32812500
-ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088>
-}
-
-define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp {
-entry:
-; CHECK-LABEL: movi_2d_imm_t12:
-; CHECK: fmov.2d v0, #-0.17187500
-ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664>
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vector-insertion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vector-insertion.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vector-insertion.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vector-insertion.ll (removed)
@@ -1,33 +0,0 @@
-; RUN: llc -march=arm64 -mcpu=generic -arm64-neon-syntax=apple < %s | FileCheck %s
-
-define void @test0f(float* nocapture %x, float %a) #0 {
-entry:
- %0 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %a, i32 0
- %1 = bitcast float* %x to <4 x float>*
- store <4 x float> %0, <4 x float>* %1, align 16
- ret void
-
- ; CHECK-LABEL: test0f
- ; CHECK: movi.2d v[[TEMP:[0-9]+]], #0000000000000000
- ; CHECK: ins.s v[[TEMP]][0], v{{[0-9]+}}[0]
- ; CHECK: str q[[TEMP]], [x0]
- ; CHECK: ret
-
-
-}
-
-
-define void @test1f(float* nocapture %x, float %a) #0 {
-entry:
- %0 = insertelement <4 x float> <float undef, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, float %a, i32 0
- %1 = bitcast float* %x to <4 x float>*
- store <4 x float> %0, <4 x float>* %1, align 16
- ret void
-
- ; CHECK-LABEL: test1f
- ; CHECK: fmov s[[TEMP:[0-9]+]], #1.0000000
- ; CHECK: dup.4s v[[TEMP2:[0-9]+]], v[[TEMP]][0]
- ; CHECK: ins.s v[[TEMP2]][0], v0[0]
- ; CHECK: str q[[TEMP2]], [x0]
- ; CHECK: ret
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vector-ldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vector-ldst.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vector-ldst.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vector-ldst.ll (removed)
@@ -1,601 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
-
-; rdar://9428579
-
-%type1 = type { <16 x i8> }
-%type2 = type { <8 x i8> }
-%type3 = type { <4 x i16> }
-
-
-define hidden fastcc void @t1(%type1** %argtable) nounwind {
-entry:
-; CHECK-LABEL: t1:
-; CHECK: ldr x[[REG:[0-9]+]], [x0]
-; CHECK: str q0, [x[[REG]]]
- %tmp1 = load %type1** %argtable, align 8
- %tmp2 = getelementptr inbounds %type1* %tmp1, i64 0, i32 0
- store <16 x i8> zeroinitializer, <16 x i8>* %tmp2, align 16
- ret void
-}
-
-define hidden fastcc void @t2(%type2** %argtable) nounwind {
-entry:
-; CHECK-LABEL: t2:
-; CHECK: ldr x[[REG:[0-9]+]], [x0]
-; CHECK: str d0, [x[[REG]]]
- %tmp1 = load %type2** %argtable, align 8
- %tmp2 = getelementptr inbounds %type2* %tmp1, i64 0, i32 0
- store <8 x i8> zeroinitializer, <8 x i8>* %tmp2, align 8
- ret void
-}
-
-; add a bunch of tests for rdar://11246289
-
- at globalArray64x2 = common global <2 x i64>* null, align 8
- at globalArray32x4 = common global <4 x i32>* null, align 8
- at globalArray16x8 = common global <8 x i16>* null, align 8
- at globalArray8x16 = common global <16 x i8>* null, align 8
- at globalArray64x1 = common global <1 x i64>* null, align 8
- at globalArray32x2 = common global <2 x i32>* null, align 8
- at globalArray16x4 = common global <4 x i16>* null, align 8
- at globalArray8x8 = common global <8 x i8>* null, align 8
- at floatglobalArray64x2 = common global <2 x double>* null, align 8
- at floatglobalArray32x4 = common global <4 x float>* null, align 8
- at floatglobalArray64x1 = common global <1 x double>* null, align 8
- at floatglobalArray32x2 = common global <2 x float>* null, align 8
-
-define void @fct1_64x2(<2 x i64>* nocapture %array, i64 %offset) nounwind ssp {
-entry:
-; CHECK-LABEL: fct1_64x2:
-; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
-; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
- %arrayidx = getelementptr inbounds <2 x i64>* %array, i64 %offset
- %tmp = load <2 x i64>* %arrayidx, align 16
- %tmp1 = load <2 x i64>** @globalArray64x2, align 8
- %arrayidx1 = getelementptr inbounds <2 x i64>* %tmp1, i64 %offset
- store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16
- ret void
-}
-
-define void @fct2_64x2(<2 x i64>* nocapture %array) nounwind ssp {
-entry:
-; CHECK-LABEL: fct2_64x2:
-; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], #80]
- %arrayidx = getelementptr inbounds <2 x i64>* %array, i64 3
- %tmp = load <2 x i64>* %arrayidx, align 16
- %tmp1 = load <2 x i64>** @globalArray64x2, align 8
- %arrayidx1 = getelementptr inbounds <2 x i64>* %tmp1, i64 5
- store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16
- ret void
-}
-
-define void @fct1_32x4(<4 x i32>* nocapture %array, i64 %offset) nounwind ssp {
-entry:
-; CHECK-LABEL: fct1_32x4:
-; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
-; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
- %arrayidx = getelementptr inbounds <4 x i32>* %array, i64 %offset
- %tmp = load <4 x i32>* %arrayidx, align 16
- %tmp1 = load <4 x i32>** @globalArray32x4, align 8
- %arrayidx1 = getelementptr inbounds <4 x i32>* %tmp1, i64 %offset
- store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16
- ret void
-}
-
-define void @fct2_32x4(<4 x i32>* nocapture %array) nounwind ssp {
-entry:
-; CHECK-LABEL: fct2_32x4:
-; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], #80]
- %arrayidx = getelementptr inbounds <4 x i32>* %array, i64 3
- %tmp = load <4 x i32>* %arrayidx, align 16
- %tmp1 = load <4 x i32>** @globalArray32x4, align 8
- %arrayidx1 = getelementptr inbounds <4 x i32>* %tmp1, i64 5
- store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16
- ret void
-}
-
-define void @fct1_16x8(<8 x i16>* nocapture %array, i64 %offset) nounwind ssp {
-entry:
-; CHECK-LABEL: fct1_16x8:
-; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
-; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
- %arrayidx = getelementptr inbounds <8 x i16>* %array, i64 %offset
- %tmp = load <8 x i16>* %arrayidx, align 16
- %tmp1 = load <8 x i16>** @globalArray16x8, align 8
- %arrayidx1 = getelementptr inbounds <8 x i16>* %tmp1, i64 %offset
- store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16
- ret void
-}
-
-define void @fct2_16x8(<8 x i16>* nocapture %array) nounwind ssp {
-entry:
-; CHECK-LABEL: fct2_16x8:
-; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], #80]
- %arrayidx = getelementptr inbounds <8 x i16>* %array, i64 3
- %tmp = load <8 x i16>* %arrayidx, align 16
- %tmp1 = load <8 x i16>** @globalArray16x8, align 8
- %arrayidx1 = getelementptr inbounds <8 x i16>* %tmp1, i64 5
- store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16
- ret void
-}
-
-define void @fct1_8x16(<16 x i8>* nocapture %array, i64 %offset) nounwind ssp {
-entry:
-; CHECK-LABEL: fct1_8x16:
-; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
-; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
- %arrayidx = getelementptr inbounds <16 x i8>* %array, i64 %offset
- %tmp = load <16 x i8>* %arrayidx, align 16
- %tmp1 = load <16 x i8>** @globalArray8x16, align 8
- %arrayidx1 = getelementptr inbounds <16 x i8>* %tmp1, i64 %offset
- store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16
- ret void
-}
-
-define void @fct2_8x16(<16 x i8>* nocapture %array) nounwind ssp {
-entry:
-; CHECK-LABEL: fct2_8x16:
-; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], #80]
- %arrayidx = getelementptr inbounds <16 x i8>* %array, i64 3
- %tmp = load <16 x i8>* %arrayidx, align 16
- %tmp1 = load <16 x i8>** @globalArray8x16, align 8
- %arrayidx1 = getelementptr inbounds <16 x i8>* %tmp1, i64 5
- store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16
- ret void
-}
-
-define void @fct1_64x1(<1 x i64>* nocapture %array, i64 %offset) nounwind ssp {
-entry:
-; CHECK-LABEL: fct1_64x1:
-; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
-; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
- %arrayidx = getelementptr inbounds <1 x i64>* %array, i64 %offset
- %tmp = load <1 x i64>* %arrayidx, align 8
- %tmp1 = load <1 x i64>** @globalArray64x1, align 8
- %arrayidx1 = getelementptr inbounds <1 x i64>* %tmp1, i64 %offset
- store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8
- ret void
-}
-
-define void @fct2_64x1(<1 x i64>* nocapture %array) nounwind ssp {
-entry:
-; CHECK-LABEL: fct2_64x1:
-; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], #40]
- %arrayidx = getelementptr inbounds <1 x i64>* %array, i64 3
- %tmp = load <1 x i64>* %arrayidx, align 8
- %tmp1 = load <1 x i64>** @globalArray64x1, align 8
- %arrayidx1 = getelementptr inbounds <1 x i64>* %tmp1, i64 5
- store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8
- ret void
-}
-
-define void @fct1_32x2(<2 x i32>* nocapture %array, i64 %offset) nounwind ssp {
-entry:
-; CHECK-LABEL: fct1_32x2:
-; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
-; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
- %arrayidx = getelementptr inbounds <2 x i32>* %array, i64 %offset
- %tmp = load <2 x i32>* %arrayidx, align 8
- %tmp1 = load <2 x i32>** @globalArray32x2, align 8
- %arrayidx1 = getelementptr inbounds <2 x i32>* %tmp1, i64 %offset
- store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8
- ret void
-}
-
-define void @fct2_32x2(<2 x i32>* nocapture %array) nounwind ssp {
-entry:
-; CHECK-LABEL: fct2_32x2:
-; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], #40]
- %arrayidx = getelementptr inbounds <2 x i32>* %array, i64 3
- %tmp = load <2 x i32>* %arrayidx, align 8
- %tmp1 = load <2 x i32>** @globalArray32x2, align 8
- %arrayidx1 = getelementptr inbounds <2 x i32>* %tmp1, i64 5
- store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8
- ret void
-}
-
-define void @fct1_16x4(<4 x i16>* nocapture %array, i64 %offset) nounwind ssp {
-entry:
-; CHECK-LABEL: fct1_16x4:
-; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
-; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
- %arrayidx = getelementptr inbounds <4 x i16>* %array, i64 %offset
- %tmp = load <4 x i16>* %arrayidx, align 8
- %tmp1 = load <4 x i16>** @globalArray16x4, align 8
- %arrayidx1 = getelementptr inbounds <4 x i16>* %tmp1, i64 %offset
- store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8
- ret void
-}
-
-define void @fct2_16x4(<4 x i16>* nocapture %array) nounwind ssp {
-entry:
-; CHECK-LABEL: fct2_16x4:
-; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], #40]
- %arrayidx = getelementptr inbounds <4 x i16>* %array, i64 3
- %tmp = load <4 x i16>* %arrayidx, align 8
- %tmp1 = load <4 x i16>** @globalArray16x4, align 8
- %arrayidx1 = getelementptr inbounds <4 x i16>* %tmp1, i64 5
- store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8
- ret void
-}
-
-define void @fct1_8x8(<8 x i8>* nocapture %array, i64 %offset) nounwind ssp {
-entry:
-; CHECK-LABEL: fct1_8x8:
-; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
-; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
-; CHECK: ldr [[BASE:x[0-9]+]],
-; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]]
- %arrayidx = getelementptr inbounds <8 x i8>* %array, i64 %offset
- %tmp = load <8 x i8>* %arrayidx, align 8
- %tmp1 = load <8 x i8>** @globalArray8x8, align 8
- %arrayidx1 = getelementptr inbounds <8 x i8>* %tmp1, i64 %offset
- store <8 x i8> %tmp, <8 x i8>* %arrayidx1, align 8
- ret void
-}
-
-; Add a bunch of tests for rdar://13258794: Match LDUR/STUR for D and Q
-; registers for unscaled vector accesses
- at str = global [63 x i8] c"Test case for rdar://13258794: LDUR/STUR for D and Q registers\00", align 1
-
-define <1 x i64> @fct0() nounwind readonly ssp {
-entry:
-; CHECK-LABEL: fct0:
-; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
- %0 = load <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8
- ret <1 x i64> %0
-}
-
-define <2 x i32> @fct1() nounwind readonly ssp {
-entry:
-; CHECK-LABEL: fct1:
-; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
- %0 = load <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8
- ret <2 x i32> %0
-}
-
-define <4 x i16> @fct2() nounwind readonly ssp {
-entry:
-; CHECK-LABEL: fct2:
-; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
- %0 = load <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8
- ret <4 x i16> %0
-}
-
-define <8 x i8> @fct3() nounwind readonly ssp {
-entry:
-; CHECK-LABEL: fct3:
-; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
- %0 = load <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8
- ret <8 x i8> %0
-}
-
-define <2 x i64> @fct4() nounwind readonly ssp {
-entry:
-; CHECK-LABEL: fct4:
-; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
- %0 = load <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16
- ret <2 x i64> %0
-}
-
-define <4 x i32> @fct5() nounwind readonly ssp {
-entry:
-; CHECK-LABEL: fct5:
-; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
- %0 = load <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16
- ret <4 x i32> %0
-}
-
-define <8 x i16> @fct6() nounwind readonly ssp {
-entry:
-; CHECK-LABEL: fct6:
-; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
- %0 = load <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16
- ret <8 x i16> %0
-}
-
-define <16 x i8> @fct7() nounwind readonly ssp {
-entry:
-; CHECK-LABEL: fct7:
-; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
- %0 = load <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16
- ret <16 x i8> %0
-}
-
-define void @fct8() nounwind ssp {
-entry:
-; CHECK-LABEL: fct8:
-; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
-; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
- %0 = load <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8
- store <1 x i64> %0, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <1 x i64>*), align 8
- ret void
-}
-
-define void @fct9() nounwind ssp {
-entry:
-; CHECK-LABEL: fct9:
-; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
-; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
- %0 = load <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8
- store <2 x i32> %0, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <2 x i32>*), align 8
- ret void
-}
-
-define void @fct10() nounwind ssp {
-entry:
-; CHECK-LABEL: fct10:
-; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
-; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
- %0 = load <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8
- store <4 x i16> %0, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <4 x i16>*), align 8
- ret void
-}
-
-define void @fct11() nounwind ssp {
-entry:
-; CHECK-LABEL: fct11:
-; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
-; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
- %0 = load <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8
- store <8 x i8> %0, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <8 x i8>*), align 8
- ret void
-}
-
-define void @fct12() nounwind ssp {
-entry:
-; CHECK-LABEL: fct12:
-; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
-; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
- %0 = load <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16
- store <2 x i64> %0, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <2 x i64>*), align 16
- ret void
-}
-
-define void @fct13() nounwind ssp {
-entry:
-; CHECK-LABEL: fct13:
-; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
-; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
- %0 = load <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16
- store <4 x i32> %0, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <4 x i32>*), align 16
- ret void
-}
-
-define void @fct14() nounwind ssp {
-entry:
-; CHECK-LABEL: fct14:
-; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
-; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
- %0 = load <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16
- store <8 x i16> %0, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <8 x i16>*), align 16
- ret void
-}
-
-define void @fct15() nounwind ssp {
-entry:
-; CHECK-LABEL: fct15:
-; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3]
-; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4]
- %0 = load <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16
- store <16 x i8> %0, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <16 x i8>*), align 16
- ret void
-}
-
-; Check the building of vector from a single loaded value.
-; Part of <rdar://problem/14170854>
-;
-; Single loads with immediate offset.
-define <8 x i8> @fct16(i8* nocapture %sp0) {
-; CHECK-LABEL: fct16:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i8* %sp0, i64 1
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %vec = insertelement <8 x i8> undef, i8 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <8 x i8> %vec, %vec
- ret <8 x i8> %vmull.i
-}
-
-define <16 x i8> @fct17(i8* nocapture %sp0) {
-; CHECK-LABEL: fct17:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i8* %sp0, i64 1
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %vec = insertelement <16 x i8> undef, i8 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <16 x i8> %vec, %vec
- ret <16 x i8> %vmull.i
-}
-
-define <4 x i16> @fct18(i16* nocapture %sp0) {
-; CHECK-LABEL: fct18:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i16* %sp0, i64 1
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %vec = insertelement <4 x i16> undef, i16 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <4 x i16> %vec, %vec
- ret <4 x i16> %vmull.i
-}
-
-define <8 x i16> @fct19(i16* nocapture %sp0) {
-; CHECK-LABEL: fct19:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i16* %sp0, i64 1
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %vec = insertelement <8 x i16> undef, i16 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <8 x i16> %vec, %vec
- ret <8 x i16> %vmull.i
-}
-
-define <2 x i32> @fct20(i32* nocapture %sp0) {
-; CHECK-LABEL: fct20:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i32* %sp0, i64 1
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <2 x i32> %vec, %vec
- ret <2 x i32> %vmull.i
-}
-
-define <4 x i32> @fct21(i32* nocapture %sp0) {
-; CHECK-LABEL: fct21:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: mul.4s v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i32* %sp0, i64 1
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %vec = insertelement <4 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <4 x i32> %vec, %vec
- ret <4 x i32> %vmull.i
-}
-
-define <1 x i64> @fct22(i64* nocapture %sp0) {
-; CHECK-LABEL: fct22:
-; CHECK: ldr d0, [x0, #8]
-entry:
- %addr = getelementptr i64* %sp0, i64 1
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %vec = insertelement <1 x i64> undef, i64 %pix_sp0.0.copyload, i32 0
- ret <1 x i64> %vec
-}
-
-define <2 x i64> @fct23(i64* nocapture %sp0) {
-; CHECK-LABEL: fct23:
-; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8]
-entry:
- %addr = getelementptr i64* %sp0, i64 1
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %vec = insertelement <2 x i64> undef, i64 %pix_sp0.0.copyload, i32 0
- ret <2 x i64> %vec
-}
-
-;
-; Single loads with register offset.
-define <8 x i8> @fct24(i8* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct24:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i8* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %vec = insertelement <8 x i8> undef, i8 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <8 x i8> %vec, %vec
- ret <8 x i8> %vmull.i
-}
-
-define <16 x i8> @fct25(i8* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct25:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i8* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %vec = insertelement <16 x i8> undef, i8 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <16 x i8> %vec, %vec
- ret <16 x i8> %vmull.i
-}
-
-define <4 x i16> @fct26(i16* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct26:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i16* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %vec = insertelement <4 x i16> undef, i16 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <4 x i16> %vec, %vec
- ret <4 x i16> %vmull.i
-}
-
-define <8 x i16> @fct27(i16* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct27:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i16* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %vec = insertelement <8 x i16> undef, i16 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <8 x i16> %vec, %vec
- ret <8 x i16> %vmull.i
-}
-
-define <2 x i32> @fct28(i32* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct28:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i32* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <2 x i32> %vec, %vec
- ret <2 x i32> %vmull.i
-}
-
-define <4 x i32> @fct29(i32* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct29:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: mul.4s v0, v[[REGNUM]], v[[REGNUM]]
-entry:
- %addr = getelementptr i32* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %vec = insertelement <4 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
- %vmull.i = mul <4 x i32> %vec, %vec
- ret <4 x i32> %vmull.i
-}
-
-define <1 x i64> @fct30(i64* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct30:
-; CHECK: ldr d0, [x0, x1, lsl #3]
-entry:
- %addr = getelementptr i64* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %vec = insertelement <1 x i64> undef, i64 %pix_sp0.0.copyload, i32 0
- ret <1 x i64> %vec
-}
-
-define <2 x i64> @fct31(i64* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct31:
-; CHECK: ldr d0, [x0, x1, lsl #3]
-entry:
- %addr = getelementptr i64* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %vec = insertelement <2 x i64> undef, i64 %pix_sp0.0.copyload, i32 0
- ret <2 x i64> %vec
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vext.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vext.ll (removed)
@@ -1,464 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
-
-define void @test_vext_s8() nounwind ssp {
- ; CHECK-LABEL: test_vext_s8:
- ; CHECK: {{ext.8.*#1}}
- %xS8x8 = alloca <8 x i8>, align 8
- %__a = alloca <8 x i8>, align 8
- %__b = alloca <8 x i8>, align 8
- %tmp = load <8 x i8>* %xS8x8, align 8
- store <8 x i8> %tmp, <8 x i8>* %__a, align 8
- %tmp1 = load <8 x i8>* %xS8x8, align 8
- store <8 x i8> %tmp1, <8 x i8>* %__b, align 8
- %tmp2 = load <8 x i8>* %__a, align 8
- %tmp3 = load <8 x i8>* %__b, align 8
- %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
- store <8 x i8> %vext, <8 x i8>* %xS8x8, align 8
- ret void
-}
-
-define void @test_vext_u8() nounwind ssp {
- ; CHECK-LABEL: test_vext_u8:
- ; CHECK: {{ext.8.*#2}}
- %xU8x8 = alloca <8 x i8>, align 8
- %__a = alloca <8 x i8>, align 8
- %__b = alloca <8 x i8>, align 8
- %tmp = load <8 x i8>* %xU8x8, align 8
- store <8 x i8> %tmp, <8 x i8>* %__a, align 8
- %tmp1 = load <8 x i8>* %xU8x8, align 8
- store <8 x i8> %tmp1, <8 x i8>* %__b, align 8
- %tmp2 = load <8 x i8>* %__a, align 8
- %tmp3 = load <8 x i8>* %__b, align 8
- %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
- store <8 x i8> %vext, <8 x i8>* %xU8x8, align 8
- ret void
-}
-
-define void @test_vext_p8() nounwind ssp {
- ; CHECK-LABEL: test_vext_p8:
- ; CHECK: {{ext.8.*#3}}
- %xP8x8 = alloca <8 x i8>, align 8
- %__a = alloca <8 x i8>, align 8
- %__b = alloca <8 x i8>, align 8
- %tmp = load <8 x i8>* %xP8x8, align 8
- store <8 x i8> %tmp, <8 x i8>* %__a, align 8
- %tmp1 = load <8 x i8>* %xP8x8, align 8
- store <8 x i8> %tmp1, <8 x i8>* %__b, align 8
- %tmp2 = load <8 x i8>* %__a, align 8
- %tmp3 = load <8 x i8>* %__b, align 8
- %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
- store <8 x i8> %vext, <8 x i8>* %xP8x8, align 8
- ret void
-}
-
-define void @test_vext_s16() nounwind ssp {
- ; CHECK-LABEL: test_vext_s16:
- ; CHECK: {{ext.8.*#2}}
- %xS16x4 = alloca <4 x i16>, align 8
- %__a = alloca <4 x i16>, align 8
- %__b = alloca <4 x i16>, align 8
- %tmp = load <4 x i16>* %xS16x4, align 8
- store <4 x i16> %tmp, <4 x i16>* %__a, align 8
- %tmp1 = load <4 x i16>* %xS16x4, align 8
- store <4 x i16> %tmp1, <4 x i16>* %__b, align 8
- %tmp2 = load <4 x i16>* %__a, align 8
- %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8>
- %tmp4 = load <4 x i16>* %__b, align 8
- %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8>
- %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16>
- %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16>
- %vext = shufflevector <4 x i16> %tmp6, <4 x i16> %tmp7, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
- store <4 x i16> %vext, <4 x i16>* %xS16x4, align 8
- ret void
-}
-
-define void @test_vext_u16() nounwind ssp {
- ; CHECK-LABEL: test_vext_u16:
- ; CHECK: {{ext.8.*#4}}
- %xU16x4 = alloca <4 x i16>, align 8
- %__a = alloca <4 x i16>, align 8
- %__b = alloca <4 x i16>, align 8
- %tmp = load <4 x i16>* %xU16x4, align 8
- store <4 x i16> %tmp, <4 x i16>* %__a, align 8
- %tmp1 = load <4 x i16>* %xU16x4, align 8
- store <4 x i16> %tmp1, <4 x i16>* %__b, align 8
- %tmp2 = load <4 x i16>* %__a, align 8
- %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8>
- %tmp4 = load <4 x i16>* %__b, align 8
- %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8>
- %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16>
- %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16>
- %vext = shufflevector <4 x i16> %tmp6, <4 x i16> %tmp7, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
- store <4 x i16> %vext, <4 x i16>* %xU16x4, align 8
- ret void
-}
-
-define void @test_vext_p16() nounwind ssp {
- ; CHECK-LABEL: test_vext_p16:
- ; CHECK: {{ext.8.*#6}}
- %xP16x4 = alloca <4 x i16>, align 8
- %__a = alloca <4 x i16>, align 8
- %__b = alloca <4 x i16>, align 8
- %tmp = load <4 x i16>* %xP16x4, align 8
- store <4 x i16> %tmp, <4 x i16>* %__a, align 8
- %tmp1 = load <4 x i16>* %xP16x4, align 8
- store <4 x i16> %tmp1, <4 x i16>* %__b, align 8
- %tmp2 = load <4 x i16>* %__a, align 8
- %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8>
- %tmp4 = load <4 x i16>* %__b, align 8
- %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8>
- %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16>
- %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16>
- %vext = shufflevector <4 x i16> %tmp6, <4 x i16> %tmp7, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
- store <4 x i16> %vext, <4 x i16>* %xP16x4, align 8
- ret void
-}
-
-define void @test_vext_s32() nounwind ssp {
- ; CHECK-LABEL: test_vext_s32:
- ; CHECK: {{ext.8.*#4}}
- %xS32x2 = alloca <2 x i32>, align 8
- %__a = alloca <2 x i32>, align 8
- %__b = alloca <2 x i32>, align 8
- %tmp = load <2 x i32>* %xS32x2, align 8
- store <2 x i32> %tmp, <2 x i32>* %__a, align 8
- %tmp1 = load <2 x i32>* %xS32x2, align 8
- store <2 x i32> %tmp1, <2 x i32>* %__b, align 8
- %tmp2 = load <2 x i32>* %__a, align 8
- %tmp3 = bitcast <2 x i32> %tmp2 to <8 x i8>
- %tmp4 = load <2 x i32>* %__b, align 8
- %tmp5 = bitcast <2 x i32> %tmp4 to <8 x i8>
- %tmp6 = bitcast <8 x i8> %tmp3 to <2 x i32>
- %tmp7 = bitcast <8 x i8> %tmp5 to <2 x i32>
- %vext = shufflevector <2 x i32> %tmp6, <2 x i32> %tmp7, <2 x i32> <i32 1, i32 2>
- store <2 x i32> %vext, <2 x i32>* %xS32x2, align 8
- ret void
-}
-
-define void @test_vext_u32() nounwind ssp {
- ; CHECK-LABEL: test_vext_u32:
- ; CHECK: {{ext.8.*#4}}
- %xU32x2 = alloca <2 x i32>, align 8
- %__a = alloca <2 x i32>, align 8
- %__b = alloca <2 x i32>, align 8
- %tmp = load <2 x i32>* %xU32x2, align 8
- store <2 x i32> %tmp, <2 x i32>* %__a, align 8
- %tmp1 = load <2 x i32>* %xU32x2, align 8
- store <2 x i32> %tmp1, <2 x i32>* %__b, align 8
- %tmp2 = load <2 x i32>* %__a, align 8
- %tmp3 = bitcast <2 x i32> %tmp2 to <8 x i8>
- %tmp4 = load <2 x i32>* %__b, align 8
- %tmp5 = bitcast <2 x i32> %tmp4 to <8 x i8>
- %tmp6 = bitcast <8 x i8> %tmp3 to <2 x i32>
- %tmp7 = bitcast <8 x i8> %tmp5 to <2 x i32>
- %vext = shufflevector <2 x i32> %tmp6, <2 x i32> %tmp7, <2 x i32> <i32 1, i32 2>
- store <2 x i32> %vext, <2 x i32>* %xU32x2, align 8
- ret void
-}
-
-define void @test_vext_f32() nounwind ssp {
- ; CHECK-LABEL: test_vext_f32:
- ; CHECK: {{ext.8.*#4}}
- %xF32x2 = alloca <2 x float>, align 8
- %__a = alloca <2 x float>, align 8
- %__b = alloca <2 x float>, align 8
- %tmp = load <2 x float>* %xF32x2, align 8
- store <2 x float> %tmp, <2 x float>* %__a, align 8
- %tmp1 = load <2 x float>* %xF32x2, align 8
- store <2 x float> %tmp1, <2 x float>* %__b, align 8
- %tmp2 = load <2 x float>* %__a, align 8
- %tmp3 = bitcast <2 x float> %tmp2 to <8 x i8>
- %tmp4 = load <2 x float>* %__b, align 8
- %tmp5 = bitcast <2 x float> %tmp4 to <8 x i8>
- %tmp6 = bitcast <8 x i8> %tmp3 to <2 x float>
- %tmp7 = bitcast <8 x i8> %tmp5 to <2 x float>
- %vext = shufflevector <2 x float> %tmp6, <2 x float> %tmp7, <2 x i32> <i32 1, i32 2>
- store <2 x float> %vext, <2 x float>* %xF32x2, align 8
- ret void
-}
-
-define void @test_vext_s64() nounwind ssp {
- ; CHECK-LABEL: test_vext_s64:
- ; CHECK_FIXME: {{ext.8.*#1}}
- ; this just turns into a load of the second element
- %xS64x1 = alloca <1 x i64>, align 8
- %__a = alloca <1 x i64>, align 8
- %__b = alloca <1 x i64>, align 8
- %tmp = load <1 x i64>* %xS64x1, align 8
- store <1 x i64> %tmp, <1 x i64>* %__a, align 8
- %tmp1 = load <1 x i64>* %xS64x1, align 8
- store <1 x i64> %tmp1, <1 x i64>* %__b, align 8
- %tmp2 = load <1 x i64>* %__a, align 8
- %tmp3 = bitcast <1 x i64> %tmp2 to <8 x i8>
- %tmp4 = load <1 x i64>* %__b, align 8
- %tmp5 = bitcast <1 x i64> %tmp4 to <8 x i8>
- %tmp6 = bitcast <8 x i8> %tmp3 to <1 x i64>
- %tmp7 = bitcast <8 x i8> %tmp5 to <1 x i64>
- %vext = shufflevector <1 x i64> %tmp6, <1 x i64> %tmp7, <1 x i32> <i32 1>
- store <1 x i64> %vext, <1 x i64>* %xS64x1, align 8
- ret void
-}
-
-define void @test_vext_u64() nounwind ssp {
- ; CHECK-LABEL: test_vext_u64:
- ; CHECK_FIXME: {{ext.8.*#1}}
- ; this is turned into a simple load of the 2nd element
- %xU64x1 = alloca <1 x i64>, align 8
- %__a = alloca <1 x i64>, align 8
- %__b = alloca <1 x i64>, align 8
- %tmp = load <1 x i64>* %xU64x1, align 8
- store <1 x i64> %tmp, <1 x i64>* %__a, align 8
- %tmp1 = load <1 x i64>* %xU64x1, align 8
- store <1 x i64> %tmp1, <1 x i64>* %__b, align 8
- %tmp2 = load <1 x i64>* %__a, align 8
- %tmp3 = bitcast <1 x i64> %tmp2 to <8 x i8>
- %tmp4 = load <1 x i64>* %__b, align 8
- %tmp5 = bitcast <1 x i64> %tmp4 to <8 x i8>
- %tmp6 = bitcast <8 x i8> %tmp3 to <1 x i64>
- %tmp7 = bitcast <8 x i8> %tmp5 to <1 x i64>
- %vext = shufflevector <1 x i64> %tmp6, <1 x i64> %tmp7, <1 x i32> <i32 1>
- store <1 x i64> %vext, <1 x i64>* %xU64x1, align 8
- ret void
-}
-
-define void @test_vextq_s8() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s8:
- ; CHECK: {{ext.16.*#4}}
- %xS8x16 = alloca <16 x i8>, align 16
- %__a = alloca <16 x i8>, align 16
- %__b = alloca <16 x i8>, align 16
- %tmp = load <16 x i8>* %xS8x16, align 16
- store <16 x i8> %tmp, <16 x i8>* %__a, align 16
- %tmp1 = load <16 x i8>* %xS8x16, align 16
- store <16 x i8> %tmp1, <16 x i8>* %__b, align 16
- %tmp2 = load <16 x i8>* %__a, align 16
- %tmp3 = load <16 x i8>* %__b, align 16
- %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
- store <16 x i8> %vext, <16 x i8>* %xS8x16, align 16
- ret void
-}
-
-define void @test_vextq_u8() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u8:
- ; CHECK: {{ext.16.*#5}}
- %xU8x16 = alloca <16 x i8>, align 16
- %__a = alloca <16 x i8>, align 16
- %__b = alloca <16 x i8>, align 16
- %tmp = load <16 x i8>* %xU8x16, align 16
- store <16 x i8> %tmp, <16 x i8>* %__a, align 16
- %tmp1 = load <16 x i8>* %xU8x16, align 16
- store <16 x i8> %tmp1, <16 x i8>* %__b, align 16
- %tmp2 = load <16 x i8>* %__a, align 16
- %tmp3 = load <16 x i8>* %__b, align 16
- %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
- store <16 x i8> %vext, <16 x i8>* %xU8x16, align 16
- ret void
-}
-
-define void @test_vextq_p8() nounwind ssp {
- ; CHECK-LABEL: test_vextq_p8:
- ; CHECK: {{ext.16.*#6}}
- %xP8x16 = alloca <16 x i8>, align 16
- %__a = alloca <16 x i8>, align 16
- %__b = alloca <16 x i8>, align 16
- %tmp = load <16 x i8>* %xP8x16, align 16
- store <16 x i8> %tmp, <16 x i8>* %__a, align 16
- %tmp1 = load <16 x i8>* %xP8x16, align 16
- store <16 x i8> %tmp1, <16 x i8>* %__b, align 16
- %tmp2 = load <16 x i8>* %__a, align 16
- %tmp3 = load <16 x i8>* %__b, align 16
- %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21>
- store <16 x i8> %vext, <16 x i8>* %xP8x16, align 16
- ret void
-}
-
-define void @test_vextq_s16() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s16:
- ; CHECK: {{ext.16.*#14}}
- %xS16x8 = alloca <8 x i16>, align 16
- %__a = alloca <8 x i16>, align 16
- %__b = alloca <8 x i16>, align 16
- %tmp = load <8 x i16>* %xS16x8, align 16
- store <8 x i16> %tmp, <8 x i16>* %__a, align 16
- %tmp1 = load <8 x i16>* %xS16x8, align 16
- store <8 x i16> %tmp1, <8 x i16>* %__b, align 16
- %tmp2 = load <8 x i16>* %__a, align 16
- %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8>
- %tmp4 = load <8 x i16>* %__b, align 16
- %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8>
- %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16>
- %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16>
- %vext = shufflevector <8 x i16> %tmp6, <8 x i16> %tmp7, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
- store <8 x i16> %vext, <8 x i16>* %xS16x8, align 16
- ret void
-}
-
-define void @test_vextq_u16() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u16:
- ; CHECK: {{ext.16.*#8}}
- %xU16x8 = alloca <8 x i16>, align 16
- %__a = alloca <8 x i16>, align 16
- %__b = alloca <8 x i16>, align 16
- %tmp = load <8 x i16>* %xU16x8, align 16
- store <8 x i16> %tmp, <8 x i16>* %__a, align 16
- %tmp1 = load <8 x i16>* %xU16x8, align 16
- store <8 x i16> %tmp1, <8 x i16>* %__b, align 16
- %tmp2 = load <8 x i16>* %__a, align 16
- %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8>
- %tmp4 = load <8 x i16>* %__b, align 16
- %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8>
- %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16>
- %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16>
- %vext = shufflevector <8 x i16> %tmp6, <8 x i16> %tmp7, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
- store <8 x i16> %vext, <8 x i16>* %xU16x8, align 16
- ret void
-}
-
-define void @test_vextq_p16() nounwind ssp {
- ; CHECK-LABEL: test_vextq_p16:
- ; CHECK: {{ext.16.*#10}}
- %xP16x8 = alloca <8 x i16>, align 16
- %__a = alloca <8 x i16>, align 16
- %__b = alloca <8 x i16>, align 16
- %tmp = load <8 x i16>* %xP16x8, align 16
- store <8 x i16> %tmp, <8 x i16>* %__a, align 16
- %tmp1 = load <8 x i16>* %xP16x8, align 16
- store <8 x i16> %tmp1, <8 x i16>* %__b, align 16
- %tmp2 = load <8 x i16>* %__a, align 16
- %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8>
- %tmp4 = load <8 x i16>* %__b, align 16
- %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8>
- %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16>
- %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16>
- %vext = shufflevector <8 x i16> %tmp6, <8 x i16> %tmp7, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
- store <8 x i16> %vext, <8 x i16>* %xP16x8, align 16
- ret void
-}
-
-define void @test_vextq_s32() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s32:
- ; CHECK: {{ext.16.*#4}}
- %xS32x4 = alloca <4 x i32>, align 16
- %__a = alloca <4 x i32>, align 16
- %__b = alloca <4 x i32>, align 16
- %tmp = load <4 x i32>* %xS32x4, align 16
- store <4 x i32> %tmp, <4 x i32>* %__a, align 16
- %tmp1 = load <4 x i32>* %xS32x4, align 16
- store <4 x i32> %tmp1, <4 x i32>* %__b, align 16
- %tmp2 = load <4 x i32>* %__a, align 16
- %tmp3 = bitcast <4 x i32> %tmp2 to <16 x i8>
- %tmp4 = load <4 x i32>* %__b, align 16
- %tmp5 = bitcast <4 x i32> %tmp4 to <16 x i8>
- %tmp6 = bitcast <16 x i8> %tmp3 to <4 x i32>
- %tmp7 = bitcast <16 x i8> %tmp5 to <4 x i32>
- %vext = shufflevector <4 x i32> %tmp6, <4 x i32> %tmp7, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
- store <4 x i32> %vext, <4 x i32>* %xS32x4, align 16
- ret void
-}
-
-define void @test_vextq_u32() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u32:
- ; CHECK: {{ext.16.*#8}}
- %xU32x4 = alloca <4 x i32>, align 16
- %__a = alloca <4 x i32>, align 16
- %__b = alloca <4 x i32>, align 16
- %tmp = load <4 x i32>* %xU32x4, align 16
- store <4 x i32> %tmp, <4 x i32>* %__a, align 16
- %tmp1 = load <4 x i32>* %xU32x4, align 16
- store <4 x i32> %tmp1, <4 x i32>* %__b, align 16
- %tmp2 = load <4 x i32>* %__a, align 16
- %tmp3 = bitcast <4 x i32> %tmp2 to <16 x i8>
- %tmp4 = load <4 x i32>* %__b, align 16
- %tmp5 = bitcast <4 x i32> %tmp4 to <16 x i8>
- %tmp6 = bitcast <16 x i8> %tmp3 to <4 x i32>
- %tmp7 = bitcast <16 x i8> %tmp5 to <4 x i32>
- %vext = shufflevector <4 x i32> %tmp6, <4 x i32> %tmp7, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
- store <4 x i32> %vext, <4 x i32>* %xU32x4, align 16
- ret void
-}
-
-define void @test_vextq_f32() nounwind ssp {
- ; CHECK-LABEL: test_vextq_f32:
- ; CHECK: {{ext.16.*#12}}
- %xF32x4 = alloca <4 x float>, align 16
- %__a = alloca <4 x float>, align 16
- %__b = alloca <4 x float>, align 16
- %tmp = load <4 x float>* %xF32x4, align 16
- store <4 x float> %tmp, <4 x float>* %__a, align 16
- %tmp1 = load <4 x float>* %xF32x4, align 16
- store <4 x float> %tmp1, <4 x float>* %__b, align 16
- %tmp2 = load <4 x float>* %__a, align 16
- %tmp3 = bitcast <4 x float> %tmp2 to <16 x i8>
- %tmp4 = load <4 x float>* %__b, align 16
- %tmp5 = bitcast <4 x float> %tmp4 to <16 x i8>
- %tmp6 = bitcast <16 x i8> %tmp3 to <4 x float>
- %tmp7 = bitcast <16 x i8> %tmp5 to <4 x float>
- %vext = shufflevector <4 x float> %tmp6, <4 x float> %tmp7, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
- store <4 x float> %vext, <4 x float>* %xF32x4, align 16
- ret void
-}
-
-define void @test_vextq_s64() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s64:
- ; CHECK: {{ext.16.*#8}}
- %xS64x2 = alloca <2 x i64>, align 16
- %__a = alloca <2 x i64>, align 16
- %__b = alloca <2 x i64>, align 16
- %tmp = load <2 x i64>* %xS64x2, align 16
- store <2 x i64> %tmp, <2 x i64>* %__a, align 16
- %tmp1 = load <2 x i64>* %xS64x2, align 16
- store <2 x i64> %tmp1, <2 x i64>* %__b, align 16
- %tmp2 = load <2 x i64>* %__a, align 16
- %tmp3 = bitcast <2 x i64> %tmp2 to <16 x i8>
- %tmp4 = load <2 x i64>* %__b, align 16
- %tmp5 = bitcast <2 x i64> %tmp4 to <16 x i8>
- %tmp6 = bitcast <16 x i8> %tmp3 to <2 x i64>
- %tmp7 = bitcast <16 x i8> %tmp5 to <2 x i64>
- %vext = shufflevector <2 x i64> %tmp6, <2 x i64> %tmp7, <2 x i32> <i32 1, i32 2>
- store <2 x i64> %vext, <2 x i64>* %xS64x2, align 16
- ret void
-}
-
-define void @test_vextq_u64() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u64:
- ; CHECK: {{ext.16.*#8}}
- %xU64x2 = alloca <2 x i64>, align 16
- %__a = alloca <2 x i64>, align 16
- %__b = alloca <2 x i64>, align 16
- %tmp = load <2 x i64>* %xU64x2, align 16
- store <2 x i64> %tmp, <2 x i64>* %__a, align 16
- %tmp1 = load <2 x i64>* %xU64x2, align 16
- store <2 x i64> %tmp1, <2 x i64>* %__b, align 16
- %tmp2 = load <2 x i64>* %__a, align 16
- %tmp3 = bitcast <2 x i64> %tmp2 to <16 x i8>
- %tmp4 = load <2 x i64>* %__b, align 16
- %tmp5 = bitcast <2 x i64> %tmp4 to <16 x i8>
- %tmp6 = bitcast <16 x i8> %tmp3 to <2 x i64>
- %tmp7 = bitcast <16 x i8> %tmp5 to <2 x i64>
- %vext = shufflevector <2 x i64> %tmp6, <2 x i64> %tmp7, <2 x i32> <i32 1, i32 2>
- store <2 x i64> %vext, <2 x i64>* %xU64x2, align 16
- ret void
-}
-
-; shuffles with an undef second operand can use an EXT also so long as the
-; indices wrap and stay sequential.
-; rdar://12051674
-define <16 x i8> @vext1(<16 x i8> %_a) nounwind {
-; CHECK-LABEL: vext1:
-; CHECK: ext.16b v0, v0, v0, #8
- %vext = shufflevector <16 x i8> %_a, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <16 x i8> %vext
-}
-
-; <rdar://problem/12212062>
-define <2 x i64> @vext2(<2 x i64> %p0, <2 x i64> %p1) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: vext2:
-; CHECK: ext.16b v1, v1, v1, #8
-; CHECK: ext.16b v0, v0, v0, #8
-; CHECK: add.2d v0, v0, v1
- %t0 = shufflevector <2 x i64> %p1, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
- %t1 = shufflevector <2 x i64> %p0, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
- %t2 = add <2 x i64> %t1, %t0
- ret <2 x i64> %t2
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vext_reverse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vext_reverse.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vext_reverse.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vext_reverse.ll (removed)
@@ -1,172 +0,0 @@
-; RUN: llc -mtriple=arm64-linux-gnuabi < %s | FileCheck %s
-
-; The following tests is to check the correctness of reversing input operand
-; of vext by enumerating all cases of using two undefs in shuffle masks.
-
-define <4 x i16> @vext_6701_0(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_6701_0:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_6701_12(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_6701_12:
-; CHECK: ext v0.8b, v0.8b, v0.8b, #4
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_6701_13(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_6701_13:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 undef, i32 1>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_6701_14(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_6701_14:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 0, i32 undef>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_6701_23(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_6701_23:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 undef, i32 1>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_6701_24(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_6701_24:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 0, i32 undef>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_6701_34(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_6701_34:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 undef, i32 undef>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_5670_0(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_5670_0:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_5670_12(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_5670_12:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 7, i32 0>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_5670_13(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_5670_13:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 undef, i32 0>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_5670_14(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_5670_14:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 7, i32 undef>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_5670_23(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_5670_23:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 undef, i32 0>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_5670_24(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_5670_24:
-; CHECK: rev32 v0.4h, v1.4h
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 7, i32 undef>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_5670_34(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_5670_34:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 undef, i32 undef>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_7012_0(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_7012_0:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_7012_12(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_7012_12:
-; CHECK: ext v0.8b, v0.8b, v0.8b, #6
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 1, i32 2>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_7012_13(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_7012_13:
-; CHECK: rev32 v0.4h, v0.4h
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 undef, i32 2>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_7012_14(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_7012_14:
-; CHECK: ext v0.8b, v0.8b, v0.8b, #6
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_7012_23(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_7012_23:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 undef, i32 2>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_7012_24(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_7012_24:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 1, i32 undef>
- ret <4 x i16> %x
-}
-
-define <4 x i16> @vext_7012_34(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
-; CHECK-LABEL: vext_7012_34:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
- %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 undef, i32 undef>
- ret <4 x i16> %x
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vfloatintrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vfloatintrinsics.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vfloatintrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vfloatintrinsics.ll (removed)
@@ -1,375 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
-
-;;; Float vectors
-
-%v2f32 = type <2 x float>
-; CHECK: test_v2f32.sqrt:
-define %v2f32 @test_v2f32.sqrt(%v2f32 %a) {
- ; CHECK: fsqrt.2s
- %1 = call %v2f32 @llvm.sqrt.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.powi:
-define %v2f32 @test_v2f32.powi(%v2f32 %a, i32 %b) {
- ; CHECK: pow
- %1 = call %v2f32 @llvm.powi.v2f32(%v2f32 %a, i32 %b)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.sin:
-define %v2f32 @test_v2f32.sin(%v2f32 %a) {
- ; CHECK: sin
- %1 = call %v2f32 @llvm.sin.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.cos:
-define %v2f32 @test_v2f32.cos(%v2f32 %a) {
- ; CHECK: cos
- %1 = call %v2f32 @llvm.cos.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.pow:
-define %v2f32 @test_v2f32.pow(%v2f32 %a, %v2f32 %b) {
- ; CHECK: pow
- %1 = call %v2f32 @llvm.pow.v2f32(%v2f32 %a, %v2f32 %b)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.exp:
-define %v2f32 @test_v2f32.exp(%v2f32 %a) {
- ; CHECK: exp
- %1 = call %v2f32 @llvm.exp.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.exp2:
-define %v2f32 @test_v2f32.exp2(%v2f32 %a) {
- ; CHECK: exp
- %1 = call %v2f32 @llvm.exp2.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.log:
-define %v2f32 @test_v2f32.log(%v2f32 %a) {
- ; CHECK: log
- %1 = call %v2f32 @llvm.log.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.log10:
-define %v2f32 @test_v2f32.log10(%v2f32 %a) {
- ; CHECK: log
- %1 = call %v2f32 @llvm.log10.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.log2:
-define %v2f32 @test_v2f32.log2(%v2f32 %a) {
- ; CHECK: log
- %1 = call %v2f32 @llvm.log2.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.fma:
-define %v2f32 @test_v2f32.fma(%v2f32 %a, %v2f32 %b, %v2f32 %c) {
- ; CHECK: fma
- %1 = call %v2f32 @llvm.fma.v2f32(%v2f32 %a, %v2f32 %b, %v2f32 %c)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.fabs:
-define %v2f32 @test_v2f32.fabs(%v2f32 %a) {
- ; CHECK: fabs
- %1 = call %v2f32 @llvm.fabs.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.floor:
-define %v2f32 @test_v2f32.floor(%v2f32 %a) {
- ; CHECK: frintm.2s
- %1 = call %v2f32 @llvm.floor.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.ceil:
-define %v2f32 @test_v2f32.ceil(%v2f32 %a) {
- ; CHECK: frintp.2s
- %1 = call %v2f32 @llvm.ceil.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.trunc:
-define %v2f32 @test_v2f32.trunc(%v2f32 %a) {
- ; CHECK: frintz.2s
- %1 = call %v2f32 @llvm.trunc.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.rint:
-define %v2f32 @test_v2f32.rint(%v2f32 %a) {
- ; CHECK: frintx.2s
- %1 = call %v2f32 @llvm.rint.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-; CHECK: test_v2f32.nearbyint:
-define %v2f32 @test_v2f32.nearbyint(%v2f32 %a) {
- ; CHECK: frinti.2s
- %1 = call %v2f32 @llvm.nearbyint.v2f32(%v2f32 %a)
- ret %v2f32 %1
-}
-
-declare %v2f32 @llvm.sqrt.v2f32(%v2f32) #0
-declare %v2f32 @llvm.powi.v2f32(%v2f32, i32) #0
-declare %v2f32 @llvm.sin.v2f32(%v2f32) #0
-declare %v2f32 @llvm.cos.v2f32(%v2f32) #0
-declare %v2f32 @llvm.pow.v2f32(%v2f32, %v2f32) #0
-declare %v2f32 @llvm.exp.v2f32(%v2f32) #0
-declare %v2f32 @llvm.exp2.v2f32(%v2f32) #0
-declare %v2f32 @llvm.log.v2f32(%v2f32) #0
-declare %v2f32 @llvm.log10.v2f32(%v2f32) #0
-declare %v2f32 @llvm.log2.v2f32(%v2f32) #0
-declare %v2f32 @llvm.fma.v2f32(%v2f32, %v2f32, %v2f32) #0
-declare %v2f32 @llvm.fabs.v2f32(%v2f32) #0
-declare %v2f32 @llvm.floor.v2f32(%v2f32) #0
-declare %v2f32 @llvm.ceil.v2f32(%v2f32) #0
-declare %v2f32 @llvm.trunc.v2f32(%v2f32) #0
-declare %v2f32 @llvm.rint.v2f32(%v2f32) #0
-declare %v2f32 @llvm.nearbyint.v2f32(%v2f32) #0
-
-;;;
-
-%v4f32 = type <4 x float>
-; CHECK: test_v4f32.sqrt:
-define %v4f32 @test_v4f32.sqrt(%v4f32 %a) {
- ; CHECK: fsqrt.4s
- %1 = call %v4f32 @llvm.sqrt.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.powi:
-define %v4f32 @test_v4f32.powi(%v4f32 %a, i32 %b) {
- ; CHECK: pow
- %1 = call %v4f32 @llvm.powi.v4f32(%v4f32 %a, i32 %b)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.sin:
-define %v4f32 @test_v4f32.sin(%v4f32 %a) {
- ; CHECK: sin
- %1 = call %v4f32 @llvm.sin.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.cos:
-define %v4f32 @test_v4f32.cos(%v4f32 %a) {
- ; CHECK: cos
- %1 = call %v4f32 @llvm.cos.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.pow:
-define %v4f32 @test_v4f32.pow(%v4f32 %a, %v4f32 %b) {
- ; CHECK: pow
- %1 = call %v4f32 @llvm.pow.v4f32(%v4f32 %a, %v4f32 %b)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.exp:
-define %v4f32 @test_v4f32.exp(%v4f32 %a) {
- ; CHECK: exp
- %1 = call %v4f32 @llvm.exp.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.exp2:
-define %v4f32 @test_v4f32.exp2(%v4f32 %a) {
- ; CHECK: exp
- %1 = call %v4f32 @llvm.exp2.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.log:
-define %v4f32 @test_v4f32.log(%v4f32 %a) {
- ; CHECK: log
- %1 = call %v4f32 @llvm.log.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.log10:
-define %v4f32 @test_v4f32.log10(%v4f32 %a) {
- ; CHECK: log
- %1 = call %v4f32 @llvm.log10.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.log2:
-define %v4f32 @test_v4f32.log2(%v4f32 %a) {
- ; CHECK: log
- %1 = call %v4f32 @llvm.log2.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.fma:
-define %v4f32 @test_v4f32.fma(%v4f32 %a, %v4f32 %b, %v4f32 %c) {
- ; CHECK: fma
- %1 = call %v4f32 @llvm.fma.v4f32(%v4f32 %a, %v4f32 %b, %v4f32 %c)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.fabs:
-define %v4f32 @test_v4f32.fabs(%v4f32 %a) {
- ; CHECK: fabs
- %1 = call %v4f32 @llvm.fabs.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.floor:
-define %v4f32 @test_v4f32.floor(%v4f32 %a) {
- ; CHECK: frintm.4s
- %1 = call %v4f32 @llvm.floor.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.ceil:
-define %v4f32 @test_v4f32.ceil(%v4f32 %a) {
- ; CHECK: frintp.4s
- %1 = call %v4f32 @llvm.ceil.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.trunc:
-define %v4f32 @test_v4f32.trunc(%v4f32 %a) {
- ; CHECK: frintz.4s
- %1 = call %v4f32 @llvm.trunc.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.rint:
-define %v4f32 @test_v4f32.rint(%v4f32 %a) {
- ; CHECK: frintx.4s
- %1 = call %v4f32 @llvm.rint.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-; CHECK: test_v4f32.nearbyint:
-define %v4f32 @test_v4f32.nearbyint(%v4f32 %a) {
- ; CHECK: frinti.4s
- %1 = call %v4f32 @llvm.nearbyint.v4f32(%v4f32 %a)
- ret %v4f32 %1
-}
-
-declare %v4f32 @llvm.sqrt.v4f32(%v4f32) #0
-declare %v4f32 @llvm.powi.v4f32(%v4f32, i32) #0
-declare %v4f32 @llvm.sin.v4f32(%v4f32) #0
-declare %v4f32 @llvm.cos.v4f32(%v4f32) #0
-declare %v4f32 @llvm.pow.v4f32(%v4f32, %v4f32) #0
-declare %v4f32 @llvm.exp.v4f32(%v4f32) #0
-declare %v4f32 @llvm.exp2.v4f32(%v4f32) #0
-declare %v4f32 @llvm.log.v4f32(%v4f32) #0
-declare %v4f32 @llvm.log10.v4f32(%v4f32) #0
-declare %v4f32 @llvm.log2.v4f32(%v4f32) #0
-declare %v4f32 @llvm.fma.v4f32(%v4f32, %v4f32, %v4f32) #0
-declare %v4f32 @llvm.fabs.v4f32(%v4f32) #0
-declare %v4f32 @llvm.floor.v4f32(%v4f32) #0
-declare %v4f32 @llvm.ceil.v4f32(%v4f32) #0
-declare %v4f32 @llvm.trunc.v4f32(%v4f32) #0
-declare %v4f32 @llvm.rint.v4f32(%v4f32) #0
-declare %v4f32 @llvm.nearbyint.v4f32(%v4f32) #0
-
-;;; Double vector
-
-%v2f64 = type <2 x double>
-; CHECK: test_v2f64.sqrt:
-define %v2f64 @test_v2f64.sqrt(%v2f64 %a) {
- ; CHECK: fsqrt.2d
- %1 = call %v2f64 @llvm.sqrt.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.powi:
-define %v2f64 @test_v2f64.powi(%v2f64 %a, i32 %b) {
- ; CHECK: pow
- %1 = call %v2f64 @llvm.powi.v2f64(%v2f64 %a, i32 %b)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.sin:
-define %v2f64 @test_v2f64.sin(%v2f64 %a) {
- ; CHECK: sin
- %1 = call %v2f64 @llvm.sin.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.cos:
-define %v2f64 @test_v2f64.cos(%v2f64 %a) {
- ; CHECK: cos
- %1 = call %v2f64 @llvm.cos.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.pow:
-define %v2f64 @test_v2f64.pow(%v2f64 %a, %v2f64 %b) {
- ; CHECK: pow
- %1 = call %v2f64 @llvm.pow.v2f64(%v2f64 %a, %v2f64 %b)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.exp:
-define %v2f64 @test_v2f64.exp(%v2f64 %a) {
- ; CHECK: exp
- %1 = call %v2f64 @llvm.exp.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.exp2:
-define %v2f64 @test_v2f64.exp2(%v2f64 %a) {
- ; CHECK: exp
- %1 = call %v2f64 @llvm.exp2.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.log:
-define %v2f64 @test_v2f64.log(%v2f64 %a) {
- ; CHECK: log
- %1 = call %v2f64 @llvm.log.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.log10:
-define %v2f64 @test_v2f64.log10(%v2f64 %a) {
- ; CHECK: log
- %1 = call %v2f64 @llvm.log10.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.log2:
-define %v2f64 @test_v2f64.log2(%v2f64 %a) {
- ; CHECK: log
- %1 = call %v2f64 @llvm.log2.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.fma:
-define %v2f64 @test_v2f64.fma(%v2f64 %a, %v2f64 %b, %v2f64 %c) {
- ; CHECK: fma
- %1 = call %v2f64 @llvm.fma.v2f64(%v2f64 %a, %v2f64 %b, %v2f64 %c)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.fabs:
-define %v2f64 @test_v2f64.fabs(%v2f64 %a) {
- ; CHECK: fabs
- %1 = call %v2f64 @llvm.fabs.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.floor:
-define %v2f64 @test_v2f64.floor(%v2f64 %a) {
- ; CHECK: frintm.2d
- %1 = call %v2f64 @llvm.floor.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.ceil:
-define %v2f64 @test_v2f64.ceil(%v2f64 %a) {
- ; CHECK: frintp.2d
- %1 = call %v2f64 @llvm.ceil.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.trunc:
-define %v2f64 @test_v2f64.trunc(%v2f64 %a) {
- ; CHECK: frintz.2d
- %1 = call %v2f64 @llvm.trunc.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.rint:
-define %v2f64 @test_v2f64.rint(%v2f64 %a) {
- ; CHECK: frintx.2d
- %1 = call %v2f64 @llvm.rint.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-; CHECK: test_v2f64.nearbyint:
-define %v2f64 @test_v2f64.nearbyint(%v2f64 %a) {
- ; CHECK: frinti.2d
- %1 = call %v2f64 @llvm.nearbyint.v2f64(%v2f64 %a)
- ret %v2f64 %1
-}
-
-declare %v2f64 @llvm.sqrt.v2f64(%v2f64) #0
-declare %v2f64 @llvm.powi.v2f64(%v2f64, i32) #0
-declare %v2f64 @llvm.sin.v2f64(%v2f64) #0
-declare %v2f64 @llvm.cos.v2f64(%v2f64) #0
-declare %v2f64 @llvm.pow.v2f64(%v2f64, %v2f64) #0
-declare %v2f64 @llvm.exp.v2f64(%v2f64) #0
-declare %v2f64 @llvm.exp2.v2f64(%v2f64) #0
-declare %v2f64 @llvm.log.v2f64(%v2f64) #0
-declare %v2f64 @llvm.log10.v2f64(%v2f64) #0
-declare %v2f64 @llvm.log2.v2f64(%v2f64) #0
-declare %v2f64 @llvm.fma.v2f64(%v2f64, %v2f64, %v2f64) #0
-declare %v2f64 @llvm.fabs.v2f64(%v2f64) #0
-declare %v2f64 @llvm.floor.v2f64(%v2f64) #0
-declare %v2f64 @llvm.ceil.v2f64(%v2f64) #0
-declare %v2f64 @llvm.trunc.v2f64(%v2f64) #0
-declare %v2f64 @llvm.rint.v2f64(%v2f64) #0
-declare %v2f64 @llvm.nearbyint.v2f64(%v2f64) #0
-
-attributes #0 = { nounwind readonly }
Removed: llvm/trunk/test/CodeGen/ARM64/vhadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vhadd.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vhadd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vhadd.ll (removed)
@@ -1,249 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @shadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: shadd8b:
-;CHECK: shadd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.shadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @shadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: shadd16b:
-;CHECK: shadd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.shadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @shadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: shadd4h:
-;CHECK: shadd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.shadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @shadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: shadd8h:
-;CHECK: shadd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.shadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @shadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: shadd2s:
-;CHECK: shadd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.shadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @shadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: shadd4s:
-;CHECK: shadd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.shadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <8 x i8> @uhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uhadd8b:
-;CHECK: uhadd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @uhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uhadd16b:
-;CHECK: uhadd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @uhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uhadd4h:
-;CHECK: uhadd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @uhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uhadd8h:
-;CHECK: uhadd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @uhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uhadd2s:
-;CHECK: uhadd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @uhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uhadd4s:
-;CHECK: uhadd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.shadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.shadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.shadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-
-declare <8 x i8> @llvm.arm64.neon.uhadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uhadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uhadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.shadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.shadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.shadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.uhadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.uhadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-define <8 x i8> @srhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: srhadd8b:
-;CHECK: srhadd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.srhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @srhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: srhadd16b:
-;CHECK: srhadd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.srhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @srhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: srhadd4h:
-;CHECK: srhadd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.srhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @srhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: srhadd8h:
-;CHECK: srhadd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.srhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @srhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: srhadd2s:
-;CHECK: srhadd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.srhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @srhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: srhadd4s:
-;CHECK: srhadd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.srhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <8 x i8> @urhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: urhadd8b:
-;CHECK: urhadd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.urhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @urhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: urhadd16b:
-;CHECK: urhadd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.urhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @urhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: urhadd4h:
-;CHECK: urhadd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.urhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @urhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: urhadd8h:
-;CHECK: urhadd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.urhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @urhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: urhadd2s:
-;CHECK: urhadd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.urhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @urhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: urhadd4s:
-;CHECK: urhadd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.urhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.srhadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.srhadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.srhadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-
-declare <8 x i8> @llvm.arm64.neon.urhadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.urhadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.urhadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.srhadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.srhadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.urhadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.urhadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vhsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vhsub.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vhsub.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vhsub.ll (removed)
@@ -1,125 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: shsub8b:
-;CHECK: shsub.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.shsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @shsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: shsub16b:
-;CHECK: shsub.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.shsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @shsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: shsub4h:
-;CHECK: shsub.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.shsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @shsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: shsub8h:
-;CHECK: shsub.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.shsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @shsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: shsub2s:
-;CHECK: shsub.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.shsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @shsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: shsub4s:
-;CHECK: shsub.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.shsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <8 x i8> @uhsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uhsub8b:
-;CHECK: uhsub.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uhsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @uhsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uhsub16b:
-;CHECK: uhsub.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uhsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @uhsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uhsub4h:
-;CHECK: uhsub.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uhsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @uhsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uhsub8h:
-;CHECK: uhsub.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uhsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @uhsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uhsub2s:
-;CHECK: uhsub.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uhsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @uhsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uhsub4s:
-;CHECK: uhsub.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uhsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.shsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.shsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.shsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-
-declare <8 x i8> @llvm.arm64.neon.uhsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uhsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uhsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.shsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.shsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.shsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.uhsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.uhsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.uhsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/virtual_base.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/virtual_base.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/virtual_base.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/virtual_base.ll (removed)
@@ -1,51 +0,0 @@
-; RUN: llc < %s -O3 -march arm64 | FileCheck %s
-; <rdar://13463602>
-
-%struct.Counter_Struct = type { i64, i64 }
-%struct.Bicubic_Patch_Struct = type { %struct.Method_Struct*, i32, %struct.Object_Struct*, %struct.Texture_Struct*, %struct.Interior_Struct*, %struct.Object_Struct*, %struct.Object_Struct*, %struct.Bounding_Box_Struct, i64, i32, i32, i32, [4 x [4 x [3 x double]]], [3 x double], double, double, %struct.Bezier_Node_Struct* }
-%struct.Method_Struct = type { i32 (%struct.Object_Struct*, %struct.Ray_Struct*, %struct.istack_struct*)*, i32 (double*, %struct.Object_Struct*)*, void (double*, %struct.Object_Struct*, %struct.istk_entry*)*, i8* (%struct.Object_Struct*)*, void (%struct.Object_Struct*, double*, %struct.Transform_Struct*)*, void (%struct.Object_Struct*, double*, %struct.Transform_Struct*)*, void (%struct.Object_Struct*, double*, %struct.Transform_Struct*)*, void (%struct.Object_Struct*, %struct.Transform_Struct*)*, void (%struct.Object_Struct*)*, void (%struct.Object_Struct*)* }
-%struct.Object_Struct = type { %struct.Method_Struct*, i32, %struct.Object_Struct*, %struct.Texture_Struct*, %struct.Interior_Struct*, %struct.Object_Struct*, %struct.Object_Struct*, %struct.Bounding_Box_Struct, i64 }
-%struct.Texture_Struct = type { i16, i16, i16, i32, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, %union.anon.9, %struct.Texture_Struct*, %struct.Pigment_Struct*, %struct.Tnormal_Struct*, %struct.Finish_Struct*, %struct.Texture_Struct*, i32 }
-%struct.Warps_Struct = type { i16, %struct.Warps_Struct* }
-%struct.Pattern_Struct = type { i16, i16, i16, i32, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, %union.anon.6 }
-%struct.Blend_Map_Struct = type { i16, i16, i16, i64, %struct.Blend_Map_Entry* }
-%struct.Blend_Map_Entry = type { float, i8, %union.anon }
-%union.anon = type { [2 x double], [8 x i8] }
-%union.anon.6 = type { %struct.anon.7 }
-%struct.anon.7 = type { float, [3 x double] }
-%union.anon.9 = type { %struct.anon.10 }
-%struct.anon.10 = type { float, [3 x double] }
-%struct.Pigment_Struct = type { i16, i16, i16, i32, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, %union.anon.0, [5 x float] }
-%union.anon.0 = type { %struct.anon }
-%struct.anon = type { float, [3 x double] }
-%struct.Tnormal_Struct = type { i16, i16, i16, i32, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, %union.anon.3, float }
-%union.anon.3 = type { %struct.anon.4 }
-%struct.anon.4 = type { float, [3 x double] }
-%struct.Finish_Struct = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, [3 x float], [3 x float] }
-%struct.Interior_Struct = type { i64, i32, float, float, float, float, float, %struct.Media_Struct* }
-%struct.Media_Struct = type { i32, i32, i32, i32, i32, double, double, i32, i32, i32, i32, [5 x float], [5 x float], [5 x float], [5 x float], double, double, double, double*, %struct.Pigment_Struct*, %struct.Media_Struct* }
-%struct.Bounding_Box_Struct = type { [3 x float], [3 x float] }
-%struct.Ray_Struct = type { [3 x double], [3 x double], i32, [100 x %struct.Interior_Struct*] }
-%struct.istack_struct = type { %struct.istack_struct*, %struct.istk_entry*, i32 }
-%struct.istk_entry = type { double, [3 x double], [3 x double], %struct.Object_Struct*, i32, i32, double, double, i8* }
-%struct.Transform_Struct = type { [4 x [4 x double]], [4 x [4 x double]] }
-%struct.Bezier_Node_Struct = type { i32, [3 x double], double, i32, i8* }
-
-define void @Precompute_Patch_Values(%struct.Bicubic_Patch_Struct* %Shape) {
-; CHECK: Precompute_Patch_Values
-; CHECK: ldr [[VAL:x[0-9]+]], [x0, #288]
-; CHECK-NEXT: str [[VAL]], [sp, #232]
-; CHECK-NEXT: ldr [[VAL2:q[0-9]+]], [x0, #272]
-; CHECK-NEXT: stur [[VAL2]], {{\[}}sp, #216]
-entry:
- %Control_Points = alloca [16 x [3 x double]], align 8
- %arraydecay5.3.1 = getelementptr inbounds [16 x [3 x double]]* %Control_Points, i64 0, i64 9, i64 0
- %tmp14 = bitcast double* %arraydecay5.3.1 to i8*
- %arraydecay11.3.1 = getelementptr inbounds %struct.Bicubic_Patch_Struct* %Shape, i64 0, i32 12, i64 1, i64 3, i64 0
- %tmp15 = bitcast double* %arraydecay11.3.1 to i8*
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 24, i32 1, i1 false)
- ret void
-}
-
-; Function Attrs: nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1)
Removed: llvm/trunk/test/CodeGen/ARM64/vmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vmax.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vmax.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vmax.ll (removed)
@@ -1,679 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @smax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: smax_8b:
-;CHECK: smax.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.smax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @smax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: smax_16b:
-;CHECK: smax.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.smax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @smax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: smax_4h:
-;CHECK: smax.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.smax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @smax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: smax_8h:
-;CHECK: smax.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.smax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @smax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: smax_2s:
-;CHECK: smax.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.smax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @smax_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: smax_4s:
-;CHECK: smax.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.smax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.smax.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.smax.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.smax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.smax.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.smax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-define <8 x i8> @umax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: umax_8b:
-;CHECK: umax.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.umax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @umax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: umax_16b:
-;CHECK: umax.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.umax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @umax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: umax_4h:
-;CHECK: umax.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.umax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @umax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: umax_8h:
-;CHECK: umax.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.umax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @umax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: umax_2s:
-;CHECK: umax.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.umax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @umax_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: umax_4s:
-;CHECK: umax.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.umax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.umax.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.umax.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.umax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.umax.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.umax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-define <8 x i8> @smin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: smin_8b:
-;CHECK: smin.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.smin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @smin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: smin_16b:
-;CHECK: smin.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.smin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @smin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: smin_4h:
-;CHECK: smin.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.smin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @smin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: smin_8h:
-;CHECK: smin.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.smin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @smin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: smin_2s:
-;CHECK: smin.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.smin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @smin_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: smin_4s:
-;CHECK: smin.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.smin.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.smin.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.smin.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.smin.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.smin.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.smin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-define <8 x i8> @umin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: umin_8b:
-;CHECK: umin.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.umin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @umin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: umin_16b:
-;CHECK: umin.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.umin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @umin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: umin_4h:
-;CHECK: umin.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.umin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @umin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: umin_8h:
-;CHECK: umin.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.umin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @umin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: umin_2s:
-;CHECK: umin.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.umin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @umin_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: umin_4s:
-;CHECK: umin.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.umin.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.umin.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.umin.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.umin.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.umin.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.umin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @smaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: smaxp_8b:
-;CHECK: smaxp.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.smaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @smaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: smaxp_16b:
-;CHECK: smaxp.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.smaxp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @smaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: smaxp_4h:
-;CHECK: smaxp.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.smaxp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @smaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: smaxp_8h:
-;CHECK: smaxp.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.smaxp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @smaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: smaxp_2s:
-;CHECK: smaxp.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.smaxp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @smaxp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: smaxp_4s:
-;CHECK: smaxp.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.smaxp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.smaxp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.smaxp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.smaxp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.smaxp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.smaxp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.smaxp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-define <8 x i8> @umaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: umaxp_8b:
-;CHECK: umaxp.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.umaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @umaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: umaxp_16b:
-;CHECK: umaxp.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.umaxp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @umaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: umaxp_4h:
-;CHECK: umaxp.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.umaxp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @umaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: umaxp_8h:
-;CHECK: umaxp.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.umaxp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @umaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: umaxp_2s:
-;CHECK: umaxp.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.umaxp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @umaxp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: umaxp_4s:
-;CHECK: umaxp.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.umaxp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.umaxp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.umaxp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.umaxp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.umaxp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.umaxp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.umaxp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @sminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sminp_8b:
-;CHECK: sminp.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @sminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sminp_16b:
-;CHECK: sminp.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sminp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @sminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sminp_4h:
-;CHECK: sminp.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sminp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @sminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sminp_8h:
-;CHECK: sminp.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sminp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @sminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sminp_2s:
-;CHECK: sminp.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sminp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @sminp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sminp_4s:
-;CHECK: sminp.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sminp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.sminp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.sminp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sminp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sminp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sminp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sminp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-define <8 x i8> @uminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uminp_8b:
-;CHECK: uminp.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @uminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uminp_16b:
-;CHECK: uminp.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uminp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @uminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uminp_4h:
-;CHECK: uminp.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uminp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @uminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uminp_8h:
-;CHECK: uminp.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uminp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @uminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uminp_2s:
-;CHECK: uminp.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uminp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @uminp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uminp_4s:
-;CHECK: uminp.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uminp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.uminp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.uminp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uminp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.uminp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uminp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.uminp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-define <2 x float> @fmax_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fmax_2s:
-;CHECK: fmax.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.fmax.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @fmax_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fmax_4s:
-;CHECK: fmax.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.fmax.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @fmax_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fmax_2d:
-;CHECK: fmax.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.fmax.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.fmax.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fmax.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.fmax.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <2 x float> @fmaxp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fmaxp_2s:
-;CHECK: fmaxp.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.fmaxp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @fmaxp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fmaxp_4s:
-;CHECK: fmaxp.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.fmaxp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @fmaxp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fmaxp_2d:
-;CHECK: fmaxp.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.fmaxp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.fmaxp.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fmaxp.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.fmaxp.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <2 x float> @fmin_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fmin_2s:
-;CHECK: fmin.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.fmin.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @fmin_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fmin_4s:
-;CHECK: fmin.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.fmin.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @fmin_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fmin_2d:
-;CHECK: fmin.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.fmin.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.fmin.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fmin.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.fmin.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <2 x float> @fminp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fminp_2s:
-;CHECK: fminp.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.fminp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @fminp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fminp_4s:
-;CHECK: fminp.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.fminp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @fminp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fminp_2d:
-;CHECK: fminp.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.fminp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.fminp.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fminp.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.fminp.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <2 x float> @fminnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fminnmp_2s:
-;CHECK: fminnmp.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.fminnmp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @fminnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fminnmp_4s:
-;CHECK: fminnmp.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.fminnmp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @fminnmp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fminnmp_2d:
-;CHECK: fminnmp.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.fminnmp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.fminnmp.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fminnmp.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.fminnmp.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <2 x float> @fmaxnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fmaxnmp_2s:
-;CHECK: fmaxnmp.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.fmaxnmp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @fmaxnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fmaxnmp_4s:
-;CHECK: fmaxnmp.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.fmaxnmp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @fmaxnmp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fmaxnmp_2d:
-;CHECK: fmaxnmp.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.fmaxnmp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.fmaxnmp.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fmaxnmp.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.fmaxnmp.v2f64(<2 x double>, <2 x double>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vminmaxnm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vminmaxnm.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vminmaxnm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vminmaxnm.ll (removed)
@@ -1,68 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <2 x float> @f1(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
-; CHECK: fmaxnm.2s v0, v0, v1
-; CHECK: ret
- %vmaxnm2.i = tail call <2 x float> @llvm.arm64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind
- ret <2 x float> %vmaxnm2.i
-}
-
-define <4 x float> @f2(<4 x float> %a, <4 x float> %b) nounwind readnone ssp {
-; CHECK: fmaxnm.4s v0, v0, v1
-; CHECK: ret
- %vmaxnm2.i = tail call <4 x float> @llvm.arm64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %b) nounwind
- ret <4 x float> %vmaxnm2.i
-}
-
-define <2 x double> @f3(<2 x double> %a, <2 x double> %b) nounwind readnone ssp {
-; CHECK: fmaxnm.2d v0, v0, v1
-; CHECK: ret
- %vmaxnm2.i = tail call <2 x double> @llvm.arm64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> %b) nounwind
- ret <2 x double> %vmaxnm2.i
-}
-
-define <2 x float> @f4(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
-; CHECK: fminnm.2s v0, v0, v1
-; CHECK: ret
- %vminnm2.i = tail call <2 x float> @llvm.arm64.neon.fminnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind
- ret <2 x float> %vminnm2.i
-}
-
-define <4 x float> @f5(<4 x float> %a, <4 x float> %b) nounwind readnone ssp {
-; CHECK: fminnm.4s v0, v0, v1
-; CHECK: ret
- %vminnm2.i = tail call <4 x float> @llvm.arm64.neon.fminnm.v4f32(<4 x float> %a, <4 x float> %b) nounwind
- ret <4 x float> %vminnm2.i
-}
-
-define <2 x double> @f6(<2 x double> %a, <2 x double> %b) nounwind readnone ssp {
-; CHECK: fminnm.2d v0, v0, v1
-; CHECK: ret
- %vminnm2.i = tail call <2 x double> @llvm.arm64.neon.fminnm.v2f64(<2 x double> %a, <2 x double> %b) nounwind
- ret <2 x double> %vminnm2.i
-}
-
-declare <2 x double> @llvm.arm64.neon.fminnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x float> @llvm.arm64.neon.fminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.fmaxnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x float> @llvm.arm64.neon.fmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
-
-
-define double @test_fmaxnmv(<2 x double> %in) {
-; CHECK-LABEL: test_fmaxnmv:
-; CHECK: fmaxnmp.2d d0, v0
- %max = call double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)
- ret double %max
-}
-
-define double @test_fminnmv(<2 x double> %in) {
-; CHECK-LABEL: test_fminnmv:
-; CHECK: fminnmp.2d d0, v0
- %min = call double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double> %in)
- ret double %min
-}
-
-declare double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double>)
-declare double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double>)
Removed: llvm/trunk/test/CodeGen/ARM64/vmovn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vmovn.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vmovn.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vmovn.ll (removed)
@@ -1,242 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @xtn8b(<8 x i16> %A) nounwind {
-;CHECK-LABEL: xtn8b:
-;CHECK-NOT: ld1
-;CHECK: xtn.8b v0, v0
-;CHECK-NEXT: ret
- %tmp3 = trunc <8 x i16> %A to <8 x i8>
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @xtn4h(<4 x i32> %A) nounwind {
-;CHECK-LABEL: xtn4h:
-;CHECK-NOT: ld1
-;CHECK: xtn.4h v0, v0
-;CHECK-NEXT: ret
- %tmp3 = trunc <4 x i32> %A to <4 x i16>
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @xtn2s(<2 x i64> %A) nounwind {
-;CHECK-LABEL: xtn2s:
-;CHECK-NOT: ld1
-;CHECK: xtn.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = trunc <2 x i64> %A to <2 x i32>
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @xtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
-;CHECK-LABEL: xtn2_16b:
-;CHECK-NOT: ld1
-;CHECK: xtn2.16b v0, v1
-;CHECK-NEXT: ret
- %tmp3 = trunc <8 x i16> %A to <8 x i8>
- %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @xtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
-;CHECK-LABEL: xtn2_8h:
-;CHECK-NOT: ld1
-;CHECK: xtn2.8h v0, v1
-;CHECK-NEXT: ret
- %tmp3 = trunc <4 x i32> %A to <4 x i16>
- %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @xtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
-;CHECK-LABEL: xtn2_4s:
-;CHECK-NOT: ld1
-;CHECK: xtn2.4s v0, v1
-;CHECK-NEXT: ret
- %tmp3 = trunc <2 x i64> %A to <2 x i32>
- %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
-
-define <8 x i8> @sqxtn8b(<8 x i16> %A) nounwind {
-;CHECK-LABEL: sqxtn8b:
-;CHECK-NOT: ld1
-;CHECK: sqxtn.8b v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtn.v8i8(<8 x i16> %A)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqxtn4h(<4 x i32> %A) nounwind {
-;CHECK-LABEL: sqxtn4h:
-;CHECK-NOT: ld1
-;CHECK: sqxtn.4h v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtn.v4i16(<4 x i32> %A)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqxtn2s(<2 x i64> %A) nounwind {
-;CHECK-LABEL: sqxtn2s:
-;CHECK-NOT: ld1
-;CHECK: sqxtn.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtn.v2i32(<2 x i64> %A)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
-;CHECK-LABEL: sqxtn2_16b:
-;CHECK-NOT: ld1
-;CHECK: sqxtn2.16b v0, v1
-;CHECK-NEXT: ret
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtn.v8i8(<8 x i16> %A)
- %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @sqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
-;CHECK-LABEL: sqxtn2_8h:
-;CHECK-NOT: ld1
-;CHECK: sqxtn2.8h v0, v1
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtn.v4i16(<4 x i32> %A)
- %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @sqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
-;CHECK-LABEL: sqxtn2_4s:
-;CHECK-NOT: ld1
-;CHECK: sqxtn2.4s v0, v1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtn.v2i32(<2 x i64> %A)
- %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
-
-declare <8 x i8> @llvm.arm64.neon.sqxtn.v8i8(<8 x i16>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqxtn.v4i16(<4 x i32>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqxtn.v2i32(<2 x i64>) nounwind readnone
-
-define <8 x i8> @uqxtn8b(<8 x i16> %A) nounwind {
-;CHECK-LABEL: uqxtn8b:
-;CHECK-NOT: ld1
-;CHECK: uqxtn.8b v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqxtn.v8i8(<8 x i16> %A)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @uqxtn4h(<4 x i32> %A) nounwind {
-;CHECK-LABEL: uqxtn4h:
-;CHECK-NOT: ld1
-;CHECK: uqxtn.4h v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqxtn.v4i16(<4 x i32> %A)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @uqxtn2s(<2 x i64> %A) nounwind {
-;CHECK-LABEL: uqxtn2s:
-;CHECK-NOT: ld1
-;CHECK: uqxtn.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqxtn.v2i32(<2 x i64> %A)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @uqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
-;CHECK-LABEL: uqxtn2_16b:
-;CHECK-NOT: ld1
-;CHECK: uqxtn2.16b v0, v1
-;CHECK-NEXT: ret
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqxtn.v8i8(<8 x i16> %A)
- %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @uqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
-;CHECK-LABEL: uqxtn2_8h:
-;CHECK-NOT: ld1
-;CHECK: uqxtn2.8h v0, v1
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqxtn.v4i16(<4 x i32> %A)
- %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @uqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
-;CHECK-LABEL: uqxtn2_4s:
-;CHECK-NOT: ld1
-;CHECK: uqxtn2.4s v0, v1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqxtn.v2i32(<2 x i64> %A)
- %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
-
-declare <8 x i8> @llvm.arm64.neon.uqxtn.v8i8(<8 x i16>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uqxtn.v4i16(<4 x i32>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uqxtn.v2i32(<2 x i64>) nounwind readnone
-
-define <8 x i8> @sqxtun8b(<8 x i16> %A) nounwind {
-;CHECK-LABEL: sqxtun8b:
-;CHECK-NOT: ld1
-;CHECK: sqxtun.8b v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtun.v8i8(<8 x i16> %A)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqxtun4h(<4 x i32> %A) nounwind {
-;CHECK-LABEL: sqxtun4h:
-;CHECK-NOT: ld1
-;CHECK: sqxtun.4h v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtun.v4i16(<4 x i32> %A)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqxtun2s(<2 x i64> %A) nounwind {
-;CHECK-LABEL: sqxtun2s:
-;CHECK-NOT: ld1
-;CHECK: sqxtun.2s v0, v0
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtun.v2i32(<2 x i64> %A)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqxtun2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
-;CHECK-LABEL: sqxtun2_16b:
-;CHECK-NOT: ld1
-;CHECK: sqxtun2.16b v0, v1
-;CHECK-NEXT: ret
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtun.v8i8(<8 x i16> %A)
- %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @sqxtun2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
-;CHECK-LABEL: sqxtun2_8h:
-;CHECK-NOT: ld1
-;CHECK: sqxtun2.8h v0, v1
-;CHECK-NEXT: ret
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtun.v4i16(<4 x i32> %A)
- %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @sqxtun2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
-;CHECK-LABEL: sqxtun2_4s:
-;CHECK-NOT: ld1
-;CHECK: sqxtun2.4s v0, v1
-;CHECK-NEXT: ret
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtun.v2i32(<2 x i64> %A)
- %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
-
-declare <8 x i8> @llvm.arm64.neon.sqxtun.v8i8(<8 x i16>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqxtun.v4i16(<4 x i32>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqxtun.v2i32(<2 x i64>) nounwind readnone
-
Removed: llvm/trunk/test/CodeGen/ARM64/vmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vmul.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vmul.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vmul.ll (removed)
@@ -1,2036 +0,0 @@
-; RUN: llc -asm-verbose=false < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-
-define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: smull8h:
-;CHECK: smull.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @smull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: smull4s:
-;CHECK: smull.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @smull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: smull2d:
-;CHECK: smull.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
-
-define <8 x i16> @umull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: umull8h:
-;CHECK: umull.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.umull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @umull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: umull4s:
-;CHECK: umull.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @umull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: umull2d:
-;CHECK: umull.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i16> @llvm.arm64.neon.umull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
-
-define <4 x i32> @sqdmull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqdmull4s:
-;CHECK: sqdmull.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sqdmull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqdmull2d:
-;CHECK: sqdmull.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-define <4 x i32> @sqdmull2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqdmull2_4s:
-;CHECK: sqdmull2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sqdmull2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqdmull2_2d:
-;CHECK: sqdmull2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp3 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-
-declare <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
-
-define <8 x i16> @pmull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: pmull8h:
-;CHECK: pmull.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.pmull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-declare <8 x i16> @llvm.arm64.neon.pmull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
-
-define <4 x i16> @sqdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqdmulh_4h:
-;CHECK: sqdmulh.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @sqdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqdmulh_8h:
-;CHECK: sqdmulh.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @sqdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqdmulh_2s:
-;CHECK: sqdmulh.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @sqdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqdmulh_4s:
-;CHECK: sqdmulh.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define i32 @sqdmulh_1s(i32* %A, i32* %B) nounwind {
-;CHECK-LABEL: sqdmulh_1s:
-;CHECK: sqdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
- %tmp1 = load i32* %A
- %tmp2 = load i32* %B
- %tmp3 = call i32 @llvm.arm64.neon.sqdmulh.i32(i32 %tmp1, i32 %tmp2)
- ret i32 %tmp3
-}
-
-declare <4 x i16> @llvm.arm64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare i32 @llvm.arm64.neon.sqdmulh.i32(i32, i32) nounwind readnone
-
-define <4 x i16> @sqrdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqrdmulh_4h:
-;CHECK: sqrdmulh.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @sqrdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqrdmulh_8h:
-;CHECK: sqrdmulh.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @sqrdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqrdmulh_2s:
-;CHECK: sqrdmulh.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @sqrdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqrdmulh_4s:
-;CHECK: sqrdmulh.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define i32 @sqrdmulh_1s(i32* %A, i32* %B) nounwind {
-;CHECK-LABEL: sqrdmulh_1s:
-;CHECK: sqrdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
- %tmp1 = load i32* %A
- %tmp2 = load i32* %B
- %tmp3 = call i32 @llvm.arm64.neon.sqrdmulh.i32(i32 %tmp1, i32 %tmp2)
- ret i32 %tmp3
-}
-
-declare <4 x i16> @llvm.arm64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare i32 @llvm.arm64.neon.sqrdmulh.i32(i32, i32) nounwind readnone
-
-define <2 x float> @fmulx_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fmulx_2s:
-;CHECK: fmulx.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.fmulx.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @fmulx_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fmulx_4s:
-;CHECK: fmulx.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.fmulx.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @fmulx_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fmulx_2d:
-;CHECK: fmulx.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.fmulx.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.fmulx.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fmulx.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.fmulx.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <4 x i32> @smlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: smlal4s:
-;CHECK: smlal.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @smlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: smlal2d:
-;CHECK: smlal.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <4 x i32> @smlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: smlsl4s:
-;CHECK: smlsl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp5 = sub <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @smlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: smlsl2d:
-;CHECK: smlsl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp5 = sub <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-declare <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
-declare <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
-declare <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
-declare <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
-
-define <4 x i32> @sqdmlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sqdmlal4s:
-;CHECK: sqdmlal.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp5 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @sqdmlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sqdmlal2d:
-;CHECK: sqdmlal.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp5 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
- ret <2 x i64> %tmp5
-}
-
-define <4 x i32> @sqdmlal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sqdmlal2_4s:
-;CHECK: sqdmlal2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp5 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @sqdmlal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sqdmlal2_2d:
-;CHECK: sqdmlal2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp5 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
- ret <2 x i64> %tmp5
-}
-
-define <4 x i32> @sqdmlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sqdmlsl4s:
-;CHECK: sqdmlsl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp5 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @sqdmlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sqdmlsl2d:
-;CHECK: sqdmlsl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp5 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
- ret <2 x i64> %tmp5
-}
-
-define <4 x i32> @sqdmlsl2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sqdmlsl2_4s:
-;CHECK: sqdmlsl2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp5 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @sqdmlsl2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sqdmlsl2_2d:
-;CHECK: sqdmlsl2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp5 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
- ret <2 x i64> %tmp5
-}
-
-define <4 x i32> @umlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: umlal4s:
-;CHECK: umlal.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @umlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: umlal2d:
-;CHECK: umlal.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <4 x i32> @umlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: umlsl4s:
-;CHECK: umlsl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp5 = sub <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @umlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: umlsl2d:
-;CHECK: umlsl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp5 = sub <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <2 x float> @fmla_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK-LABEL: fmla_2s:
-;CHECK: fmla.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = load <2 x float>* %C
- %tmp4 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp1, <2 x float> %tmp2, <2 x float> %tmp3)
- ret <2 x float> %tmp4
-}
-
-define <4 x float> @fmla_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK-LABEL: fmla_4s:
-;CHECK: fmla.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = load <4 x float>* %C
- %tmp4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp1, <4 x float> %tmp2, <4 x float> %tmp3)
- ret <4 x float> %tmp4
-}
-
-define <2 x double> @fmla_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
-;CHECK-LABEL: fmla_2d:
-;CHECK: fmla.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = load <2 x double>* %C
- %tmp4 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp1, <2 x double> %tmp2, <2 x double> %tmp3)
- ret <2 x double> %tmp4
-}
-
-declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
-
-define <2 x float> @fmls_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK-LABEL: fmls_2s:
-;CHECK: fmls.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = load <2 x float>* %C
- %tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2
- %tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp1, <2 x float> %tmp4, <2 x float> %tmp3)
- ret <2 x float> %tmp5
-}
-
-define <4 x float> @fmls_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK-LABEL: fmls_4s:
-;CHECK: fmls.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = load <4 x float>* %C
- %tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2
- %tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp1, <4 x float> %tmp4, <4 x float> %tmp3)
- ret <4 x float> %tmp5
-}
-
-define <2 x double> @fmls_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
-;CHECK-LABEL: fmls_2d:
-;CHECK: fmls.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = load <2 x double>* %C
- %tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2
- %tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp1, <2 x double> %tmp4, <2 x double> %tmp3)
- ret <2 x double> %tmp5
-}
-
-define <2 x float> @fmls_commuted_neg_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK-LABEL: fmls_commuted_neg_2s:
-;CHECK: fmls.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = load <2 x float>* %C
- %tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2
- %tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp4, <2 x float> %tmp1, <2 x float> %tmp3)
- ret <2 x float> %tmp5
-}
-
-define <4 x float> @fmls_commuted_neg_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK-LABEL: fmls_commuted_neg_4s:
-;CHECK: fmls.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = load <4 x float>* %C
- %tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2
- %tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp4, <4 x float> %tmp1, <4 x float> %tmp3)
- ret <4 x float> %tmp5
-}
-
-define <2 x double> @fmls_commuted_neg_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
-;CHECK-LABEL: fmls_commuted_neg_2d:
-;CHECK: fmls.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = load <2 x double>* %C
- %tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2
- %tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp4, <2 x double> %tmp1, <2 x double> %tmp3)
- ret <2 x double> %tmp5
-}
-
-define <2 x float> @fmls_indexed_2s(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone ssp {
-;CHECK-LABEL: fmls_indexed_2s:
-;CHECK: fmls.2s
-entry:
- %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %c
- %lane = shufflevector <2 x float> %b, <2 x float> undef, <2 x i32> zeroinitializer
- %fmls1 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %0, <2 x float> %lane, <2 x float> %a)
- ret <2 x float> %fmls1
-}
-
-define <4 x float> @fmls_indexed_4s(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone ssp {
-;CHECK-LABEL: fmls_indexed_4s:
-;CHECK: fmls.4s
-entry:
- %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c
- %lane = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
- %fmls1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %lane, <4 x float> %a)
- ret <4 x float> %fmls1
-}
-
-define <2 x double> @fmls_indexed_2d(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone ssp {
-;CHECK-LABEL: fmls_indexed_2d:
-;CHECK: fmls.2d
-entry:
- %0 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %c
- %lane = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
- %fmls1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %0, <2 x double> %lane, <2 x double> %a)
- ret <2 x double> %fmls1
-}
-
-define <2 x float> @fmla_indexed_scalar_2s(<2 x float> %a, <2 x float> %b, float %c) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: fmla_indexed_scalar_2s:
-; CHECK-NEXT: fmla.2s
-; CHECK-NEXT: ret
- %v1 = insertelement <2 x float> undef, float %c, i32 0
- %v2 = insertelement <2 x float> %v1, float %c, i32 1
- %fmla1 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %v1, <2 x float> %b, <2 x float> %a) nounwind
- ret <2 x float> %fmla1
-}
-
-define <4 x float> @fmla_indexed_scalar_4s(<4 x float> %a, <4 x float> %b, float %c) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: fmla_indexed_scalar_4s:
-; CHECK-NEXT: fmla.4s
-; CHECK-NEXT: ret
- %v1 = insertelement <4 x float> undef, float %c, i32 0
- %v2 = insertelement <4 x float> %v1, float %c, i32 1
- %v3 = insertelement <4 x float> %v2, float %c, i32 2
- %v4 = insertelement <4 x float> %v3, float %c, i32 3
- %fmla1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %v4, <4 x float> %b, <4 x float> %a) nounwind
- ret <4 x float> %fmla1
-}
-
-define <2 x double> @fmla_indexed_scalar_2d(<2 x double> %a, <2 x double> %b, double %c) nounwind readnone ssp {
-; CHECK-LABEL: fmla_indexed_scalar_2d:
-; CHECK-NEXT: fmla.2d
-; CHECK-NEXT: ret
-entry:
- %v1 = insertelement <2 x double> undef, double %c, i32 0
- %v2 = insertelement <2 x double> %v1, double %c, i32 1
- %fmla1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %v2, <2 x double> %b, <2 x double> %a) nounwind
- ret <2 x double> %fmla1
-}
-
-define <4 x i16> @mul_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: mul_4h:
-;CHECK-NOT: dup
-;CHECK: mul.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = mul <4 x i16> %tmp1, %tmp3
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @mul_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: mul_8h:
-;CHECK-NOT: dup
-;CHECK: mul.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
- %tmp4 = mul <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @mul_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: mul_2s:
-;CHECK-NOT: dup
-;CHECK: mul.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = mul <2 x i32> %tmp1, %tmp3
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @mul_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: mul_4s:
-;CHECK-NOT: dup
-;CHECK: mul.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = mul <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @mul_2d(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK-LABEL: mul_2d:
-; CHECK: mul
-; CHECK: mul
- %tmp1 = mul <2 x i64> %A, %B
- ret <2 x i64> %tmp1
-}
-
-define <2 x float> @fmul_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fmul_lane_2s:
-;CHECK-NOT: dup
-;CHECK: fmul.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = shufflevector <2 x float> %tmp2, <2 x float> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = fmul <2 x float> %tmp1, %tmp3
- ret <2 x float> %tmp4
-}
-
-define <4 x float> @fmul_lane_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fmul_lane_4s:
-;CHECK-NOT: dup
-;CHECK: fmul.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = shufflevector <4 x float> %tmp2, <4 x float> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = fmul <4 x float> %tmp1, %tmp3
- ret <4 x float> %tmp4
-}
-
-define <2 x double> @fmul_lane_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fmul_lane_2d:
-;CHECK-NOT: dup
-;CHECK: fmul.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = shufflevector <2 x double> %tmp2, <2 x double> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = fmul <2 x double> %tmp1, %tmp3
- ret <2 x double> %tmp4
-}
-
-define float @fmul_lane_s(float %A, <4 x float> %vec) nounwind {
-;CHECK-LABEL: fmul_lane_s:
-;CHECK-NOT: dup
-;CHECK: fmul.s s0, s0, v1[3]
- %B = extractelement <4 x float> %vec, i32 3
- %res = fmul float %A, %B
- ret float %res
-}
-
-define double @fmul_lane_d(double %A, <2 x double> %vec) nounwind {
-;CHECK-LABEL: fmul_lane_d:
-;CHECK-NOT: dup
-;CHECK: fmul.d d0, d0, v1[1]
- %B = extractelement <2 x double> %vec, i32 1
- %res = fmul double %A, %B
- ret double %res
-}
-
-
-
-define <2 x float> @fmulx_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fmulx_lane_2s:
-;CHECK-NOT: dup
-;CHECK: fmulx.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = shufflevector <2 x float> %tmp2, <2 x float> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = call <2 x float> @llvm.arm64.neon.fmulx.v2f32(<2 x float> %tmp1, <2 x float> %tmp3)
- ret <2 x float> %tmp4
-}
-
-define <4 x float> @fmulx_lane_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fmulx_lane_4s:
-;CHECK-NOT: dup
-;CHECK: fmulx.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = shufflevector <4 x float> %tmp2, <4 x float> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <4 x float> @llvm.arm64.neon.fmulx.v4f32(<4 x float> %tmp1, <4 x float> %tmp3)
- ret <4 x float> %tmp4
-}
-
-define <2 x double> @fmulx_lane_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fmulx_lane_2d:
-;CHECK-NOT: dup
-;CHECK: fmulx.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = shufflevector <2 x double> %tmp2, <2 x double> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = call <2 x double> @llvm.arm64.neon.fmulx.v2f64(<2 x double> %tmp1, <2 x double> %tmp3)
- ret <2 x double> %tmp4
-}
-
-define <4 x i16> @sqdmulh_lane_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqdmulh_lane_4h:
-;CHECK-NOT: dup
-;CHECK: sqdmulh.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <4 x i16> @llvm.arm64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp3)
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @sqdmulh_lane_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqdmulh_lane_8h:
-;CHECK-NOT: dup
-;CHECK: sqdmulh.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <8 x i16> @llvm.arm64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp3)
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @sqdmulh_lane_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqdmulh_lane_2s:
-;CHECK-NOT: dup
-;CHECK: sqdmulh.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = call <2 x i32> @llvm.arm64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3)
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @sqdmulh_lane_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqdmulh_lane_4s:
-;CHECK-NOT: dup
-;CHECK: sqdmulh.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp3)
- ret <4 x i32> %tmp4
-}
-
-define i32 @sqdmulh_lane_1s(i32 %A, <4 x i32> %B) nounwind {
-;CHECK-LABEL: sqdmulh_lane_1s:
-;CHECK-NOT: dup
-;CHECK: sqdmulh.s s0, {{s[0-9]+}}, {{v[0-9]+}}[1]
- %tmp1 = extractelement <4 x i32> %B, i32 1
- %tmp2 = call i32 @llvm.arm64.neon.sqdmulh.i32(i32 %A, i32 %tmp1)
- ret i32 %tmp2
-}
-
-define <4 x i16> @sqrdmulh_lane_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqrdmulh_lane_4h:
-;CHECK-NOT: dup
-;CHECK: sqrdmulh.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <4 x i16> @llvm.arm64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp3)
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @sqrdmulh_lane_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqrdmulh_lane_8h:
-;CHECK-NOT: dup
-;CHECK: sqrdmulh.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <8 x i16> @llvm.arm64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp3)
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @sqrdmulh_lane_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqrdmulh_lane_2s:
-;CHECK-NOT: dup
-;CHECK: sqrdmulh.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = call <2 x i32> @llvm.arm64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3)
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @sqrdmulh_lane_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqrdmulh_lane_4s:
-;CHECK-NOT: dup
-;CHECK: sqrdmulh.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <4 x i32> @llvm.arm64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp3)
- ret <4 x i32> %tmp4
-}
-
-define i32 @sqrdmulh_lane_1s(i32 %A, <4 x i32> %B) nounwind {
-;CHECK-LABEL: sqrdmulh_lane_1s:
-;CHECK-NOT: dup
-;CHECK: sqrdmulh.s s0, {{s[0-9]+}}, {{v[0-9]+}}[1]
- %tmp1 = extractelement <4 x i32> %B, i32 1
- %tmp2 = call i32 @llvm.arm64.neon.sqrdmulh.i32(i32 %A, i32 %tmp1)
- ret i32 %tmp2
-}
-
-define <4 x i32> @sqdmull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqdmull_lane_4s:
-;CHECK-NOT: dup
-;CHECK: sqdmull.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3)
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @sqdmull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqdmull_lane_2d:
-;CHECK-NOT: dup
-;CHECK: sqdmull.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3)
- ret <2 x i64> %tmp4
-}
-
-define <4 x i32> @sqdmull2_lane_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqdmull2_lane_4s:
-;CHECK-NOT: dup
-;CHECK: sqdmull2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @sqdmull2_lane_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqdmull2_lane_2d:
-;CHECK-NOT: dup
-;CHECK: sqdmull2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
- %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i64> %tmp4
-}
-
-define <4 x i32> @umull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: umull_lane_4s:
-;CHECK-NOT: dup
-;CHECK: umull.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3)
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @umull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: umull_lane_2d:
-;CHECK-NOT: dup
-;CHECK: umull.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3)
- ret <2 x i64> %tmp4
-}
-
-define <4 x i32> @smull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: smull_lane_4s:
-;CHECK-NOT: dup
-;CHECK: smull.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3)
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @smull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: smull_lane_2d:
-;CHECK-NOT: dup
-;CHECK: smull.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp4 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3)
- ret <2 x i64> %tmp4
-}
-
-define <4 x i32> @smlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: smlal_lane_4s:
-;CHECK-NOT: dup
-;CHECK: smlal.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
- %tmp6 = add <4 x i32> %tmp3, %tmp5
- ret <4 x i32> %tmp6
-}
-
-define <2 x i64> @smlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: smlal_lane_2d:
-;CHECK-NOT: dup
-;CHECK: smlal.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp5 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
- %tmp6 = add <2 x i64> %tmp3, %tmp5
- ret <2 x i64> %tmp6
-}
-
-define <4 x i32> @sqdmlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sqdmlal_lane_4s:
-;CHECK-NOT: dup
-;CHECK: sqdmlal.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
- %tmp6 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
- ret <4 x i32> %tmp6
-}
-
-define <2 x i64> @sqdmlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sqdmlal_lane_2d:
-;CHECK-NOT: dup
-;CHECK: sqdmlal.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp5 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
- %tmp6 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
- ret <2 x i64> %tmp6
-}
-
-define <4 x i32> @sqdmlal2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sqdmlal2_lane_4s:
-;CHECK-NOT: dup
-;CHECK: sqdmlal2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp6 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
- ret <4 x i32> %tmp6
-}
-
-define <2 x i64> @sqdmlal2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sqdmlal2_lane_2d:
-;CHECK-NOT: dup
-;CHECK: sqdmlal2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
- %tmp5 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp6 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
- ret <2 x i64> %tmp6
-}
-
-define i32 @sqdmlal_lane_1s(i32 %A, i16 %B, <4 x i16> %C) nounwind {
-;CHECK-LABEL: sqdmlal_lane_1s:
-;CHECK: sqdmlal.4s
- %lhs = insertelement <4 x i16> undef, i16 %B, i32 0
- %rhs = shufflevector <4 x i16> %C, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
- %prod.vec = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %lhs, <4 x i16> %rhs)
- %prod = extractelement <4 x i32> %prod.vec, i32 0
- %res = call i32 @llvm.arm64.neon.sqadd.i32(i32 %A, i32 %prod)
- ret i32 %res
-}
-declare i32 @llvm.arm64.neon.sqadd.i32(i32, i32)
-
-define i32 @sqdmlsl_lane_1s(i32 %A, i16 %B, <4 x i16> %C) nounwind {
-;CHECK-LABEL: sqdmlsl_lane_1s:
-;CHECK: sqdmlsl.4s
- %lhs = insertelement <4 x i16> undef, i16 %B, i32 0
- %rhs = shufflevector <4 x i16> %C, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
- %prod.vec = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %lhs, <4 x i16> %rhs)
- %prod = extractelement <4 x i32> %prod.vec, i32 0
- %res = call i32 @llvm.arm64.neon.sqsub.i32(i32 %A, i32 %prod)
- ret i32 %res
-}
-declare i32 @llvm.arm64.neon.sqsub.i32(i32, i32)
-
-define i64 @sqdmlal_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
-;CHECK-LABEL: sqdmlal_lane_1d:
-;CHECK: sqdmlal.s
- %rhs = extractelement <2 x i32> %C, i32 1
- %prod = call i64 @llvm.arm64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)
- %res = call i64 @llvm.arm64.neon.sqadd.i64(i64 %A, i64 %prod)
- ret i64 %res
-}
-declare i64 @llvm.arm64.neon.sqdmulls.scalar(i32, i32)
-declare i64 @llvm.arm64.neon.sqadd.i64(i64, i64)
-
-define i64 @sqdmlsl_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
-;CHECK-LABEL: sqdmlsl_lane_1d:
-;CHECK: sqdmlsl.s
- %rhs = extractelement <2 x i32> %C, i32 1
- %prod = call i64 @llvm.arm64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)
- %res = call i64 @llvm.arm64.neon.sqsub.i64(i64 %A, i64 %prod)
- ret i64 %res
-}
-declare i64 @llvm.arm64.neon.sqsub.i64(i64, i64)
-
-
-define <4 x i32> @umlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: umlal_lane_4s:
-;CHECK-NOT: dup
-;CHECK: umlal.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
- %tmp6 = add <4 x i32> %tmp3, %tmp5
- ret <4 x i32> %tmp6
-}
-
-define <2 x i64> @umlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: umlal_lane_2d:
-;CHECK-NOT: dup
-;CHECK: umlal.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp5 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
- %tmp6 = add <2 x i64> %tmp3, %tmp5
- ret <2 x i64> %tmp6
-}
-
-
-define <4 x i32> @smlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: smlsl_lane_4s:
-;CHECK-NOT: dup
-;CHECK: smlsl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
- %tmp6 = sub <4 x i32> %tmp3, %tmp5
- ret <4 x i32> %tmp6
-}
-
-define <2 x i64> @smlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: smlsl_lane_2d:
-;CHECK-NOT: dup
-;CHECK: smlsl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp5 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
- %tmp6 = sub <2 x i64> %tmp3, %tmp5
- ret <2 x i64> %tmp6
-}
-
-define <4 x i32> @sqdmlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sqdmlsl_lane_4s:
-;CHECK-NOT: dup
-;CHECK: sqdmlsl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
- %tmp6 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
- ret <4 x i32> %tmp6
-}
-
-define <2 x i64> @sqdmlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sqdmlsl_lane_2d:
-;CHECK-NOT: dup
-;CHECK: sqdmlsl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp5 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
- %tmp6 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
- ret <2 x i64> %tmp6
-}
-
-define <4 x i32> @sqdmlsl2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sqdmlsl2_lane_4s:
-;CHECK-NOT: dup
-;CHECK: sqdmlsl2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp6 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
- ret <4 x i32> %tmp6
-}
-
-define <2 x i64> @sqdmlsl2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sqdmlsl2_lane_2d:
-;CHECK-NOT: dup
-;CHECK: sqdmlsl2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
- %tmp5 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp6 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
- ret <2 x i64> %tmp6
-}
-
-define <4 x i32> @umlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: umlsl_lane_4s:
-;CHECK-NOT: dup
-;CHECK: umlsl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
- %tmp6 = sub <4 x i32> %tmp3, %tmp5
- ret <4 x i32> %tmp6
-}
-
-define <2 x i64> @umlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: umlsl_lane_2d:
-;CHECK-NOT: dup
-;CHECK: umlsl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
- %tmp5 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
- %tmp6 = sub <2 x i64> %tmp3, %tmp5
- ret <2 x i64> %tmp6
-}
-
-; Scalar FMULX
-define float @fmulxs(float %a, float %b) nounwind {
-; CHECK-LABEL: fmulxs:
-; CHECKNEXT: fmulx s0, s0, s1
- %fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
-; CHECKNEXT: ret
- ret float %fmulx.i
-}
-
-define double @fmulxd(double %a, double %b) nounwind {
-; CHECK-LABEL: fmulxd:
-; CHECKNEXT: fmulx d0, d0, d1
- %fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
-; CHECKNEXT: ret
- ret double %fmulx.i
-}
-
-define float @fmulxs_lane(float %a, <4 x float> %vec) nounwind {
-; CHECK-LABEL: fmulxs_lane:
-; CHECKNEXT: fmulx.s s0, s0, v1[3]
- %b = extractelement <4 x float> %vec, i32 3
- %fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
-; CHECKNEXT: ret
- ret float %fmulx.i
-}
-
-define double @fmulxd_lane(double %a, <2 x double> %vec) nounwind {
-; CHECK-LABEL: fmulxd_lane:
-; CHECKNEXT: fmulx d0, d0, v1[1]
- %b = extractelement <2 x double> %vec, i32 1
- %fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
-; CHECKNEXT: ret
- ret double %fmulx.i
-}
-
-declare double @llvm.arm64.neon.fmulx.f64(double, double) nounwind readnone
-declare float @llvm.arm64.neon.fmulx.f32(float, float) nounwind readnone
-
-
-define <8 x i16> @smull2_8h_simple(<16 x i8> %a, <16 x i8> %b) nounwind {
-; CHECK-LABEL: smull2_8h_simple:
-; CHECK-NEXT: smull2.8h v0, v0, v1
-; CHECK-NEXT: ret
- %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %2 = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %3 = tail call <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8> %1, <8 x i8> %2) #2
- ret <8 x i16> %3
-}
-
-define <8 x i16> @foo0(<16 x i8> %a, <16 x i8> %b) nounwind {
-; CHECK-LABEL: foo0:
-; CHECK: smull2.8h v0, v0, v1
- %tmp = bitcast <16 x i8> %a to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <8 x i8>
- %tmp2 = bitcast <16 x i8> %b to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <8 x i8>
- %vmull.i.i = tail call <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp3) nounwind
- ret <8 x i16> %vmull.i.i
-}
-
-define <4 x i32> @foo1(<8 x i16> %a, <8 x i16> %b) nounwind {
-; CHECK-LABEL: foo1:
-; CHECK: smull2.4s v0, v0, v1
- %tmp = bitcast <8 x i16> %a to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
- %tmp2 = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>
- %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
- ret <4 x i32> %vmull2.i.i
-}
-
-define <2 x i64> @foo2(<4 x i32> %a, <4 x i32> %b) nounwind {
-; CHECK-LABEL: foo2:
-; CHECK: smull2.2d v0, v0, v1
- %tmp = bitcast <4 x i32> %a to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
- %tmp2 = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>
- %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
- ret <2 x i64> %vmull2.i.i
-}
-
-define <8 x i16> @foo3(<16 x i8> %a, <16 x i8> %b) nounwind {
-; CHECK-LABEL: foo3:
-; CHECK: umull2.8h v0, v0, v1
- %tmp = bitcast <16 x i8> %a to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <8 x i8>
- %tmp2 = bitcast <16 x i8> %b to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <8 x i8>
- %vmull.i.i = tail call <8 x i16> @llvm.arm64.neon.umull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp3) nounwind
- ret <8 x i16> %vmull.i.i
-}
-
-define <4 x i32> @foo4(<8 x i16> %a, <8 x i16> %b) nounwind {
-; CHECK-LABEL: foo4:
-; CHECK: umull2.4s v0, v0, v1
- %tmp = bitcast <8 x i16> %a to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
- %tmp2 = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>
- %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
- ret <4 x i32> %vmull2.i.i
-}
-
-define <2 x i64> @foo5(<4 x i32> %a, <4 x i32> %b) nounwind {
-; CHECK-LABEL: foo5:
-; CHECK: umull2.2d v0, v0, v1
- %tmp = bitcast <4 x i32> %a to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
- %tmp2 = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>
- %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
- ret <2 x i64> %vmull2.i.i
-}
-
-define <4 x i32> @foo6(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
-; CHECK-LABEL: foo6:
-; CHECK-NEXT: smull2.4s v0, v1, v2[1]
-; CHECK-NEXT: ret
-entry:
- %0 = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
- %1 = bitcast <1 x i64> %shuffle.i to <4 x i16>
- %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %vmull2.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %1, <4 x i16> %shuffle) nounwind
- ret <4 x i32> %vmull2.i
-}
-
-define <2 x i64> @foo7(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
-; CHECK-LABEL: foo7:
-; CHECK-NEXT: smull2.2d v0, v1, v2[1]
-; CHECK-NEXT: ret
-entry:
- %0 = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
- %1 = bitcast <1 x i64> %shuffle.i to <2 x i32>
- %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
- %vmull2.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %1, <2 x i32> %shuffle) nounwind
- ret <2 x i64> %vmull2.i
-}
-
-define <4 x i32> @foo8(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
-; CHECK-LABEL: foo8:
-; CHECK-NEXT: umull2.4s v0, v1, v2[1]
-; CHECK-NEXT: ret
-entry:
- %0 = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
- %1 = bitcast <1 x i64> %shuffle.i to <4 x i16>
- %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %vmull2.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %1, <4 x i16> %shuffle) nounwind
- ret <4 x i32> %vmull2.i
-}
-
-define <2 x i64> @foo9(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
-; CHECK-LABEL: foo9:
-; CHECK-NEXT: umull2.2d v0, v1, v2[1]
-; CHECK-NEXT: ret
-entry:
- %0 = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
- %1 = bitcast <1 x i64> %shuffle.i to <2 x i32>
- %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
- %vmull2.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %1, <2 x i32> %shuffle) nounwind
- ret <2 x i64> %vmull2.i
-}
-
-define <8 x i16> @bar0(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) nounwind {
-; CHECK-LABEL: bar0:
-; CHECK: smlal2.8h v0, v1, v2
-; CHECK-NEXT: ret
-
- %tmp = bitcast <16 x i8> %b to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>
- %tmp2 = bitcast <16 x i8> %c to <2 x i64>
- %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <8 x i8>
- %vmull.i.i.i = tail call <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp3) nounwind
- %add.i = add <8 x i16> %vmull.i.i.i, %a
- ret <8 x i16> %add.i
-}
-
-define <4 x i32> @bar1(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) nounwind {
-; CHECK-LABEL: bar1:
-; CHECK: smlal2.4s v0, v1, v2
-; CHECK-NEXT: ret
-
- %tmp = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>
- %tmp2 = bitcast <8 x i16> %c to <2 x i64>
- %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <4 x i16>
- %vmull2.i.i.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
- %add.i = add <4 x i32> %vmull2.i.i.i, %a
- ret <4 x i32> %add.i
-}
-
-define <2 x i64> @bar2(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) nounwind {
-; CHECK-LABEL: bar2:
-; CHECK: smlal2.2d v0, v1, v2
-; CHECK-NEXT: ret
-
- %tmp = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>
- %tmp2 = bitcast <4 x i32> %c to <2 x i64>
- %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <2 x i32>
- %vmull2.i.i.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
- %add.i = add <2 x i64> %vmull2.i.i.i, %a
- ret <2 x i64> %add.i
-}
-
-define <8 x i16> @bar3(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) nounwind {
-; CHECK-LABEL: bar3:
-; CHECK: umlal2.8h v0, v1, v2
-; CHECK-NEXT: ret
-
- %tmp = bitcast <16 x i8> %b to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>
- %tmp2 = bitcast <16 x i8> %c to <2 x i64>
- %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <8 x i8>
- %vmull.i.i.i = tail call <8 x i16> @llvm.arm64.neon.umull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp3) nounwind
- %add.i = add <8 x i16> %vmull.i.i.i, %a
- ret <8 x i16> %add.i
-}
-
-define <4 x i32> @bar4(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) nounwind {
-; CHECK-LABEL: bar4:
-; CHECK: umlal2.4s v0, v1, v2
-; CHECK-NEXT: ret
-
- %tmp = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>
- %tmp2 = bitcast <8 x i16> %c to <2 x i64>
- %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <4 x i16>
- %vmull2.i.i.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
- %add.i = add <4 x i32> %vmull2.i.i.i, %a
- ret <4 x i32> %add.i
-}
-
-define <2 x i64> @bar5(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) nounwind {
-; CHECK-LABEL: bar5:
-; CHECK: umlal2.2d v0, v1, v2
-; CHECK-NEXT: ret
-
- %tmp = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>
- %tmp2 = bitcast <4 x i32> %c to <2 x i64>
- %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <2 x i32>
- %vmull2.i.i.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
- %add.i = add <2 x i64> %vmull2.i.i.i, %a
- ret <2 x i64> %add.i
-}
-
-define <4 x i32> @mlal2_1(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind {
-; CHECK-LABEL: mlal2_1:
-; CHECK: smlal2.4s v0, v1, v2[3]
-; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
- %tmp = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
- %tmp2 = bitcast <8 x i16> %shuffle to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>
- %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
- %add = add <4 x i32> %vmull2.i.i, %a
- ret <4 x i32> %add
-}
-
-define <2 x i64> @mlal2_2(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind {
-; CHECK-LABEL: mlal2_2:
-; CHECK: smlal2.2d v0, v1, v2[1]
-; CHECK-NEXT: ret
- %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
- %tmp2 = bitcast <4 x i32> %shuffle to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>
- %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
- %add = add <2 x i64> %vmull2.i.i, %a
- ret <2 x i64> %add
-}
-
-define <4 x i32> @mlal2_4(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind {
-; CHECK-LABEL: mlal2_4:
-; CHECK: umlal2.4s v0, v1, v2[2]
-; CHECK-NEXT: ret
-
- %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
- %tmp = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
- %tmp2 = bitcast <8 x i16> %shuffle to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>
- %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
- %add = add <4 x i32> %vmull2.i.i, %a
- ret <4 x i32> %add
-}
-
-define <2 x i64> @mlal2_5(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind {
-; CHECK-LABEL: mlal2_5:
-; CHECK: umlal2.2d v0, v1, v2[0]
-; CHECK-NEXT: ret
- %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <4 x i32> zeroinitializer
- %tmp = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
- %tmp2 = bitcast <4 x i32> %shuffle to <2 x i64>
- %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>
- %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
- %add = add <2 x i64> %vmull2.i.i, %a
- ret <2 x i64> %add
-}
-
-; rdar://12328502
-define <2 x double> @vmulq_n_f64(<2 x double> %x, double %y) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: vmulq_n_f64:
-; CHECK-NOT: dup.2d
-; CHECK: fmul.2d v0, v0, v1[0]
- %vecinit.i = insertelement <2 x double> undef, double %y, i32 0
- %vecinit1.i = insertelement <2 x double> %vecinit.i, double %y, i32 1
- %mul.i = fmul <2 x double> %vecinit1.i, %x
- ret <2 x double> %mul.i
-}
-
-define <4 x float> @vmulq_n_f32(<4 x float> %x, float %y) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: vmulq_n_f32:
-; CHECK-NOT: dup.4s
-; CHECK: fmul.4s v0, v0, v1[0]
- %vecinit.i = insertelement <4 x float> undef, float %y, i32 0
- %vecinit1.i = insertelement <4 x float> %vecinit.i, float %y, i32 1
- %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %y, i32 2
- %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %y, i32 3
- %mul.i = fmul <4 x float> %vecinit3.i, %x
- ret <4 x float> %mul.i
-}
-
-define <2 x float> @vmul_n_f32(<2 x float> %x, float %y) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: vmul_n_f32:
-; CHECK-NOT: dup.2s
-; CHECK: fmul.2s v0, v0, v1[0]
- %vecinit.i = insertelement <2 x float> undef, float %y, i32 0
- %vecinit1.i = insertelement <2 x float> %vecinit.i, float %y, i32 1
- %mul.i = fmul <2 x float> %vecinit1.i, %x
- ret <2 x float> %mul.i
-}
-
-define <4 x i16> @vmla_laneq_s16_test(<4 x i16> %a, <4 x i16> %b, <8 x i16> %c) nounwind readnone ssp {
-entry:
-; CHECK: vmla_laneq_s16_test
-; CHECK-NOT: ext
-; CHECK: mla.4h v0, v1, v2[6]
-; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>
- %mul = mul <4 x i16> %shuffle, %b
- %add = add <4 x i16> %mul, %a
- ret <4 x i16> %add
-}
-
-define <2 x i32> @vmla_laneq_s32_test(<2 x i32> %a, <2 x i32> %b, <4 x i32> %c) nounwind readnone ssp {
-entry:
-; CHECK: vmla_laneq_s32_test
-; CHECK-NOT: ext
-; CHECK: mla.2s v0, v1, v2[3]
-; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 3, i32 3>
- %mul = mul <2 x i32> %shuffle, %b
- %add = add <2 x i32> %mul, %a
- ret <2 x i32> %add
-}
-
-define <8 x i16> @not_really_vmlaq_laneq_s16_test(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone ssp {
-entry:
-; CHECK: not_really_vmlaq_laneq_s16_test
-; CHECK-NOT: ext
-; CHECK: mla.8h v0, v1, v2[5]
-; CHECK-NEXT: ret
- %shuffle1 = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %shuffle2 = shufflevector <4 x i16> %shuffle1, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
- %mul = mul <8 x i16> %shuffle2, %b
- %add = add <8 x i16> %mul, %a
- ret <8 x i16> %add
-}
-
-define <4 x i32> @not_really_vmlaq_laneq_s32_test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone ssp {
-entry:
-; CHECK: not_really_vmlaq_laneq_s32_test
-; CHECK-NOT: ext
-; CHECK: mla.4s v0, v1, v2[3]
-; CHECK-NEXT: ret
- %shuffle1 = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %shuffle2 = shufflevector <2 x i32> %shuffle1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %mul = mul <4 x i32> %shuffle2, %b
- %add = add <4 x i32> %mul, %a
- ret <4 x i32> %add
-}
-
-define <4 x i32> @vmull_laneq_s16_test(<4 x i16> %a, <8 x i16> %b) nounwind readnone ssp {
-entry:
-; CHECK: vmull_laneq_s16_test
-; CHECK-NOT: ext
-; CHECK: smull.4s v0, v0, v1[6]
-; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>
- %vmull2.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %a, <4 x i16> %shuffle) #2
- ret <4 x i32> %vmull2.i
-}
-
-define <2 x i64> @vmull_laneq_s32_test(<2 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
-entry:
-; CHECK: vmull_laneq_s32_test
-; CHECK-NOT: ext
-; CHECK: smull.2d v0, v0, v1[2]
-; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 2>
- %vmull2.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %a, <2 x i32> %shuffle) #2
- ret <2 x i64> %vmull2.i
-}
-define <4 x i32> @vmull_laneq_u16_test(<4 x i16> %a, <8 x i16> %b) nounwind readnone ssp {
-entry:
-; CHECK: vmull_laneq_u16_test
-; CHECK-NOT: ext
-; CHECK: umull.4s v0, v0, v1[6]
-; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>
- %vmull2.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %a, <4 x i16> %shuffle) #2
- ret <4 x i32> %vmull2.i
-}
-
-define <2 x i64> @vmull_laneq_u32_test(<2 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
-entry:
-; CHECK: vmull_laneq_u32_test
-; CHECK-NOT: ext
-; CHECK: umull.2d v0, v0, v1[2]
-; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 2>
- %vmull2.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %a, <2 x i32> %shuffle) #2
- ret <2 x i64> %vmull2.i
-}
-
-define <4 x i32> @vmull_high_n_s16_test(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c, i32 %d) nounwind readnone optsize ssp {
-entry:
-; CHECK: vmull_high_n_s16_test
-; CHECK-NOT: ext
-; CHECK: smull2.4s
-; CHECK-NEXT: ret
- %conv = trunc i32 %d to i16
- %0 = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
- %1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
- %vecinit.i = insertelement <4 x i16> undef, i16 %conv, i32 0
- %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %conv, i32 1
- %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %conv, i32 2
- %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %conv, i32 3
- %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %1, <4 x i16> %vecinit3.i) nounwind
- ret <4 x i32> %vmull2.i.i
-}
-
-define <2 x i64> @vmull_high_n_s32_test(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c, i32 %d) nounwind readnone optsize ssp {
-entry:
-; CHECK: vmull_high_n_s32_test
-; CHECK-NOT: ext
-; CHECK: smull2.2d
-; CHECK-NEXT: ret
- %0 = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
- %1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
- %vecinit.i = insertelement <2 x i32> undef, i32 %d, i32 0
- %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %d, i32 1
- %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %1, <2 x i32> %vecinit1.i) nounwind
- ret <2 x i64> %vmull2.i.i
-}
-
-define <4 x i32> @vmull_high_n_u16_test(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c, i32 %d) nounwind readnone optsize ssp {
-entry:
-; CHECK: vmull_high_n_u16_test
-; CHECK-NOT: ext
-; CHECK: umull2.4s
-; CHECK-NEXT: ret
- %conv = trunc i32 %d to i16
- %0 = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
- %1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
- %vecinit.i = insertelement <4 x i16> undef, i16 %conv, i32 0
- %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %conv, i32 1
- %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %conv, i32 2
- %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %conv, i32 3
- %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %1, <4 x i16> %vecinit3.i) nounwind
- ret <4 x i32> %vmull2.i.i
-}
-
-define <2 x i64> @vmull_high_n_u32_test(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c, i32 %d) nounwind readnone optsize ssp {
-entry:
-; CHECK: vmull_high_n_u32_test
-; CHECK-NOT: ext
-; CHECK: umull2.2d
-; CHECK-NEXT: ret
- %0 = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
- %1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
- %vecinit.i = insertelement <2 x i32> undef, i32 %d, i32 0
- %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %d, i32 1
- %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %1, <2 x i32> %vecinit1.i) nounwind
- ret <2 x i64> %vmull2.i.i
-}
-
-define <4 x i32> @vmul_built_dup_test(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-LABEL: vmul_built_dup_test:
-; CHECK-NOT: ins
-; CHECK-NOT: dup
-; CHECK: mul.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[1]
- %vget_lane = extractelement <4 x i32> %b, i32 1
- %vecinit.i = insertelement <4 x i32> undef, i32 %vget_lane, i32 0
- %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %vget_lane, i32 1
- %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %vget_lane, i32 2
- %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %vget_lane, i32 3
- %prod = mul <4 x i32> %a, %vecinit3.i
- ret <4 x i32> %prod
-}
-
-define <4 x i16> @vmul_built_dup_fromsmall_test(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: vmul_built_dup_fromsmall_test:
-; CHECK-NOT: ins
-; CHECK-NOT: dup
-; CHECK: mul.4h {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[3]
- %vget_lane = extractelement <4 x i16> %b, i32 3
- %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
- %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
- %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
- %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
- %prod = mul <4 x i16> %a, %vecinit3.i
- ret <4 x i16> %prod
-}
-
-define <8 x i16> @vmulq_built_dup_fromsmall_test(<8 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: vmulq_built_dup_fromsmall_test:
-; CHECK-NOT: ins
-; CHECK-NOT: dup
-; CHECK: mul.8h {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[0]
- %vget_lane = extractelement <4 x i16> %b, i32 0
- %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 0
- %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 1
- %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 2
- %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 3
- %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 4
- %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 5
- %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 6
- %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 7
- %prod = mul <8 x i16> %a, %vecinit7.i
- ret <8 x i16> %prod
-}
-
-define <2 x i64> @mull_from_two_extracts(<4 x i32> %lhs, <4 x i32> %rhs) {
-; CHECK-LABEL: mull_from_two_extracts:
-; CHECK-NOT: ext
-; CHECK: sqdmull2.2d
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
- %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
- ret <2 x i64> %res
-}
-
-define <2 x i64> @mlal_from_two_extracts(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {
-; CHECK-LABEL: mlal_from_two_extracts:
-; CHECK-NOT: ext
-; CHECK: sqdmlal2.2d
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
- %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
- %sum = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %accum, <2 x i64> %res)
- ret <2 x i64> %sum
-}
-
-define <2 x i64> @mull_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
-; CHECK-LABEL: mull_from_extract_dup:
-; CHECK-NOT: ext
-; CHECK: sqdmull2.2d
- %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
- %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
- %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
- ret <2 x i64> %res
-}
-
-define <8 x i16> @pmull_from_extract_dup(<16 x i8> %lhs, i8 %rhs) {
-; CHECK-LABEL: pmull_from_extract_dup:
-; CHECK-NOT: ext
-; CHECK: pmull2.8h
- %rhsvec.0 = insertelement <8 x i8> undef, i8 %rhs, i32 0
- %rhsvec = shufflevector <8 x i8> %rhsvec.0, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
-
- %lhs.high = shufflevector <16 x i8> %lhs, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-
- %res = tail call <8 x i16> @llvm.arm64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhsvec) nounwind
- ret <8 x i16> %res
-}
-
-define <8 x i16> @pmull_from_extract_duplane(<16 x i8> %lhs, <8 x i8> %rhs) {
-; CHECK-LABEL: pmull_from_extract_duplane:
-; CHECK-NOT: ext
-; CHECK: pmull2.8h
-
- %lhs.high = shufflevector <16 x i8> %lhs, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %rhs.high = shufflevector <8 x i8> %rhs, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
-
- %res = tail call <8 x i16> @llvm.arm64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhs.high) nounwind
- ret <8 x i16> %res
-}
-
-define <2 x i64> @sqdmull_from_extract_duplane(<4 x i32> %lhs, <4 x i32> %rhs) {
-; CHECK-LABEL: sqdmull_from_extract_duplane:
-; CHECK-NOT: ext
-; CHECK: sqdmull2.2d
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>
-
- %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
- ret <2 x i64> %res
-}
-
-define <2 x i64> @sqdmlal_from_extract_duplane(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {
-; CHECK-LABEL: sqdmlal_from_extract_duplane:
-; CHECK-NOT: ext
-; CHECK: sqdmlal2.2d
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>
-
- %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
- %sum = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %accum, <2 x i64> %res)
- ret <2 x i64> %sum
-}
-
-define <2 x i64> @umlal_from_extract_duplane(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {
-; CHECK-LABEL: umlal_from_extract_duplane:
-; CHECK-NOT: ext
-; CHECK: umlal2.2d
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>
-
- %res = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
- %sum = add <2 x i64> %accum, %res
- ret <2 x i64> %sum
-}
-
-define float @scalar_fmla_from_extract_v4f32(float %accum, float %lhs, <4 x float> %rvec) {
-; CHECK-LABEL: scalar_fmla_from_extract_v4f32:
-; CHECK: fmla.s s0, s1, v2[3]
- %rhs = extractelement <4 x float> %rvec, i32 3
- %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)
- ret float %res
-}
-
-define float @scalar_fmla_from_extract_v2f32(float %accum, float %lhs, <2 x float> %rvec) {
-; CHECK-LABEL: scalar_fmla_from_extract_v2f32:
-; CHECK: fmla.s s0, s1, v2[1]
- %rhs = extractelement <2 x float> %rvec, i32 1
- %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)
- ret float %res
-}
-
-define float @scalar_fmls_from_extract_v4f32(float %accum, float %lhs, <4 x float> %rvec) {
-; CHECK-LABEL: scalar_fmls_from_extract_v4f32:
-; CHECK: fmls.s s0, s1, v2[3]
- %rhs.scal = extractelement <4 x float> %rvec, i32 3
- %rhs = fsub float -0.0, %rhs.scal
- %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)
- ret float %res
-}
-
-define float @scalar_fmls_from_extract_v2f32(float %accum, float %lhs, <2 x float> %rvec) {
-; CHECK-LABEL: scalar_fmls_from_extract_v2f32:
-; CHECK: fmls.s s0, s1, v2[1]
- %rhs.scal = extractelement <2 x float> %rvec, i32 1
- %rhs = fsub float -0.0, %rhs.scal
- %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)
- ret float %res
-}
-
-declare float @llvm.fma.f32(float, float, float)
-
-define double @scalar_fmla_from_extract_v2f64(double %accum, double %lhs, <2 x double> %rvec) {
-; CHECK-LABEL: scalar_fmla_from_extract_v2f64:
-; CHECK: fmla.d d0, d1, v2[1]
- %rhs = extractelement <2 x double> %rvec, i32 1
- %res = call double @llvm.fma.f64(double %lhs, double %rhs, double %accum)
- ret double %res
-}
-
-define double @scalar_fmls_from_extract_v2f64(double %accum, double %lhs, <2 x double> %rvec) {
-; CHECK-LABEL: scalar_fmls_from_extract_v2f64:
-; CHECK: fmls.d d0, d1, v2[1]
- %rhs.scal = extractelement <2 x double> %rvec, i32 1
- %rhs = fsub double -0.0, %rhs.scal
- %res = call double @llvm.fma.f64(double %lhs, double %rhs, double %accum)
- ret double %res
-}
-
-declare double @llvm.fma.f64(double, double, double)
-
-define <2 x float> @fmls_with_fneg_before_extract_v2f32(<2 x float> %accum, <2 x float> %lhs, <4 x float> %rhs) {
-; CHECK-LABEL: fmls_with_fneg_before_extract_v2f32:
-; CHECK: fmls.2s v0, v1, v2[3]
- %rhs_neg = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %rhs
- %splat = shufflevector <4 x float> %rhs_neg, <4 x float> undef, <2 x i32> <i32 3, i32 3>
- %res = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %splat, <2 x float> %accum)
- ret <2 x float> %res
-}
-
-define <2 x float> @fmls_with_fneg_before_extract_v2f32_1(<2 x float> %accum, <2 x float> %lhs, <2 x float> %rhs) {
-; CHECK-LABEL: fmls_with_fneg_before_extract_v2f32_1:
-; CHECK: fmls.2s v0, v1, v2[1]
- %rhs_neg = fsub <2 x float> <float -0.0, float -0.0>, %rhs
- %splat = shufflevector <2 x float> %rhs_neg, <2 x float> undef, <2 x i32> <i32 1, i32 1>
- %res = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %splat, <2 x float> %accum)
- ret <2 x float> %res
-}
-
-define <4 x float> @fmls_with_fneg_before_extract_v4f32(<4 x float> %accum, <4 x float> %lhs, <4 x float> %rhs) {
-; CHECK-LABEL: fmls_with_fneg_before_extract_v4f32:
-; CHECK: fmls.4s v0, v1, v2[3]
- %rhs_neg = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %rhs
- %splat = shufflevector <4 x float> %rhs_neg, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
- %res = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %splat, <4 x float> %accum)
- ret <4 x float> %res
-}
-
-define <4 x float> @fmls_with_fneg_before_extract_v4f32_1(<4 x float> %accum, <4 x float> %lhs, <2 x float> %rhs) {
-; CHECK-LABEL: fmls_with_fneg_before_extract_v4f32_1:
-; CHECK: fmls.4s v0, v1, v2[1]
- %rhs_neg = fsub <2 x float> <float -0.0, float -0.0>, %rhs
- %splat = shufflevector <2 x float> %rhs_neg, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %res = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %splat, <4 x float> %accum)
- ret <4 x float> %res
-}
-
-define <2 x double> @fmls_with_fneg_before_extract_v2f64(<2 x double> %accum, <2 x double> %lhs, <2 x double> %rhs) {
-; CHECK-LABEL: fmls_with_fneg_before_extract_v2f64:
-; CHECK: fmls.2d v0, v1, v2[1]
- %rhs_neg = fsub <2 x double> <double -0.0, double -0.0>, %rhs
- %splat = shufflevector <2 x double> %rhs_neg, <2 x double> undef, <2 x i32> <i32 1, i32 1>
- %res = call <2 x double> @llvm.fma.v2f64(<2 x double> %lhs, <2 x double> %splat, <2 x double> %accum)
- ret <2 x double> %res
-}
-
-define <1 x double> @test_fmul_v1f64(<1 x double> %L, <1 x double> %R) nounwind {
-; CHECK-LABEL: test_fmul_v1f64:
-; CHECK: fmul
- %prod = fmul <1 x double> %L, %R
- ret <1 x double> %prod
-}
-
-define <1 x double> @test_fdiv_v1f64(<1 x double> %L, <1 x double> %R) nounwind {
-; CHECK-LABEL: test_fdiv_v1f64:
-; CHECK-LABEL: fdiv
- %prod = fdiv <1 x double> %L, %R
- ret <1 x double> %prod
-}
-
-define i64 @sqdmlal_d(i32 %A, i32 %B, i64 %C) nounwind {
-;CHECK-LABEL: sqdmlal_d:
-;CHECK: sqdmlal
- %tmp4 = call i64 @llvm.arm64.neon.sqdmulls.scalar(i32 %A, i32 %B)
- %tmp5 = call i64 @llvm.arm64.neon.sqadd.i64(i64 %C, i64 %tmp4)
- ret i64 %tmp5
-}
-
-define i64 @sqdmlsl_d(i32 %A, i32 %B, i64 %C) nounwind {
-;CHECK-LABEL: sqdmlsl_d:
-;CHECK: sqdmlsl
- %tmp4 = call i64 @llvm.arm64.neon.sqdmulls.scalar(i32 %A, i32 %B)
- %tmp5 = call i64 @llvm.arm64.neon.sqsub.i64(i64 %C, i64 %tmp4)
- ret i64 %tmp5
-}
-
-define <16 x i8> @test_pmull_64(i64 %l, i64 %r) nounwind {
-; CHECK-LABEL: test_pmull_64:
-; CHECK: pmull.1q
- %val = call <16 x i8> @llvm.arm64.neon.pmull64(i64 %l, i64 %r)
- ret <16 x i8> %val
-}
-
-define <16 x i8> @test_pmull_high_64(<2 x i64> %l, <2 x i64> %r) nounwind {
-; CHECK-LABEL: test_pmull_high_64:
-; CHECK: pmull2.1q
- %l_hi = extractelement <2 x i64> %l, i32 1
- %r_hi = extractelement <2 x i64> %r, i32 1
- %val = call <16 x i8> @llvm.arm64.neon.pmull64(i64 %l_hi, i64 %r_hi)
- ret <16 x i8> %val
-}
-
-declare <16 x i8> @llvm.arm64.neon.pmull64(i64, i64)
-
-define <1 x i64> @test_mul_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) nounwind {
-; CHECK-LABEL: test_mul_v1i64:
-; CHECK: mul
- %prod = mul <1 x i64> %lhs, %rhs
- ret <1 x i64> %prod
-}
Removed: llvm/trunk/test/CodeGen/ARM64/volatile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/volatile.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/volatile.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/volatile.ll (removed)
@@ -1,27 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-define i64 @normal_load(i64* nocapture %bar) nounwind readonly {
-; CHECK: normal_load
-; CHECK: ldp
-; CHECK-NEXT: add
-; CHECK-NEXT: ret
- %add.ptr = getelementptr inbounds i64* %bar, i64 1
- %tmp = load i64* %add.ptr, align 8
- %add.ptr1 = getelementptr inbounds i64* %bar, i64 2
- %tmp1 = load i64* %add.ptr1, align 8
- %add = add nsw i64 %tmp1, %tmp
- ret i64 %add
-}
-
-define i64 @volatile_load(i64* nocapture %bar) nounwind {
-; CHECK: volatile_load
-; CHECK: ldr
-; CHECK-NEXT: ldr
-; CHECK-NEXT: add
-; CHECK-NEXT: ret
- %add.ptr = getelementptr inbounds i64* %bar, i64 1
- %tmp = load volatile i64* %add.ptr, align 8
- %add.ptr1 = getelementptr inbounds i64* %bar, i64 2
- %tmp1 = load volatile i64* %add.ptr1, align 8
- %add = add nsw i64 %tmp1, %tmp
- ret i64 %add
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vpopcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vpopcnt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vpopcnt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vpopcnt.ll (removed)
@@ -1,68 +0,0 @@
-; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
-target triple = "arm64-apple-ios"
-
-; The non-byte ones used to fail with "Cannot select"
-
-; CHECK-LABEL: ctpopv8i8
-; CHECK: cnt.8b
-define <8 x i8> @ctpopv8i8(<8 x i8> %x) nounwind readnone {
- %cnt = tail call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %x)
- ret <8 x i8> %cnt
-}
-
-declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
-
-; CHECK-LABEL: ctpopv4i16
-; CHECK: cnt.8b
-define <4 x i16> @ctpopv4i16(<4 x i16> %x) nounwind readnone {
- %cnt = tail call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %x)
- ret <4 x i16> %cnt
-}
-
-declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone
-
-; CHECK-LABEL: ctpopv2i32
-; CHECK: cnt.8b
-define <2 x i32> @ctpopv2i32(<2 x i32> %x) nounwind readnone {
- %cnt = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %x)
- ret <2 x i32> %cnt
-}
-
-declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
-
-
-; CHECK-LABEL: ctpopv16i8
-; CHECK: cnt.16b
-define <16 x i8> @ctpopv16i8(<16 x i8> %x) nounwind readnone {
- %cnt = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x)
- ret <16 x i8> %cnt
-}
-
-declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
-
-; CHECK-LABEL: ctpopv8i16
-; CHECK: cnt.8b
-define <8 x i16> @ctpopv8i16(<8 x i16> %x) nounwind readnone {
- %cnt = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %x)
- ret <8 x i16> %cnt
-}
-
-declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone
-
-; CHECK-LABEL: ctpopv4i32
-; CHECK: cnt.8b
-define <4 x i32> @ctpopv4i32(<4 x i32> %x) nounwind readnone {
- %cnt = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %x)
- ret <4 x i32> %cnt
-}
-
-declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
-
-; CHECK-LABEL: ctpopv2i64
-; CHECK: cnt.8b
-define <2 x i64> @ctpopv2i64(<2 x i64> %x) nounwind readnone {
- %cnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x)
- ret <2 x i64> %cnt
-}
-
-declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vqadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vqadd.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vqadd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vqadd.ll (removed)
@@ -1,332 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sqadd8b:
-;CHECK: sqadd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqadd4h:
-;CHECK: sqadd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqadd2s:
-;CHECK: sqadd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <8 x i8> @uqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uqadd8b:
-;CHECK: uqadd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @uqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uqadd4h:
-;CHECK: uqadd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @uqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uqadd2s:
-;CHECK: uqadd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sqadd16b:
-;CHECK: sqadd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @sqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqadd8h:
-;CHECK: sqadd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @sqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqadd4s:
-;CHECK: sqadd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: sqadd2d:
-;CHECK: sqadd.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-define <16 x i8> @uqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uqadd16b:
-;CHECK: uqadd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @uqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uqadd8h:
-;CHECK: uqadd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @uqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uqadd4s:
-;CHECK: uqadd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @uqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: uqadd2d:
-;CHECK: uqadd.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.uqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.sqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.sqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <8 x i8> @llvm.arm64.neon.uqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.uqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.sqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.uqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.uqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.uqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.uqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i8> @usqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: usqadd8b:
-;CHECK: usqadd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.usqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @usqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: usqadd4h:
-;CHECK: usqadd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.usqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @usqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: usqadd2s:
-;CHECK: usqadd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.usqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @usqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: usqadd16b:
-;CHECK: usqadd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.usqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @usqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: usqadd8h:
-;CHECK: usqadd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.usqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @usqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: usqadd4s:
-;CHECK: usqadd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.usqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @usqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: usqadd2d:
-;CHECK: usqadd.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.usqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-define i64 @usqadd_d(i64 %l, i64 %r) nounwind {
-; CHECK-LABEL: usqadd_d:
-; CHECK: usqadd {{d[0-9]+}}, {{d[0-9]+}}
- %sum = call i64 @llvm.arm64.neon.usqadd.i64(i64 %l, i64 %r)
- ret i64 %sum
-}
-
-define i32 @usqadd_s(i32 %l, i32 %r) nounwind {
-; CHECK-LABEL: usqadd_s:
-; CHECK: usqadd {{s[0-9]+}}, {{s[0-9]+}}
- %sum = call i32 @llvm.arm64.neon.usqadd.i32(i32 %l, i32 %r)
- ret i32 %sum
-}
-
-declare <8 x i8> @llvm.arm64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.usqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.usqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-declare i64 @llvm.arm64.neon.usqadd.i64(i64, i64) nounwind readnone
-declare i32 @llvm.arm64.neon.usqadd.i32(i32, i32) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.usqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.usqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.usqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.usqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i8> @suqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: suqadd8b:
-;CHECK: suqadd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.suqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @suqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: suqadd4h:
-;CHECK: suqadd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.suqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @suqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: suqadd2s:
-;CHECK: suqadd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.suqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @suqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: suqadd16b:
-;CHECK: suqadd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.suqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @suqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: suqadd8h:
-;CHECK: suqadd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.suqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @suqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: suqadd4s:
-;CHECK: suqadd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.suqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @suqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: suqadd2d:
-;CHECK: suqadd.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.suqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-define <1 x i64> @suqadd_1d(<1 x i64> %l, <1 x i64> %r) nounwind {
-; CHECK-LABEL: suqadd_1d:
-; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
- %sum = call <1 x i64> @llvm.arm64.neon.suqadd.v1i64(<1 x i64> %l, <1 x i64> %r)
- ret <1 x i64> %sum
-}
-
-define i64 @suqadd_d(i64 %l, i64 %r) nounwind {
-; CHECK-LABEL: suqadd_d:
-; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
- %sum = call i64 @llvm.arm64.neon.suqadd.i64(i64 %l, i64 %r)
- ret i64 %sum
-}
-
-define i32 @suqadd_s(i32 %l, i32 %r) nounwind {
-; CHECK-LABEL: suqadd_s:
-; CHECK: suqadd {{s[0-9]+}}, {{s[0-9]+}}
- %sum = call i32 @llvm.arm64.neon.suqadd.i32(i32 %l, i32 %r)
- ret i32 %sum
-}
-
-declare <8 x i8> @llvm.arm64.neon.suqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.suqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.suqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.suqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-declare i64 @llvm.arm64.neon.suqadd.i64(i64, i64) nounwind readnone
-declare i32 @llvm.arm64.neon.suqadd.i32(i32, i32) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.suqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.suqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.suqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.suqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vqsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vqsub.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vqsub.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vqsub.ll (removed)
@@ -1,147 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sqsub8b:
-;CHECK: sqsub.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqsub4h:
-;CHECK: sqsub.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqsub2s:
-;CHECK: sqsub.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <8 x i8> @uqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uqsub8b:
-;CHECK: uqsub.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @uqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uqsub4h:
-;CHECK: uqsub.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @uqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uqsub2s:
-;CHECK: uqsub.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sqsub16b:
-;CHECK: sqsub.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @sqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqsub8h:
-;CHECK: sqsub.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @sqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqsub4s:
-;CHECK: sqsub.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: sqsub2d:
-;CHECK: sqsub.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-define <16 x i8> @uqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uqsub16b:
-;CHECK: uqsub.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @uqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uqsub8h:
-;CHECK: uqsub.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @uqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uqsub4s:
-;CHECK: uqsub.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @uqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: uqsub2d:
-;CHECK: uqsub.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.uqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.sqsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.sqsub.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <8 x i8> @llvm.arm64.neon.uqsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uqsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.uqsub.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.sqsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sqsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.uqsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.uqsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.uqsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.uqsub.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vselect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vselect.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vselect.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vselect.ll (removed)
@@ -1,25 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-;CHECK: @func63
-;CHECK: cmeq.4h v0, v0, v1
-
-;FIXME: currently, it will generate 3 instructions:
-; ushll.4s v0, v0, #0
-; shl.4s v0, v0, #31
-; sshr.4s v0, v0, #31
-;But these instrucitons can be optimized into 1 instruction:
-; sshll.4s v0, v0, #0
-
-;CHECK: bsl.16b v0, v2, v3
-;CHECK: str q0, [x0]
-;CHECK: ret
-
-%T0_63 = type <4 x i16>
-%T1_63 = type <4 x i32>
-%T2_63 = type <4 x i1>
-define void @func63(%T1_63* %out, %T0_63 %v0, %T0_63 %v1, %T1_63 %v2, %T1_63 %v3) {
- %cond = icmp eq %T0_63 %v0, %v1
- %r = select %T2_63 %cond, %T1_63 %v2, %T1_63 %v3
- store %T1_63 %r, %T1_63* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vsetcc_fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vsetcc_fp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vsetcc_fp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vsetcc_fp.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -asm-verbose=false | FileCheck %s
-define <2 x i32> @fcmp_one(<2 x float> %x, <2 x float> %y) nounwind optsize readnone {
-; CHECK-LABEL: fcmp_one:
-; CHECK-NEXT: fcmgt.2s [[REG:v[0-9]+]], v0, v1
-; CHECK-NEXT: fcmgt.2s [[REG2:v[0-9]+]], v1, v0
-; CHECK-NEXT: orr.8b v0, [[REG2]], [[REG]]
-; CHECK-NEXT: ret
- %tmp = fcmp one <2 x float> %x, %y
- %or = sext <2 x i1> %tmp to <2 x i32>
- ret <2 x i32> %or
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vshift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vshift.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vshift.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vshift.ll (removed)
@@ -1,1917 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -enable-misched=false | FileCheck %s
-
-define <8 x i8> @sqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sqshl8b:
-;CHECK: sqshl.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqshl4h:
-;CHECK: sqshl.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqshl2s:
-;CHECK: sqshl.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <8 x i8> @uqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uqshl8b:
-;CHECK: uqshl.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @uqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uqshl4h:
-;CHECK: uqshl.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @uqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uqshl2s:
-;CHECK: uqshl.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sqshl16b:
-;CHECK: sqshl.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @sqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqshl8h:
-;CHECK: sqshl.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @sqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqshl4s:
-;CHECK: sqshl.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: sqshl2d:
-;CHECK: sqshl.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-define <16 x i8> @uqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uqshl16b:
-;CHECK: uqshl.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @uqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uqshl8h:
-;CHECK: uqshl.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @uqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uqshl4s:
-;CHECK: uqshl.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @uqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: uqshl2d:
-;CHECK: uqshl.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.sqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.sqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <8 x i8> @llvm.arm64.neon.uqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.uqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.sqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.sqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.uqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.uqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.uqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.uqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i8> @srshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: srshl8b:
-;CHECK: srshl.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @srshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: srshl4h:
-;CHECK: srshl.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @srshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: srshl2s:
-;CHECK: srshl.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <8 x i8> @urshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: urshl8b:
-;CHECK: urshl.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @urshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: urshl4h:
-;CHECK: urshl.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @urshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: urshl2s:
-;CHECK: urshl.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @srshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: srshl16b:
-;CHECK: srshl.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @srshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: srshl8h:
-;CHECK: srshl.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @srshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: srshl4s:
-;CHECK: srshl.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @srshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: srshl2d:
-;CHECK: srshl.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-define <16 x i8> @urshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: urshl16b:
-;CHECK: urshl.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @urshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: urshl8h:
-;CHECK: urshl.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @urshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: urshl4s:
-;CHECK: urshl.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @urshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: urshl2d:
-;CHECK: urshl.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.srshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.urshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i8> @sqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sqrshl8b:
-;CHECK: sqrshl.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sqrshl4h:
-;CHECK: sqrshl.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sqrshl2s:
-;CHECK: sqrshl.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <8 x i8> @uqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uqrshl8b:
-;CHECK: uqrshl.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @uqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uqrshl4h:
-;CHECK: uqrshl.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @uqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uqrshl2s:
-;CHECK: uqrshl.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sqrshl16b:
-;CHECK: sqrshl.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @sqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sqrshl8h:
-;CHECK: sqrshl.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @sqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sqrshl4s:
-;CHECK: sqrshl.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: sqrshl2d:
-;CHECK: sqrshl.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.sqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-define <16 x i8> @uqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uqrshl16b:
-;CHECK: uqrshl.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @uqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uqrshl8h:
-;CHECK: uqrshl.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @uqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uqrshl4s:
-;CHECK: uqrshl.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @uqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: uqrshl2d:
-;CHECK: uqrshl.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.uqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.sqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.sqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <8 x i8> @llvm.arm64.neon.uqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.uqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.sqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.sqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.uqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.uqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.uqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.uqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i8> @urshr8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: urshr8b:
-;CHECK: urshr.8b
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @urshr4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: urshr4h:
-;CHECK: urshr.4h
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @urshr2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: urshr2s:
-;CHECK: urshr.2s
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @urshr16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: urshr16b:
-;CHECK: urshr.16b
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @urshr8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: urshr8h:
-;CHECK: urshr.8h
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @urshr4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: urshr4s:
-;CHECK: urshr.4s
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @urshr2d(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: urshr2d:
-;CHECK: urshr.2d
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
- ret <2 x i64> %tmp3
-}
-
-define <8 x i8> @srshr8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: srshr8b:
-;CHECK: srshr.8b
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @srshr4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: srshr4h:
-;CHECK: srshr.4h
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @srshr2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: srshr2s:
-;CHECK: srshr.2s
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @srshr16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: srshr16b:
-;CHECK: srshr.16b
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @srshr8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: srshr8h:
-;CHECK: srshr.8h
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @srshr4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: srshr4s:
-;CHECK: srshr.4s
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @srshr2d(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: srshr2d:
-;CHECK: srshr.2d
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
- ret <2 x i64> %tmp3
-}
-
-define <8 x i8> @sqshlu8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: sqshlu8b:
-;CHECK: sqshlu.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshlu.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqshlu4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: sqshlu4h:
-;CHECK: sqshlu.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshlu.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqshlu2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: sqshlu2s:
-;CHECK: sqshlu.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshlu.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqshlu16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: sqshlu16b:
-;CHECK: sqshlu.16b v0, {{v[0-9]+}}, #1
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sqshlu.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @sqshlu8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqshlu8h:
-;CHECK: sqshlu.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqshlu.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @sqshlu4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqshlu4s:
-;CHECK: sqshlu.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqshlu.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sqshlu2d(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqshlu2d:
-;CHECK: sqshlu.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.sqshlu.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.sqshlu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqshlu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqshlu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.sqshlu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.sqshlu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sqshlu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sqshlu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.sqshlu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i8> @rshrn8b(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: rshrn8b:
-;CHECK: rshrn.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @rshrn4h(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: rshrn4h:
-;CHECK: rshrn.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @rshrn2s(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: rshrn2s:
-;CHECK: rshrn.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @rshrn16b(<8 x i8> *%ret, <8 x i16>* %A) nounwind {
-;CHECK-LABEL: rshrn16b:
-;CHECK: rshrn2.16b v0, {{v[0-9]+}}, #1
- %out = load <8 x i8>* %ret
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)
- %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @rshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
-;CHECK-LABEL: rshrn8h:
-;CHECK: rshrn2.8h v0, {{v[0-9]+}}, #1
- %out = load <4 x i16>* %ret
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)
- %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @rshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
-;CHECK-LABEL: rshrn4s:
-;CHECK: rshrn2.4s v0, {{v[0-9]+}}, #1
- %out = load <2 x i32>* %ret
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)
- %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %tmp4
-}
-
-declare <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.rshrn.v4i16(<4 x i32>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.rshrn.v2i32(<2 x i64>, i32) nounwind readnone
-
-define <8 x i8> @shrn8b(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: shrn8b:
-;CHECK: shrn.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @shrn4h(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: shrn4h:
-;CHECK: shrn.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
- %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @shrn2s(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: shrn2s:
-;CHECK: shrn.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
- %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @shrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
-;CHECK-LABEL: shrn16b:
-;CHECK: shrn2.16b v0, {{v[0-9]+}}, #1
- %out = load <8 x i8>* %ret
- %tmp1 = load <8 x i16>* %A
- %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
- %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @shrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
-;CHECK-LABEL: shrn8h:
-;CHECK: shrn2.8h v0, {{v[0-9]+}}, #1
- %out = load <4 x i16>* %ret
- %tmp1 = load <4 x i32>* %A
- %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
- %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
- %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @shrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
-;CHECK-LABEL: shrn4s:
-;CHECK: shrn2.4s v0, {{v[0-9]+}}, #1
- %out = load <2 x i32>* %ret
- %tmp1 = load <2 x i64>* %A
- %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
- %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
- %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %tmp4
-}
-
-declare <8 x i8> @llvm.arm64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone
-
-define i32 @sqshrn1s(i64 %A) nounwind {
-; CHECK-LABEL: sqshrn1s:
-; CHECK: sqshrn {{s[0-9]+}}, d0, #1
- %tmp = call i32 @llvm.arm64.neon.sqshrn.i32(i64 %A, i32 1)
- ret i32 %tmp
-}
-
-define <8 x i8> @sqshrn8b(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqshrn8b:
-;CHECK: sqshrn.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqshrn4h(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqshrn4h:
-;CHECK: sqshrn.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqshrn2s(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqshrn2s:
-;CHECK: sqshrn.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
- ret <2 x i32> %tmp3
-}
-
-
-define <16 x i8> @sqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqshrn16b:
-;CHECK: sqshrn2.16b v0, {{v[0-9]+}}, #1
- %out = load <8 x i8>* %ret
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
- %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @sqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqshrn8h:
-;CHECK: sqshrn2.8h v0, {{v[0-9]+}}, #1
- %out = load <4 x i16>* %ret
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
- %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @sqshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqshrn4s:
-;CHECK: sqshrn2.4s v0, {{v[0-9]+}}, #1
- %out = load <2 x i32>* %ret
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
- %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %tmp4
-}
-
-declare i32 @llvm.arm64.neon.sqshrn.i32(i64, i32) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.sqshrn.v8i8(<8 x i16>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqshrn.v4i16(<4 x i32>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqshrn.v2i32(<2 x i64>, i32) nounwind readnone
-
-define i32 @sqshrun1s(i64 %A) nounwind {
-; CHECK-LABEL: sqshrun1s:
-; CHECK: sqshrun {{s[0-9]+}}, d0, #1
- %tmp = call i32 @llvm.arm64.neon.sqshrun.i32(i64 %A, i32 1)
- ret i32 %tmp
-}
-
-define <8 x i8> @sqshrun8b(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqshrun8b:
-;CHECK: sqshrun.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqshrun4h(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqshrun4h:
-;CHECK: sqshrun.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqshrun2s(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqshrun2s:
-;CHECK: sqshrun.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqshrun16b:
-;CHECK: sqshrun2.16b v0, {{v[0-9]+}}, #1
- %out = load <8 x i8>* %ret
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)
- %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @sqshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqshrun8h:
-;CHECK: sqshrun2.8h v0, {{v[0-9]+}}, #1
- %out = load <4 x i16>* %ret
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)
- %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @sqshrun4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqshrun4s:
-;CHECK: sqshrun2.4s v0, {{v[0-9]+}}, #1
- %out = load <2 x i32>* %ret
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)
- %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %tmp4
-}
-
-declare i32 @llvm.arm64.neon.sqshrun.i32(i64, i32) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.sqshrun.v8i8(<8 x i16>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqshrun.v4i16(<4 x i32>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqshrun.v2i32(<2 x i64>, i32) nounwind readnone
-
-define i32 @sqrshrn1s(i64 %A) nounwind {
-; CHECK-LABEL: sqrshrn1s:
-; CHECK: sqrshrn {{s[0-9]+}}, d0, #1
- %tmp = call i32 @llvm.arm64.neon.sqrshrn.i32(i64 %A, i32 1)
- ret i32 %tmp
-}
-
-define <8 x i8> @sqrshrn8b(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqrshrn8b:
-;CHECK: sqrshrn.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqrshrn4h(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqrshrn4h:
-;CHECK: sqrshrn.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqrshrn2s(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqrshrn2s:
-;CHECK: sqrshrn.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqrshrn16b:
-;CHECK: sqrshrn2.16b v0, {{v[0-9]+}}, #1
- %out = load <8 x i8>* %ret
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
- %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @sqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqrshrn8h:
-;CHECK: sqrshrn2.8h v0, {{v[0-9]+}}, #1
- %out = load <4 x i16>* %ret
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
- %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @sqrshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqrshrn4s:
-;CHECK: sqrshrn2.4s v0, {{v[0-9]+}}, #1
- %out = load <2 x i32>* %ret
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
- %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %tmp4
-}
-
-declare i32 @llvm.arm64.neon.sqrshrn.i32(i64, i32) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.sqrshrn.v8i8(<8 x i16>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqrshrn.v4i16(<4 x i32>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqrshrn.v2i32(<2 x i64>, i32) nounwind readnone
-
-define i32 @sqrshrun1s(i64 %A) nounwind {
-; CHECK-LABEL: sqrshrun1s:
-; CHECK: sqrshrun {{s[0-9]+}}, d0, #1
- %tmp = call i32 @llvm.arm64.neon.sqrshrun.i32(i64 %A, i32 1)
- ret i32 %tmp
-}
-
-define <8 x i8> @sqrshrun8b(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqrshrun8b:
-;CHECK: sqrshrun.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqrshrun4h(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqrshrun4h:
-;CHECK: sqrshrun.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqrshrun2s(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqrshrun2s:
-;CHECK: sqrshrun.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqrshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqrshrun16b:
-;CHECK: sqrshrun2.16b v0, {{v[0-9]+}}, #1
- %out = load <8 x i8>* %ret
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)
- %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @sqrshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqrshrun8h:
-;CHECK: sqrshrun2.8h v0, {{v[0-9]+}}, #1
- %out = load <4 x i16>* %ret
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)
- %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @sqrshrun4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqrshrun4s:
-;CHECK: sqrshrun2.4s v0, {{v[0-9]+}}, #1
- %out = load <2 x i32>* %ret
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)
- %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %tmp4
-}
-
-declare i32 @llvm.arm64.neon.sqrshrun.i32(i64, i32) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.sqrshrun.v8i8(<8 x i16>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqrshrun.v4i16(<4 x i32>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqrshrun.v2i32(<2 x i64>, i32) nounwind readnone
-
-define i32 @uqrshrn1s(i64 %A) nounwind {
-; CHECK-LABEL: uqrshrn1s:
-; CHECK: uqrshrn {{s[0-9]+}}, d0, #1
- %tmp = call i32 @llvm.arm64.neon.uqrshrn.i32(i64 %A, i32 1)
- ret i32 %tmp
-}
-
-define <8 x i8> @uqrshrn8b(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: uqrshrn8b:
-;CHECK: uqrshrn.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @uqrshrn4h(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: uqrshrn4h:
-;CHECK: uqrshrn.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @uqrshrn2s(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: uqrshrn2s:
-;CHECK: uqrshrn.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @uqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
-;CHECK-LABEL: uqrshrn16b:
-;CHECK: uqrshrn2.16b v0, {{v[0-9]+}}, #1
- %out = load <8 x i8>* %ret
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
- %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @uqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
-;CHECK-LABEL: uqrshrn8h:
-;CHECK: uqrshrn2.8h v0, {{v[0-9]+}}, #1
- %out = load <4 x i16>* %ret
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
- %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @uqrshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
-;CHECK-LABEL: uqrshrn4s:
-;CHECK: uqrshrn2.4s v0, {{v[0-9]+}}, #1
- %out = load <2 x i32>* %ret
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
- %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %tmp4
-}
-
-declare i32 @llvm.arm64.neon.uqrshrn.i32(i64, i32) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.uqrshrn.v8i8(<8 x i16>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uqrshrn.v4i16(<4 x i32>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uqrshrn.v2i32(<2 x i64>, i32) nounwind readnone
-
-define i32 @uqshrn1s(i64 %A) nounwind {
-; CHECK-LABEL: uqshrn1s:
-; CHECK: uqshrn {{s[0-9]+}}, d0, #1
- %tmp = call i32 @llvm.arm64.neon.uqshrn.i32(i64 %A, i32 1)
- ret i32 %tmp
-}
-
-define <8 x i8> @uqshrn8b(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: uqshrn8b:
-;CHECK: uqshrn.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @uqshrn4h(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: uqshrn4h:
-;CHECK: uqshrn.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @uqshrn2s(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: uqshrn2s:
-;CHECK: uqshrn.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @uqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
-;CHECK-LABEL: uqshrn16b:
-;CHECK: uqshrn2.16b v0, {{v[0-9]+}}, #1
- %out = load <8 x i8>* %ret
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
- %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @uqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
-;CHECK-LABEL: uqshrn8h:
-;CHECK: uqshrn2.8h v0, {{v[0-9]+}}, #1
- %out = load <4 x i16>* %ret
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
- %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @uqshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
-;CHECK-LABEL: uqshrn4s:
-;CHECK: uqshrn2.4s v0, {{v[0-9]+}}, #1
- %out = load <2 x i32>* %ret
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
- %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %tmp4
-}
-
-declare i32 @llvm.arm64.neon.uqshrn.i32(i64, i32) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.uqshrn.v8i8(<8 x i16>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uqshrn.v4i16(<4 x i32>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uqshrn.v2i32(<2 x i64>, i32) nounwind readnone
-
-define <8 x i16> @ushll8h(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: ushll8h:
-;CHECK: ushll.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @ushll4s(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: ushll4s:
-;CHECK: ushll.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @ushll2d(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: ushll2d:
-;CHECK: ushll.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
- ret <2 x i64> %tmp3
-}
-
-define <8 x i16> @ushll2_8h(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: ushll2_8h:
-;CHECK: ushll2.8h v0, {{v[0-9]+}}, #1
- %load1 = load <16 x i8>* %A
- %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @ushll2_4s(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: ushll2_4s:
-;CHECK: ushll2.4s v0, {{v[0-9]+}}, #1
- %load1 = load <8 x i16>* %A
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @ushll2_2d(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: ushll2_2d:
-;CHECK: ushll2.2d v0, {{v[0-9]+}}, #1
- %load1 = load <4 x i32>* %A
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
- ret <2 x i64> %tmp3
-}
-
-define <8 x i16> @sshll8h(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: sshll8h:
-;CHECK: sshll.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @sshll4s(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: sshll4s:
-;CHECK: sshll.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sshll2d(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: sshll2d:
-;CHECK: sshll.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
- ret <2 x i64> %tmp3
-}
-
-define <8 x i16> @sshll2_8h(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: sshll2_8h:
-;CHECK: sshll2.8h v0, {{v[0-9]+}}, #1
- %load1 = load <16 x i8>* %A
- %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @sshll2_4s(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sshll2_4s:
-;CHECK: sshll2.4s v0, {{v[0-9]+}}, #1
- %load1 = load <8 x i16>* %A
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sshll2_2d(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sshll2_2d:
-;CHECK: sshll2.2d v0, {{v[0-9]+}}, #1
- %load1 = load <4 x i32>* %A
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
- ret <2 x i64> %tmp3
-}
-
-define <8 x i8> @sqshli8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: sqshli8b:
-;CHECK: sqshl.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sqshli4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: sqshli4h:
-;CHECK: sqshl.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sqshli2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: sqshli2s:
-;CHECK: sqshl.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @sqshli16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: sqshli16b:
-;CHECK: sqshl.16b v0, {{v[0-9]+}}, #1
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @sqshli8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqshli8h:
-;CHECK: sqshl.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @sqshli4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqshli4s:
-;CHECK: sqshl.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sqshli2d(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: sqshli2d:
-;CHECK: sqshl.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
- ret <2 x i64> %tmp3
-}
-
-define <8 x i8> @uqshli8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: uqshli8b:
-;CHECK: uqshl.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @uqshli4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: uqshli4h:
-;CHECK: uqshl.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @uqshli2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: uqshli2s:
-;CHECK: uqshl.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @uqshli16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: uqshli16b:
-;CHECK: uqshl.16b
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @uqshli8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: uqshli8h:
-;CHECK: uqshl.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @uqshli4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: uqshli4s:
-;CHECK: uqshl.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @uqshli2d(<2 x i64>* %A) nounwind {
-;CHECK-LABEL: uqshli2d:
-;CHECK: uqshl.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
- ret <2 x i64> %tmp3
-}
-
-define <8 x i8> @ursra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: ursra8b:
-;CHECK: ursra.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
- %tmp4 = load <8 x i8>* %B
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @ursra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: ursra4h:
-;CHECK: ursra.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
- %tmp4 = load <4 x i16>* %B
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @ursra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: ursra2s:
-;CHECK: ursra.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
- %tmp4 = load <2 x i32>* %B
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <16 x i8> @ursra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: ursra16b:
-;CHECK: ursra.16b v0, {{v[0-9]+}}, #1
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
- %tmp4 = load <16 x i8>* %B
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @ursra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: ursra8h:
-;CHECK: ursra.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
- %tmp4 = load <8 x i16>* %B
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @ursra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: ursra4s:
-;CHECK: ursra.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
- %tmp4 = load <4 x i32>* %B
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @ursra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: ursra2d:
-;CHECK: ursra.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
- %tmp4 = load <2 x i64>* %B
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i8> @srsra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: srsra8b:
-;CHECK: srsra.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
- %tmp4 = load <8 x i8>* %B
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @srsra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: srsra4h:
-;CHECK: srsra.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
- %tmp4 = load <4 x i16>* %B
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @srsra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: srsra2s:
-;CHECK: srsra.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
- %tmp4 = load <2 x i32>* %B
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <16 x i8> @srsra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: srsra16b:
-;CHECK: srsra.16b v0, {{v[0-9]+}}, #1
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
- %tmp4 = load <16 x i8>* %B
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @srsra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: srsra8h:
-;CHECK: srsra.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
- %tmp4 = load <8 x i16>* %B
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @srsra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: srsra4s:
-;CHECK: srsra.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
- %tmp4 = load <4 x i32>* %B
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @srsra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: srsra2d:
-;CHECK: srsra.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
- %tmp4 = load <2 x i64>* %B
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i8> @usra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: usra8b:
-;CHECK: usra.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %tmp4 = load <8 x i8>* %B
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @usra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: usra4h:
-;CHECK: usra.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
- %tmp4 = load <4 x i16>* %B
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @usra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: usra2s:
-;CHECK: usra.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>
- %tmp4 = load <2 x i32>* %B
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <16 x i8> @usra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: usra16b:
-;CHECK: usra.16b v0, {{v[0-9]+}}, #1
- %tmp1 = load <16 x i8>* %A
- %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %tmp4 = load <16 x i8>* %B
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @usra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: usra8h:
-;CHECK: usra.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- %tmp4 = load <8 x i16>* %B
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @usra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: usra4s:
-;CHECK: usra.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = load <4 x i32>* %B
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @usra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: usra2d:
-;CHECK: usra.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
- %tmp4 = load <2 x i64>* %B
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i8> @ssra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: ssra8b:
-;CHECK: ssra.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp3 = ashr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %tmp4 = load <8 x i8>* %B
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @ssra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: ssra4h:
-;CHECK: ssra.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp3 = ashr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
- %tmp4 = load <4 x i16>* %B
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @ssra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: ssra2s:
-;CHECK: ssra.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp3 = ashr <2 x i32> %tmp1, <i32 1, i32 1>
- %tmp4 = load <2 x i32>* %B
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <16 x i8> @ssra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: ssra16b:
-;CHECK: ssra.16b v0, {{v[0-9]+}}, #1
- %tmp1 = load <16 x i8>* %A
- %tmp3 = ashr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %tmp4 = load <16 x i8>* %B
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @ssra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: ssra8h:
-;CHECK: ssra.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp3 = ashr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- %tmp4 = load <8 x i16>* %B
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @ssra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: ssra4s:
-;CHECK: ssra.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp3 = ashr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
- %tmp4 = load <4 x i32>* %B
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @ssra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: ssra2d:
-;CHECK: ssra.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp3 = ashr <2 x i64> %tmp1, <i64 1, i64 1>
- %tmp4 = load <2 x i64>* %B
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i8> @shr_orr8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: shr_orr8b:
-;CHECK: shr.8b v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.8b
-;CHECK-NEXT: ret
- %tmp1 = load <8 x i8>* %A
- %tmp4 = load <8 x i8>* %B
- %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %tmp5 = or <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @shr_orr4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: shr_orr4h:
-;CHECK: shr.4h v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.8b
-;CHECK-NEXT: ret
- %tmp1 = load <4 x i16>* %A
- %tmp4 = load <4 x i16>* %B
- %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
- %tmp5 = or <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @shr_orr2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: shr_orr2s:
-;CHECK: shr.2s v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.8b
-;CHECK-NEXT: ret
- %tmp1 = load <2 x i32>* %A
- %tmp4 = load <2 x i32>* %B
- %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>
- %tmp5 = or <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <16 x i8> @shr_orr16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: shr_orr16b:
-;CHECK: shr.16b v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.16b
-;CHECK-NEXT: ret
- %tmp1 = load <16 x i8>* %A
- %tmp4 = load <16 x i8>* %B
- %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %tmp5 = or <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @shr_orr8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: shr_orr8h:
-;CHECK: shr.8h v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.16b
-;CHECK-NEXT: ret
- %tmp1 = load <8 x i16>* %A
- %tmp4 = load <8 x i16>* %B
- %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- %tmp5 = or <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @shr_orr4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: shr_orr4s:
-;CHECK: shr.4s v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.16b
-;CHECK-NEXT: ret
- %tmp1 = load <4 x i32>* %A
- %tmp4 = load <4 x i32>* %B
- %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = or <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @shr_orr2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: shr_orr2d:
-;CHECK: shr.2d v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.16b
-;CHECK-NEXT: ret
- %tmp1 = load <2 x i64>* %A
- %tmp4 = load <2 x i64>* %B
- %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
- %tmp5 = or <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i8> @shl_orr8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: shl_orr8b:
-;CHECK: shl.8b v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.8b
-;CHECK-NEXT: ret
- %tmp1 = load <8 x i8>* %A
- %tmp4 = load <8 x i8>* %B
- %tmp3 = shl <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %tmp5 = or <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @shl_orr4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: shl_orr4h:
-;CHECK: shl.4h v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.8b
-;CHECK-NEXT: ret
- %tmp1 = load <4 x i16>* %A
- %tmp4 = load <4 x i16>* %B
- %tmp3 = shl <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
- %tmp5 = or <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @shl_orr2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: shl_orr2s:
-;CHECK: shl.2s v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.8b
-;CHECK-NEXT: ret
- %tmp1 = load <2 x i32>* %A
- %tmp4 = load <2 x i32>* %B
- %tmp3 = shl <2 x i32> %tmp1, <i32 1, i32 1>
- %tmp5 = or <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <16 x i8> @shl_orr16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: shl_orr16b:
-;CHECK: shl.16b v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.16b
-;CHECK-NEXT: ret
- %tmp1 = load <16 x i8>* %A
- %tmp4 = load <16 x i8>* %B
- %tmp3 = shl <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %tmp5 = or <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @shl_orr8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: shl_orr8h:
-;CHECK: shl.8h v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.16b
-;CHECK-NEXT: ret
- %tmp1 = load <8 x i16>* %A
- %tmp4 = load <8 x i16>* %B
- %tmp3 = shl <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
- %tmp5 = or <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @shl_orr4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: shl_orr4s:
-;CHECK: shl.4s v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.16b
-;CHECK-NEXT: ret
- %tmp1 = load <4 x i32>* %A
- %tmp4 = load <4 x i32>* %B
- %tmp3 = shl <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
- %tmp5 = or <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @shl_orr2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: shl_orr2d:
-;CHECK: shl.2d v0, {{v[0-9]+}}, #1
-;CHECK-NEXT: orr.16b
-;CHECK-NEXT: ret
- %tmp1 = load <2 x i64>* %A
- %tmp4 = load <2 x i64>* %B
- %tmp3 = shl <2 x i64> %tmp1, <i64 1, i64 1>
- %tmp5 = or <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @shll(<8 x i8> %in) {
-; CHECK-LABEL: shll:
-; CHECK: shll.8h v0, {{v[0-9]+}}, #8
- %ext = zext <8 x i8> %in to <8 x i16>
- %res = shl <8 x i16> %ext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @shll_high(<8 x i16> %in) {
-; CHECK-LABEL: shll_high
-; CHECK: shll2.4s v0, {{v[0-9]+}}, #16
- %extract = shufflevector <8 x i16> %in, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %ext = zext <4 x i16> %extract to <4 x i32>
- %res = shl <4 x i32> %ext, <i32 16, i32 16, i32 16, i32 16>
- ret <4 x i32> %res
-}
-
-define <8 x i8> @sli8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sli8b:
-;CHECK: sli.8b v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.vsli.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, i32 1)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @sli4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sli4h:
-;CHECK: sli.4h v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.vsli.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, i32 1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @sli2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sli2s:
-;CHECK: sli.2s v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.vsli.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, i32 1)
- ret <2 x i32> %tmp3
-}
-
-define <1 x i64> @sli1d(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK-LABEL: sli1d:
-;CHECK: sli d0, {{d[0-9]+}}, #1
- %tmp1 = load <1 x i64>* %A
- %tmp2 = load <1 x i64>* %B
- %tmp3 = call <1 x i64> @llvm.arm64.neon.vsli.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, i32 1)
- ret <1 x i64> %tmp3
-}
-
-define <16 x i8> @sli16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sli16b:
-;CHECK: sli.16b v0, {{v[0-9]+}}, #1
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.vsli.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, i32 1)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @sli8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sli8h:
-;CHECK: sli.8h v0, {{v[0-9]+}}, #1
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.vsli.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, i32 1)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @sli4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sli4s:
-;CHECK: sli.4s v0, {{v[0-9]+}}, #1
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.vsli.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, i32 1)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @sli2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: sli2d:
-;CHECK: sli.2d v0, {{v[0-9]+}}, #1
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.vsli.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, i32 1)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.vsli.v8i8(<8 x i8>, <8 x i8>, i32) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.vsli.v4i16(<4 x i16>, <4 x i16>, i32) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.vsli.v2i32(<2 x i32>, <2 x i32>, i32) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) nounwind readnone
-
-declare <16 x i8> @llvm.arm64.neon.vsli.v16i8(<16 x i8>, <16 x i8>, i32) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.vsli.v8i16(<8 x i16>, <8 x i16>, i32) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.vsli.v4i32(<4 x i32>, <4 x i32>, i32) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.vsli.v2i64(<2 x i64>, <2 x i64>, i32) nounwind readnone
-
-define <1 x i64> @ashr_v1i64(<1 x i64> %a, <1 x i64> %b) {
-; CHECK-LABEL: ashr_v1i64:
-; CHECK: neg d{{[0-9]+}}, d{{[0-9]+}}
-; CHECK: sshl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
- %c = ashr <1 x i64> %a, %b
- ret <1 x i64> %c
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vshr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vshr.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vshr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vshr.ll (removed)
@@ -1,63 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
-
-define <8 x i16> @testShiftRightArith_v8i16(<8 x i16> %a, <8 x i16> %b) #0 {
-; CHECK-LABEL: testShiftRightArith_v8i16:
-; CHECK: neg.8h [[REG1:v[0-9]+]], [[REG1]]
-; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
-
-entry:
- %a.addr = alloca <8 x i16>, align 16
- %b.addr = alloca <8 x i16>, align 16
- store <8 x i16> %a, <8 x i16>* %a.addr, align 16
- store <8 x i16> %b, <8 x i16>* %b.addr, align 16
- %0 = load <8 x i16>* %a.addr, align 16
- %1 = load <8 x i16>* %b.addr, align 16
- %shr = ashr <8 x i16> %0, %1
- ret <8 x i16> %shr
-}
-
-define <4 x i32> @testShiftRightArith_v4i32(<4 x i32> %a, <4 x i32> %b) #0 {
-; CHECK-LABEL: testShiftRightArith_v4i32:
-; CHECK: neg.4s [[REG3:v[0-9]+]], [[REG3]]
-; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]
-entry:
- %a.addr = alloca <4 x i32>, align 32
- %b.addr = alloca <4 x i32>, align 32
- store <4 x i32> %a, <4 x i32>* %a.addr, align 32
- store <4 x i32> %b, <4 x i32>* %b.addr, align 32
- %0 = load <4 x i32>* %a.addr, align 32
- %1 = load <4 x i32>* %b.addr, align 32
- %shr = ashr <4 x i32> %0, %1
- ret <4 x i32> %shr
-}
-
-define <8 x i16> @testShiftRightLogical(<8 x i16> %a, <8 x i16> %b) #0 {
-; CHECK: testShiftRightLogical
-; CHECK: neg.8h [[REG5:v[0-9]+]], [[REG5]]
-; CHECK-NEXT: ushl.8h [[REG6:v[0-9]+]], [[REG6]], [[REG5]]
-entry:
- %a.addr = alloca <8 x i16>, align 16
- %b.addr = alloca <8 x i16>, align 16
- store <8 x i16> %a, <8 x i16>* %a.addr, align 16
- store <8 x i16> %b, <8 x i16>* %b.addr, align 16
- %0 = load <8 x i16>* %a.addr, align 16
- %1 = load <8 x i16>* %b.addr, align 16
- %shr = lshr <8 x i16> %0, %1
- ret <8 x i16> %shr
-}
-
-define <1 x i64> @sshr_v1i64(<1 x i64> %A) nounwind {
-; CHECK-LABEL: sshr_v1i64:
-; CHECK: sshr d0, d0, #63
- %tmp3 = ashr <1 x i64> %A, < i64 63 >
- ret <1 x i64> %tmp3
-}
-
-define <1 x i64> @ushr_v1i64(<1 x i64> %A) nounwind {
-; CHECK-LABEL: ushr_v1i64:
-; CHECK: ushr d0, d0, #63
- %tmp3 = lshr <1 x i64> %A, < i64 63 >
- ret <1 x i64> %tmp3
-}
-
-attributes #0 = { nounwind }
Removed: llvm/trunk/test/CodeGen/ARM64/vshuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vshuffle.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vshuffle.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vshuffle.ll (removed)
@@ -1,115 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
-
-
-; The mask:
-; CHECK: lCPI0_0:
-; CHECK: .byte 2 ; 0x2
-; CHECK: .byte 255 ; 0xff
-; CHECK: .byte 6 ; 0x6
-; CHECK: .byte 255 ; 0xff
-; The second vector is legalized to undef and the elements of the first vector
-; are used instead.
-; CHECK: .byte 2 ; 0x2
-; CHECK: .byte 4 ; 0x4
-; CHECK: .byte 6 ; 0x6
-; CHECK: .byte 0 ; 0x0
-; CHECK: test1
-; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI0_0
-; CHECK: movi.8h v[[REG1:[0-9]+]], #0x1, lsl #8
-; CHECK: tbl.8b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
-define <8 x i1> @test1() {
-entry:
- %Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
- i1 7>,
- <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
- i1 7>,
- <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10,
- i32 12, i32 14, i32 0>
- ret <8 x i1> %Shuff
-}
-
-; CHECK: lCPI1_0:
-; CHECK: .byte 2 ; 0x2
-; CHECK: .byte 255 ; 0xff
-; CHECK: .byte 6 ; 0x6
-; CHECK: .byte 255 ; 0xff
-; CHECK: .byte 10 ; 0xa
-; CHECK: .byte 12 ; 0xc
-; CHECK: .byte 14 ; 0xe
-; CHECK: .byte 0 ; 0x0
-; CHECK: test2
-; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI1_0 at PAGEOFF]
-; CHECK: adrp x[[REG2:[0-9]+]], lCPI1_1 at PAGE
-; CHECK: ldr q[[REG1:[0-9]+]], [x[[REG2]], lCPI1_1 at PAGEOFF]
-; CHECK: tbl.8b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
-define <8 x i1>@test2() {
-bb:
- %Shuff = shufflevector <8 x i1> zeroinitializer,
- <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
- <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
- i32 0>
- ret <8 x i1> %Shuff
-}
-
-; CHECK: lCPI2_0:
-; CHECK: .byte 2 ; 0x2
-; CHECK: .byte 255 ; 0xff
-; CHECK: .byte 6 ; 0x6
-; CHECK: .byte 255 ; 0xff
-; CHECK: .byte 10 ; 0xa
-; CHECK: .byte 12 ; 0xc
-; CHECK: .byte 14 ; 0xe
-; CHECK: .byte 0 ; 0x0
-; CHECK: .byte 2 ; 0x2
-; CHECK: .byte 255 ; 0xff
-; CHECK: .byte 6 ; 0x6
-; CHECK: .byte 255 ; 0xff
-; CHECK: .byte 10 ; 0xa
-; CHECK: .byte 12 ; 0xc
-; CHECK: .byte 14 ; 0xe
-; CHECK: .byte 0 ; 0x0
-; CHECK: test3
-; CHECK: adrp x[[REG3:[0-9]+]], lCPI2_0 at PAGE
-; CHECK: ldr q[[REG0:[0-9]+]], [x[[REG3]], lCPI2_0 at PAGEOFF]
-; CHECK: ldr q[[REG1:[0-9]+]], [x[[REG3]], lCPI2_1 at PAGEOFF]
-; CHECK: tbl.16b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
-define <16 x i1> @test3(i1* %ptr, i32 %v) {
-bb:
- %Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef,
- <16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
- i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12,
- i32 14, i32 0>
- ret <16 x i1> %Shuff
-}
-; CHECK: lCPI3_1:
-; CHECK: .byte 2 ; 0x2
-; CHECK: .byte 1 ; 0x1
-; CHECK: .byte 6 ; 0x6
-; CHECK: .byte 18 ; 0x12
-; CHECK: .byte 10 ; 0xa
-; CHECK: .byte 12 ; 0xc
-; CHECK: .byte 14 ; 0xe
-; CHECK: .byte 0 ; 0x0
-; CHECK: .byte 2 ; 0x2
-; CHECK: .byte 31 ; 0x1f
-; CHECK: .byte 6 ; 0x6
-; CHECK: .byte 30 ; 0x1e
-; CHECK: .byte 10 ; 0xa
-; CHECK: .byte 12 ; 0xc
-; CHECK: .byte 14 ; 0xe
-; CHECK: .byte 0 ; 0x0
-; CHECK: _test4:
-; CHECK: ldr q[[REG1:[0-9]+]]
-; CHECK: movi.2d v[[REG0:[0-9]+]], #0000000000000000
-; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_1 at PAGE
-; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_1 at PAGEOFF]
-; CHECK: tbl.16b v{{[0-9]+}}, { v[[REG0]], v[[REG1]] }, v[[REG2]]
-define <16 x i1> @test4(i1* %ptr, i32 %v) {
-bb:
- %Shuff = shufflevector <16 x i1> zeroinitializer,
- <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,
- i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
- <16 x i32> <i32 2, i32 1, i32 6, i32 18, i32 10, i32 12, i32 14, i32 0,
- i32 2, i32 31, i32 6, i32 30, i32 10, i32 12, i32 14, i32 0>
- ret <16 x i1> %Shuff
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vsqrt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vsqrt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vsqrt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vsqrt.ll (removed)
@@ -1,232 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <2 x float> @frecps_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: frecps_2s:
-;CHECK: frecps.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frecps_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: frecps_4s:
-;CHECK: frecps.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frecps_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: frecps_2d:
-;CHECK: frecps.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-
-define <2 x float> @frsqrts_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: frsqrts_2s:
-;CHECK: frsqrts.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frsqrts_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: frsqrts_4s:
-;CHECK: frsqrts.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frsqrts_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: frsqrts_2d:
-;CHECK: frsqrts.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.frsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.frsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.frsqrts.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <2 x float> @frecpe_2s(<2 x float>* %A) nounwind {
-;CHECK-LABEL: frecpe_2s:
-;CHECK: frecpe.2s
- %tmp1 = load <2 x float>* %A
- %tmp3 = call <2 x float> @llvm.arm64.neon.frecpe.v2f32(<2 x float> %tmp1)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frecpe_4s(<4 x float>* %A) nounwind {
-;CHECK-LABEL: frecpe_4s:
-;CHECK: frecpe.4s
- %tmp1 = load <4 x float>* %A
- %tmp3 = call <4 x float> @llvm.arm64.neon.frecpe.v4f32(<4 x float> %tmp1)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frecpe_2d(<2 x double>* %A) nounwind {
-;CHECK-LABEL: frecpe_2d:
-;CHECK: frecpe.2d
- %tmp1 = load <2 x double>* %A
- %tmp3 = call <2 x double> @llvm.arm64.neon.frecpe.v2f64(<2 x double> %tmp1)
- ret <2 x double> %tmp3
-}
-
-define float @frecpe_s(float* %A) nounwind {
-;CHECK-LABEL: frecpe_s:
-;CHECK: frecpe s0, {{s[0-9]+}}
- %tmp1 = load float* %A
- %tmp3 = call float @llvm.arm64.neon.frecpe.f32(float %tmp1)
- ret float %tmp3
-}
-
-define double @frecpe_d(double* %A) nounwind {
-;CHECK-LABEL: frecpe_d:
-;CHECK: frecpe d0, {{d[0-9]+}}
- %tmp1 = load double* %A
- %tmp3 = call double @llvm.arm64.neon.frecpe.f64(double %tmp1)
- ret double %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.frecpe.v2f32(<2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.frecpe.v4f32(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.frecpe.v2f64(<2 x double>) nounwind readnone
-declare float @llvm.arm64.neon.frecpe.f32(float) nounwind readnone
-declare double @llvm.arm64.neon.frecpe.f64(double) nounwind readnone
-
-define float @frecpx_s(float* %A) nounwind {
-;CHECK-LABEL: frecpx_s:
-;CHECK: frecpx s0, {{s[0-9]+}}
- %tmp1 = load float* %A
- %tmp3 = call float @llvm.arm64.neon.frecpx.f32(float %tmp1)
- ret float %tmp3
-}
-
-define double @frecpx_d(double* %A) nounwind {
-;CHECK-LABEL: frecpx_d:
-;CHECK: frecpx d0, {{d[0-9]+}}
- %tmp1 = load double* %A
- %tmp3 = call double @llvm.arm64.neon.frecpx.f64(double %tmp1)
- ret double %tmp3
-}
-
-declare float @llvm.arm64.neon.frecpx.f32(float) nounwind readnone
-declare double @llvm.arm64.neon.frecpx.f64(double) nounwind readnone
-
-define <2 x float> @frsqrte_2s(<2 x float>* %A) nounwind {
-;CHECK-LABEL: frsqrte_2s:
-;CHECK: frsqrte.2s
- %tmp1 = load <2 x float>* %A
- %tmp3 = call <2 x float> @llvm.arm64.neon.frsqrte.v2f32(<2 x float> %tmp1)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @frsqrte_4s(<4 x float>* %A) nounwind {
-;CHECK-LABEL: frsqrte_4s:
-;CHECK: frsqrte.4s
- %tmp1 = load <4 x float>* %A
- %tmp3 = call <4 x float> @llvm.arm64.neon.frsqrte.v4f32(<4 x float> %tmp1)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @frsqrte_2d(<2 x double>* %A) nounwind {
-;CHECK-LABEL: frsqrte_2d:
-;CHECK: frsqrte.2d
- %tmp1 = load <2 x double>* %A
- %tmp3 = call <2 x double> @llvm.arm64.neon.frsqrte.v2f64(<2 x double> %tmp1)
- ret <2 x double> %tmp3
-}
-
-define float @frsqrte_s(float* %A) nounwind {
-;CHECK-LABEL: frsqrte_s:
-;CHECK: frsqrte s0, {{s[0-9]+}}
- %tmp1 = load float* %A
- %tmp3 = call float @llvm.arm64.neon.frsqrte.f32(float %tmp1)
- ret float %tmp3
-}
-
-define double @frsqrte_d(double* %A) nounwind {
-;CHECK-LABEL: frsqrte_d:
-;CHECK: frsqrte d0, {{d[0-9]+}}
- %tmp1 = load double* %A
- %tmp3 = call double @llvm.arm64.neon.frsqrte.f64(double %tmp1)
- ret double %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.frsqrte.v2f32(<2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.frsqrte.v4f32(<4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.frsqrte.v2f64(<2 x double>) nounwind readnone
-declare float @llvm.arm64.neon.frsqrte.f32(float) nounwind readnone
-declare double @llvm.arm64.neon.frsqrte.f64(double) nounwind readnone
-
-define <2 x i32> @urecpe_2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: urecpe_2s:
-;CHECK: urecpe.2s
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.urecpe.v2i32(<2 x i32> %tmp1)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @urecpe_4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: urecpe_4s:
-;CHECK: urecpe.4s
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.urecpe.v4i32(<4 x i32> %tmp1)
- ret <4 x i32> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.urecpe.v2i32(<2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.urecpe.v4i32(<4 x i32>) nounwind readnone
-
-define <2 x i32> @ursqrte_2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: ursqrte_2s:
-;CHECK: ursqrte.2s
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.ursqrte.v2i32(<2 x i32> %tmp1)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @ursqrte_4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: ursqrte_4s:
-;CHECK: ursqrte.4s
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.ursqrte.v4i32(<4 x i32> %tmp1)
- ret <4 x i32> %tmp3
-}
-
-declare <2 x i32> @llvm.arm64.neon.ursqrte.v2i32(<2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.ursqrte.v4i32(<4 x i32>) nounwind readnone
-
-define float @f1(float %a, float %b) nounwind readnone optsize ssp {
-; CHECK-LABEL: f1:
-; CHECK: frsqrts s0, s0, s1
-; CHECK-NEXT: ret
- %vrsqrtss.i = tail call float @llvm.arm64.neon.frsqrts.f32(float %a, float %b) nounwind
- ret float %vrsqrtss.i
-}
-
-define double @f2(double %a, double %b) nounwind readnone optsize ssp {
-; CHECK-LABEL: f2:
-; CHECK: frsqrts d0, d0, d1
-; CHECK-NEXT: ret
- %vrsqrtsd.i = tail call double @llvm.arm64.neon.frsqrts.f64(double %a, double %b) nounwind
- ret double %vrsqrtsd.i
-}
-
-declare double @llvm.arm64.neon.frsqrts.f64(double, double) nounwind readnone
-declare float @llvm.arm64.neon.frsqrts.f32(float, float) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/vsra.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vsra.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vsra.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vsra.ll (removed)
@@ -1,150 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsras8:
-;CHECK: ssra.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
- %tmp4 = add <8 x i8> %tmp1, %tmp3
- ret <8 x i8> %tmp4
-}
-
-define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsras16:
-;CHECK: ssra.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
- %tmp4 = add <4 x i16> %tmp1, %tmp3
- ret <4 x i16> %tmp4
-}
-
-define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsras32:
-;CHECK: ssra.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 >
- %tmp4 = add <2 x i32> %tmp1, %tmp3
- ret <2 x i32> %tmp4
-}
-
-define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vsraQs8:
-;CHECK: ssra.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
- %tmp4 = add <16 x i8> %tmp1, %tmp3
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vsraQs16:
-;CHECK: ssra.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
- %tmp4 = add <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vsraQs32:
-;CHECK: ssra.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
- %tmp4 = add <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vsraQs64:
-;CHECK: ssra.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 >
- %tmp4 = add <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsrau8:
-;CHECK: usra.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
- %tmp4 = add <8 x i8> %tmp1, %tmp3
- ret <8 x i8> %tmp4
-}
-
-define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsrau16:
-;CHECK: usra.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
- %tmp4 = add <4 x i16> %tmp1, %tmp3
- ret <4 x i16> %tmp4
-}
-
-define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsrau32:
-;CHECK: usra.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 >
- %tmp4 = add <2 x i32> %tmp1, %tmp3
- ret <2 x i32> %tmp4
-}
-
-
-define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vsraQu8:
-;CHECK: usra.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
- %tmp4 = add <16 x i8> %tmp1, %tmp3
- ret <16 x i8> %tmp4
-}
-
-define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vsraQu16:
-;CHECK: usra.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
- %tmp4 = add <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vsraQu32:
-;CHECK: usra.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
- %tmp4 = add <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vsraQu64:
-;CHECK: usra.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 >
- %tmp4 = add <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
-}
-
-define <1 x i64> @vsra_v1i64(<1 x i64> %A, <1 x i64> %B) nounwind {
-; CHECK-LABEL: vsra_v1i64:
-; CHECK: ssra d0, d1, #63
- %tmp3 = ashr <1 x i64> %B, < i64 63 >
- %tmp4 = add <1 x i64> %A, %tmp3
- ret <1 x i64> %tmp4
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vsub.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vsub.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vsub.ll (removed)
@@ -1,417 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @subhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: subhn8b:
-;CHECK: subhn.8b
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @subhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: subhn4h:
-;CHECK: subhn.4h
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.subhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @subhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: subhn2s:
-;CHECK: subhn.2s
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.subhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @subhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind {
-;CHECK-LABEL: subhn2_16b:
-;CHECK: subhn.8b
-;CHECK-NEXT: subhn2.16b
- %vsubhn2.i = tail call <8 x i8> @llvm.arm64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
- %vsubhn_high2.i = tail call <8 x i8> @llvm.arm64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
- %res = shufflevector <8 x i8> %vsubhn2.i, <8 x i8> %vsubhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @subhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind {
-;CHECK-LABEL: subhn2_8h:
-;CHECK: subhn.4h
-;CHECK-NEXT: subhn2.8h
- %vsubhn2.i = tail call <4 x i16> @llvm.arm64.neon.subhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
- %vsubhn_high3.i = tail call <4 x i16> @llvm.arm64.neon.subhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
- %res = shufflevector <4 x i16> %vsubhn2.i, <4 x i16> %vsubhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @subhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind {
-;CHECK-LABEL: subhn2_4s:
-;CHECK: subhn.2s
-;CHECK-NEXT: subhn2.4s
- %vsubhn2.i = tail call <2 x i32> @llvm.arm64.neon.subhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
- %vsubhn_high3.i = tail call <2 x i32> @llvm.arm64.neon.subhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
- %res = shufflevector <2 x i32> %vsubhn2.i, <2 x i32> %vsubhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
-
-declare <2 x i32> @llvm.arm64.neon.subhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.subhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.subhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-
-define <8 x i8> @rsubhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: rsubhn8b:
-;CHECK: rsubhn.8b
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @rsubhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: rsubhn4h:
-;CHECK: rsubhn.4h
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @rsubhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: rsubhn2s:
-;CHECK: rsubhn.2s
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.rsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @rsubhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind {
-;CHECK-LABEL: rsubhn2_16b:
-;CHECK: rsubhn.8b
-;CHECK-NEXT: rsubhn2.16b
- %vrsubhn2.i = tail call <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
- %vrsubhn_high2.i = tail call <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
- %res = shufflevector <8 x i8> %vrsubhn2.i, <8 x i8> %vrsubhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @rsubhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind {
-;CHECK-LABEL: rsubhn2_8h:
-;CHECK: rsubhn.4h
-;CHECK-NEXT: rsubhn2.8h
- %vrsubhn2.i = tail call <4 x i16> @llvm.arm64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
- %vrsubhn_high3.i = tail call <4 x i16> @llvm.arm64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
- %res = shufflevector <4 x i16> %vrsubhn2.i, <4 x i16> %vrsubhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @rsubhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind {
-;CHECK-LABEL: rsubhn2_4s:
-;CHECK: rsubhn.2s
-;CHECK-NEXT: rsubhn2.4s
- %vrsubhn2.i = tail call <2 x i32> @llvm.arm64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
- %vrsubhn_high3.i = tail call <2 x i32> @llvm.arm64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
- %res = shufflevector <2 x i32> %vrsubhn2.i, <2 x i32> %vrsubhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
-
-declare <2 x i32> @llvm.arm64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-
-define <8 x i16> @ssubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: ssubl8h:
-;CHECK: ssubl.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = sub <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @ssubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: ssubl4s:
-;CHECK: ssubl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = sub <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @ssubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: ssubl2d:
-;CHECK: ssubl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = sub <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @ssubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: ssubl2_8h:
-;CHECK: ssubl2.8h
- %tmp1 = load <16 x i8>* %A
- %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %ext1 = sext <8 x i8> %high1 to <8 x i16>
-
- %tmp2 = load <16 x i8>* %B
- %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %ext2 = sext <8 x i8> %high2 to <8 x i16>
-
- %res = sub <8 x i16> %ext1, %ext2
- ret <8 x i16> %res
-}
-
-define <4 x i32> @ssubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: ssubl2_4s:
-;CHECK: ssubl2.4s
- %tmp1 = load <8 x i16>* %A
- %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %ext1 = sext <4 x i16> %high1 to <4 x i32>
-
- %tmp2 = load <8 x i16>* %B
- %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %ext2 = sext <4 x i16> %high2 to <4 x i32>
-
- %res = sub <4 x i32> %ext1, %ext2
- ret <4 x i32> %res
-}
-
-define <2 x i64> @ssubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: ssubl2_2d:
-;CHECK: ssubl2.2d
- %tmp1 = load <4 x i32>* %A
- %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %ext1 = sext <2 x i32> %high1 to <2 x i64>
-
- %tmp2 = load <4 x i32>* %B
- %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %ext2 = sext <2 x i32> %high2 to <2 x i64>
-
- %res = sub <2 x i64> %ext1, %ext2
- ret <2 x i64> %res
-}
-
-define <8 x i16> @usubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: usubl8h:
-;CHECK: usubl.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = sub <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @usubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: usubl4s:
-;CHECK: usubl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = sub <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @usubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: usubl2d:
-;CHECK: usubl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = sub <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @usubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: usubl2_8h:
-;CHECK: usubl2.8h
- %tmp1 = load <16 x i8>* %A
- %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %ext1 = zext <8 x i8> %high1 to <8 x i16>
-
- %tmp2 = load <16 x i8>* %B
- %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %ext2 = zext <8 x i8> %high2 to <8 x i16>
-
- %res = sub <8 x i16> %ext1, %ext2
- ret <8 x i16> %res
-}
-
-define <4 x i32> @usubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: usubl2_4s:
-;CHECK: usubl2.4s
- %tmp1 = load <8 x i16>* %A
- %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %ext1 = zext <4 x i16> %high1 to <4 x i32>
-
- %tmp2 = load <8 x i16>* %B
- %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %ext2 = zext <4 x i16> %high2 to <4 x i32>
-
- %res = sub <4 x i32> %ext1, %ext2
- ret <4 x i32> %res
-}
-
-define <2 x i64> @usubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: usubl2_2d:
-;CHECK: usubl2.2d
- %tmp1 = load <4 x i32>* %A
- %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %ext1 = zext <2 x i32> %high1 to <2 x i64>
-
- %tmp2 = load <4 x i32>* %B
- %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %ext2 = zext <2 x i32> %high2 to <2 x i64>
-
- %res = sub <2 x i64> %ext1, %ext2
- ret <2 x i64> %res
-}
-
-define <8 x i16> @ssubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: ssubw8h:
-;CHECK: ssubw.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp4 = sub <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @ssubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: ssubw4s:
-;CHECK: ssubw.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp4 = sub <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @ssubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: ssubw2d:
-;CHECK: ssubw.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp4 = sub <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @ssubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: ssubw2_8h:
-;CHECK: ssubw2.8h
- %tmp1 = load <8 x i16>* %A
-
- %tmp2 = load <16 x i8>* %B
- %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %ext2 = sext <8 x i8> %high2 to <8 x i16>
-
- %res = sub <8 x i16> %tmp1, %ext2
- ret <8 x i16> %res
-}
-
-define <4 x i32> @ssubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: ssubw2_4s:
-;CHECK: ssubw2.4s
- %tmp1 = load <4 x i32>* %A
-
- %tmp2 = load <8 x i16>* %B
- %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %ext2 = sext <4 x i16> %high2 to <4 x i32>
-
- %res = sub <4 x i32> %tmp1, %ext2
- ret <4 x i32> %res
-}
-
-define <2 x i64> @ssubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: ssubw2_2d:
-;CHECK: ssubw2.2d
- %tmp1 = load <2 x i64>* %A
-
- %tmp2 = load <4 x i32>* %B
- %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %ext2 = sext <2 x i32> %high2 to <2 x i64>
-
- %res = sub <2 x i64> %tmp1, %ext2
- ret <2 x i64> %res
-}
-
-define <8 x i16> @usubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: usubw8h:
-;CHECK: usubw.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp4 = sub <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @usubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: usubw4s:
-;CHECK: usubw.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp4 = sub <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @usubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: usubw2d:
-;CHECK: usubw.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp4 = sub <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @usubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: usubw2_8h:
-;CHECK: usubw2.8h
- %tmp1 = load <8 x i16>* %A
-
- %tmp2 = load <16 x i8>* %B
- %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %ext2 = zext <8 x i8> %high2 to <8 x i16>
-
- %res = sub <8 x i16> %tmp1, %ext2
- ret <8 x i16> %res
-}
-
-define <4 x i32> @usubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: usubw2_4s:
-;CHECK: usubw2.4s
- %tmp1 = load <4 x i32>* %A
-
- %tmp2 = load <8 x i16>* %B
- %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %ext2 = zext <4 x i16> %high2 to <4 x i32>
-
- %res = sub <4 x i32> %tmp1, %ext2
- ret <4 x i32> %res
-}
-
-define <2 x i64> @usubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: usubw2_2d:
-;CHECK: usubw2.2d
- %tmp1 = load <2 x i64>* %A
-
- %tmp2 = load <4 x i32>* %B
- %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %ext2 = zext <2 x i32> %high2 to <2 x i64>
-
- %res = sub <2 x i64> %tmp1, %ext2
- ret <2 x i64> %res
-}
Removed: llvm/trunk/test/CodeGen/ARM64/weak-reference.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/weak-reference.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/weak-reference.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/weak-reference.ll (removed)
@@ -1,10 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
-
- at x = extern_weak global i32
-
-define i32 @fn() nounwind ssp {
-; CHECK-LABEL: fn:
-; CHECK: .weak_reference
- %val = load i32* @x, align 4
- ret i32 %val
-}
Removed: llvm/trunk/test/CodeGen/ARM64/xaluo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/xaluo.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/xaluo.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/xaluo.ll (removed)
@@ -1,524 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-;
-; Get the actual value of the overflow bit.
-;
-define i1 @saddo.i32(i32 %v1, i32 %v2, i32* %res) {
-entry:
-; CHECK-LABEL: saddo.i32
-; CHECK: adds w8, w0, w1
-; CHECK-NEXT: cset w0, vs
- %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- store i32 %val, i32* %res
- ret i1 %obit
-}
-
-define i1 @saddo.i64(i64 %v1, i64 %v2, i64* %res) {
-entry:
-; CHECK-LABEL: saddo.i64
-; CHECK: adds x8, x0, x1
-; CHECK-NEXT: cset w0, vs
- %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- store i64 %val, i64* %res
- ret i1 %obit
-}
-
-define i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
-entry:
-; CHECK-LABEL: uaddo.i32
-; CHECK: adds w8, w0, w1
-; CHECK-NEXT: cset w0, hs
- %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- store i32 %val, i32* %res
- ret i1 %obit
-}
-
-define i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
-entry:
-; CHECK-LABEL: uaddo.i64
-; CHECK: adds x8, x0, x1
-; CHECK-NEXT: cset w0, hs
- %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- store i64 %val, i64* %res
- ret i1 %obit
-}
-
-define i1 @ssubo.i32(i32 %v1, i32 %v2, i32* %res) {
-entry:
-; CHECK-LABEL: ssubo.i32
-; CHECK: subs w8, w0, w1
-; CHECK-NEXT: cset w0, vs
- %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- store i32 %val, i32* %res
- ret i1 %obit
-}
-
-define i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
-entry:
-; CHECK-LABEL: ssubo.i64
-; CHECK: subs x8, x0, x1
-; CHECK-NEXT: cset w0, vs
- %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- store i64 %val, i64* %res
- ret i1 %obit
-}
-
-define i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
-entry:
-; CHECK-LABEL: usubo.i32
-; CHECK: subs w8, w0, w1
-; CHECK-NEXT: cset w0, lo
- %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- store i32 %val, i32* %res
- ret i1 %obit
-}
-
-define i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
-entry:
-; CHECK-LABEL: usubo.i64
-; CHECK: subs x8, x0, x1
-; CHECK-NEXT: cset w0, lo
- %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- store i64 %val, i64* %res
- ret i1 %obit
-}
-
-define i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
-entry:
-; CHECK-LABEL: smulo.i32
-; CHECK: smull x8, w0, w1
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: cmp w9, w8, asr #31
-; CHECK-NEXT: cset w0, ne
- %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- store i32 %val, i32* %res
- ret i1 %obit
-}
-
-define i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
-entry:
-; CHECK-LABEL: smulo.i64
-; CHECK: mul x8, x0, x1
-; CHECK-NEXT: smulh x9, x0, x1
-; CHECK-NEXT: cmp x9, x8, asr #63
-; CHECK-NEXT: cset w0, ne
- %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- store i64 %val, i64* %res
- ret i1 %obit
-}
-
-define i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
-entry:
-; CHECK-LABEL: umulo.i32
-; CHECK: umull x8, w0, w1
-; CHECK-NEXT: cmp xzr, x8, lsr #32
-; CHECK-NEXT: cset w0, ne
- %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- store i32 %val, i32* %res
- ret i1 %obit
-}
-
-define i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
-entry:
-; CHECK-LABEL: umulo.i64
-; CHECK: umulh x8, x0, x1
-; CHECK-NEXT: cmp xzr, x8
-; CHECK-NEXT: cset w8, ne
-; CHECK-NEXT: mul x9, x0, x1
- %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- store i64 %val, i64* %res
- ret i1 %obit
-}
-
-
-;
-; Check the use of the overflow bit in combination with a select instruction.
-;
-define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: saddo.select.i32
-; CHECK: cmn w0, w1
-; CHECK-NEXT: csel w0, w0, w1, vs
- %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
- %obit = extractvalue {i32, i1} %t, 1
- %ret = select i1 %obit, i32 %v1, i32 %v2
- ret i32 %ret
-}
-
-define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: saddo.select.i64
-; CHECK: cmn x0, x1
-; CHECK-NEXT: csel x0, x0, x1, vs
- %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
- %obit = extractvalue {i64, i1} %t, 1
- %ret = select i1 %obit, i64 %v1, i64 %v2
- ret i64 %ret
-}
-
-define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: uaddo.select.i32
-; CHECK: cmn w0, w1
-; CHECK-NEXT: csel w0, w0, w1, hs
- %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
- %obit = extractvalue {i32, i1} %t, 1
- %ret = select i1 %obit, i32 %v1, i32 %v2
- ret i32 %ret
-}
-
-define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: uaddo.select.i64
-; CHECK: cmn x0, x1
-; CHECK-NEXT: csel x0, x0, x1, hs
- %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
- %obit = extractvalue {i64, i1} %t, 1
- %ret = select i1 %obit, i64 %v1, i64 %v2
- ret i64 %ret
-}
-
-define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: ssubo.select.i32
-; CHECK: cmp w0, w1
-; CHECK-NEXT: csel w0, w0, w1, vs
- %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
- %obit = extractvalue {i32, i1} %t, 1
- %ret = select i1 %obit, i32 %v1, i32 %v2
- ret i32 %ret
-}
-
-define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: ssubo.select.i64
-; CHECK: cmp x0, x1
-; CHECK-NEXT: csel x0, x0, x1, vs
- %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
- %obit = extractvalue {i64, i1} %t, 1
- %ret = select i1 %obit, i64 %v1, i64 %v2
- ret i64 %ret
-}
-
-define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: usubo.select.i32
-; CHECK: cmp w0, w1
-; CHECK-NEXT: csel w0, w0, w1, lo
- %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
- %obit = extractvalue {i32, i1} %t, 1
- %ret = select i1 %obit, i32 %v1, i32 %v2
- ret i32 %ret
-}
-
-define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: usubo.select.i64
-; CHECK: cmp x0, x1
-; CHECK-NEXT: csel x0, x0, x1, lo
- %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
- %obit = extractvalue {i64, i1} %t, 1
- %ret = select i1 %obit, i64 %v1, i64 %v2
- ret i64 %ret
-}
-
-define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: smulo.select.i32
-; CHECK: smull x8, w0, w1
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: cmp w9, w8, asr #31
-; CHECK-NEXT: csel w0, w0, w1, ne
- %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
- %obit = extractvalue {i32, i1} %t, 1
- %ret = select i1 %obit, i32 %v1, i32 %v2
- ret i32 %ret
-}
-
-define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: smulo.select.i64
-; CHECK: mul x8, x0, x1
-; CHECK-NEXT: smulh x9, x0, x1
-; CHECK-NEXT: cmp x9, x8, asr #63
-; CHECK-NEXT: csel x0, x0, x1, ne
- %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
- %obit = extractvalue {i64, i1} %t, 1
- %ret = select i1 %obit, i64 %v1, i64 %v2
- ret i64 %ret
-}
-
-define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: umulo.select.i32
-; CHECK: umull x8, w0, w1
-; CHECK-NEXT: cmp xzr, x8, lsr #32
-; CHECK-NEXT: csel w0, w0, w1, ne
- %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
- %obit = extractvalue {i32, i1} %t, 1
- %ret = select i1 %obit, i32 %v1, i32 %v2
- ret i32 %ret
-}
-
-define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: umulo.select.i64
-; CHECK: umulh x8, x0, x1
-; CHECK-NEXT: cmp xzr, x8
-; CHECK-NEXT: csel x0, x0, x1, ne
- %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
- %obit = extractvalue {i64, i1} %t, 1
- %ret = select i1 %obit, i64 %v1, i64 %v2
- ret i64 %ret
-}
-
-
-;
-; Check the use of the overflow bit in combination with a branch instruction.
-;
-define i1 @saddo.br.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: saddo.br.i32
-; CHECK: cmn w0, w1
-; CHECK-NEXT: b.vc
- %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @saddo.br.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: saddo.br.i64
-; CHECK: cmn x0, x1
-; CHECK-NEXT: b.vc
- %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: uaddo.br.i32
-; CHECK: cmn w0, w1
-; CHECK-NEXT: b.lo
- %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: uaddo.br.i64
-; CHECK: cmn x0, x1
-; CHECK-NEXT: b.lo
- %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: ssubo.br.i32
-; CHECK: cmp w0, w1
-; CHECK-NEXT: b.vc
- %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: ssubo.br.i64
-; CHECK: cmp x0, x1
-; CHECK-NEXT: b.vc
- %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @usubo.br.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: usubo.br.i32
-; CHECK: cmp w0, w1
-; CHECK-NEXT: b.hs
- %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @usubo.br.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: usubo.br.i64
-; CHECK: cmp x0, x1
-; CHECK-NEXT: b.hs
- %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @smulo.br.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: smulo.br.i32
-; CHECK: smull x8, w0, w1
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: cmp w9, w8, asr #31
-; CHECK-NEXT: b.eq
- %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @smulo.br.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: smulo.br.i64
-; CHECK: mul x8, x0, x1
-; CHECK-NEXT: smulh x9, x0, x1
-; CHECK-NEXT: cmp x9, x8, asr #63
-; CHECK-NEXT: b.eq
- %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @umulo.br.i32(i32 %v1, i32 %v2) {
-entry:
-; CHECK-LABEL: umulo.br.i32
-; CHECK: umull x8, w0, w1
-; CHECK-NEXT: cmp xzr, x8, lsr #32
-; CHECK-NEXT: b.eq
- %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
- %val = extractvalue {i32, i1} %t, 0
- %obit = extractvalue {i32, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-define i1 @umulo.br.i64(i64 %v1, i64 %v2) {
-entry:
-; CHECK-LABEL: umulo.br.i64
-; CHECK: umulh x8, x0, x1
-; CHECK-NEXT: cbz
- %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
- %val = extractvalue {i64, i1} %t, 0
- %obit = extractvalue {i64, i1} %t, 1
- br i1 %obit, label %overflow, label %continue
-
-overflow:
- ret i1 false
-
-continue:
- ret i1 true
-}
-
-declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
-declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
-declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
-declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
-declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
-declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
-declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
-declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
-declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
-declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
-declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
-declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
-
Removed: llvm/trunk/test/CodeGen/ARM64/zero-cycle-regmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zero-cycle-regmov.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zero-cycle-regmov.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/zero-cycle-regmov.ll (removed)
@@ -1,17 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
-; rdar://12254953
-
-define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind ssp {
-entry:
-; CHECK-LABEL: t:
-; CHECK: mov x0, [[REG1:x[0-9]+]]
-; CHECK: mov x1, [[REG2:x[0-9]+]]
-; CHECK: bl _foo
-; CHECK: mov x0, [[REG1]]
-; CHECK: mov x1, [[REG2]]
- %call = call i32 @foo(i32 %c, i32 %d) nounwind
- %call1 = call i32 @foo(i32 %c, i32 %d) nounwind
- unreachable
-}
-
-declare i32 @foo(i32, i32)
Removed: llvm/trunk/test/CodeGen/ARM64/zero-cycle-zeroing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zero-cycle-zeroing.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zero-cycle-zeroing.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/zero-cycle-zeroing.ll (removed)
@@ -1,49 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
-; rdar://11481771
-; rdar://13713797
-
-define void @t1() nounwind ssp {
-entry:
-; CHECK-LABEL: t1:
-; CHECK-NOT: fmov
-; CHECK: movi.2d v0, #0000000000000000
-; CHECK: movi.2d v1, #0000000000000000
-; CHECK: movi.2d v2, #0000000000000000
-; CHECK: movi.2d v3, #0000000000000000
- tail call void @bar(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00) nounwind
- ret void
-}
-
-define void @t2() nounwind ssp {
-entry:
-; CHECK-LABEL: t2:
-; CHECK-NOT: mov w0, wzr
-; CHECK: movz w0, #0
-; CHECK: movz w1, #0
- tail call void @bari(i32 0, i32 0) nounwind
- ret void
-}
-
-define void @t3() nounwind ssp {
-entry:
-; CHECK-LABEL: t3:
-; CHECK-NOT: mov x0, xzr
-; CHECK: movz x0, #0
-; CHECK: movz x1, #0
- tail call void @barl(i64 0, i64 0) nounwind
- ret void
-}
-
-define void @t4() nounwind ssp {
-; CHECK-LABEL: t4:
-; CHECK-NOT: fmov
-; CHECK: movi.2d v0, #0000000000000000
-; CHECK: movi.2d v1, #0000000000000000
- tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
- ret void
-}
-
-declare void @bar(double, double, double, double)
-declare void @bari(i32, i32)
-declare void @barl(i64, i64)
-declare void @barf(float, float)
Removed: llvm/trunk/test/CodeGen/ARM64/zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zext.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/zext.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-define i64 @foo(i32 %a, i32 %b) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: foo:
-; CHECK: add w0, w1, w0
-; CHECK: ret
- %add = add i32 %b, %a
- %conv = zext i32 %add to i64
- ret i64 %conv
-}
Removed: llvm/trunk/test/CodeGen/ARM64/zextload-unscaled.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zextload-unscaled.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zextload-unscaled.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/zextload-unscaled.ll (removed)
@@ -1,40 +0,0 @@
-; RUN: llc -march=arm64 < %s | FileCheck %s
-
- at var32 = global i32 0
-
-define void @test_zextloadi1_unscaled(i1* %base) {
-; CHECK-LABEL: test_zextloadi1_unscaled:
-; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
-
- %addr = getelementptr i1* %base, i32 -7
- %val = load i1* %addr, align 1
-
- %extended = zext i1 %val to i32
- store i32 %extended, i32* @var32, align 4
- ret void
-}
-
-define void @test_zextloadi8_unscaled(i8* %base) {
-; CHECK-LABEL: test_zextloadi8_unscaled:
-; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
-
- %addr = getelementptr i8* %base, i32 -7
- %val = load i8* %addr, align 1
-
- %extended = zext i8 %val to i32
- store i32 %extended, i32* @var32, align 4
- ret void
-}
-
-define void @test_zextloadi16_unscaled(i16* %base) {
-; CHECK-LABEL: test_zextloadi16_unscaled:
-; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-14]
-
- %addr = getelementptr i16* %base, i32 -7
- %val = load i16* %addr, align 2
-
- %extended = zext i16 %val to i32
- store i32 %extended, i32* @var32, align 4
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/zip.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zip.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zip.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/zip.ll (removed)
@@ -1,107 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vzipi8:
-;CHECK: zip1.8b
-;CHECK: zip2.8b
-;CHECK-NEXT: add.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
- %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vzipi16:
-;CHECK: zip1.4h
-;CHECK: zip2.4h
-;CHECK-NEXT: add.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
- %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vzipQi8:
-;CHECK: zip1.16b
-;CHECK: zip2.16b
-;CHECK-NEXT: add.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
- %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vzipQi16:
-;CHECK: zip1.8h
-;CHECK: zip2.8h
-;CHECK-NEXT: add.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
- %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vzipQi32:
-;CHECK: zip1.4s
-;CHECK: zip2.4s
-;CHECK-NEXT: add.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
- %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vzipQf:
-;CHECK: zip1.4s
-;CHECK: zip2.4s
-;CHECK-NEXT: fadd.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
- %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
- %tmp5 = fadd <4 x float> %tmp3, %tmp4
- ret <4 x float> %tmp5
-}
-
-; Undef shuffle indices should not prevent matching to VZIP:
-
-define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vzipi8_undef:
-;CHECK: zip1.8b
-;CHECK: zip2.8b
-;CHECK-NEXT: add.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11>
- %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vzipQi8_undef:
-;CHECK: zip1.16b
-;CHECK: zip2.16b
-;CHECK-NEXT: add.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
- %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
Copied: llvm/trunk/test/DebugInfo/AArch64/struct_by_value.ll (from r209576, llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/AArch64/struct_by_value.ll?p2=llvm/trunk/test/DebugInfo/AArch64/struct_by_value.ll&p1=llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg (removed)
@@ -1,4 +0,0 @@
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
-
Removed: llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll (original)
+++ llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll (removed)
@@ -1,68 +0,0 @@
-; A by-value struct is a register-indirect value (breg).
-; RUN: llc %s -filetype=asm -o - | FileCheck %s
-
-; CHECK: DW_OP_breg0
-
-; rdar://problem/13658587
-;
-; Generated from
-;
-; struct five
-; {
-; int a;
-; int b;
-; int c;
-; int d;
-; int e;
-; };
-;
-; int
-; return_five_int (struct five f)
-; {
-; return f.a;
-; }
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
-target triple = "arm64-apple-ios3.0.0"
-
-%struct.five = type { i32, i32, i32, i32, i32 }
-
-; Function Attrs: nounwind ssp
-define i32 @return_five_int(%struct.five* %f) #0 {
-entry:
- call void @llvm.dbg.declare(metadata !{%struct.five* %f}, metadata !17), !dbg !18
- %a = getelementptr inbounds %struct.five* %f, i32 0, i32 0, !dbg !19
- %0 = load i32* %a, align 4, !dbg !19
- ret i32 %0, !dbg !19
-}
-
-; Function Attrs: nounwind readnone
-declare void @llvm.dbg.declare(metadata, metadata) #1
-
-attributes #0 = { nounwind ssp }
-attributes #1 = { nounwind readnone }
-
-!llvm.dbg.cu = !{!0}
-!llvm.module.flags = !{!16, !20}
-
-!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"LLVM version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [struct_by_value.c] [DW_LANG_C99]
-!1 = metadata !{metadata !"struct_by_value.c", metadata !""}
-!2 = metadata !{}
-!3 = metadata !{metadata !4}
-!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"return_five_int", metadata !"return_five_int", metadata !"", i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (%struct.five*)* @return_five_int, null, null, metadata !2, i32 14} ; [ DW_TAG_subprogram ] [line 13] [def] [scope 14] [return_five_int]
-!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [struct_by_value.c]
-!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!7 = metadata !{metadata !8, metadata !9}
-!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!9 = metadata !{i32 786451, metadata !1, null, metadata !"five", i32 1, i64 160, i64 32, i32 0, i32 0, null, metadata !10, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [five] [line 1, size 160, align 32, offset 0] [def] [from ]
-!10 = metadata !{metadata !11, metadata !12, metadata !13, metadata !14, metadata !15}
-!11 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"a", i32 3, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_member ] [a] [line 3, size 32, align 32, offset 0] [from int]
-!12 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"b", i32 4, i64 32, i64 32, i64 32, i32 0, metadata !8} ; [ DW_TAG_member ] [b] [line 4, size 32, align 32, offset 32] [from int]
-!13 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"c", i32 5, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] [c] [line 5, size 32, align 32, offset 64] [from int]
-!14 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"d", i32 6, i64 32, i64 32, i64 96, i32 0, metadata !8} ; [ DW_TAG_member ] [d] [line 6, size 32, align 32, offset 96] [from int]
-!15 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"e", i32 7, i64 32, i64 32, i64 128, i32 0, metadata !8} ; [ DW_TAG_member ] [e] [line 7, size 32, align 32, offset 128] [from int]
-!16 = metadata !{i32 2, metadata !"Dwarf Version", i32 2}
-!17 = metadata !{i32 786689, metadata !4, metadata !"f", metadata !5, i32 16777229, metadata !9, i32 8192, i32 0} ; [ DW_TAG_arg_variable ] [f] [line 13]
-!18 = metadata !{i32 13, i32 0, metadata !4, null}
-!19 = metadata !{i32 16, i32 0, metadata !4, null}
-!20 = metadata !{i32 1, metadata !"Debug Info Version", i32 1}
Modified: llvm/trunk/test/MC/AArch64/adrp-relocation.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/adrp-relocation.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/adrp-relocation.s (original)
+++ llvm/trunk/test/MC/AArch64/adrp-relocation.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj -o - %s| llvm-readobj -r - | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s| llvm-readobj -r - | FileCheck %s
.text
// These should produce an ADRP/ADD pair to calculate the address of
// testfn. The important point is that LLVM shouldn't think it can deal with the
Copied: llvm/trunk/test/MC/AArch64/arm64-adr.s (from r209576, llvm/trunk/test/MC/ARM64/adr.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-adr.s?p2=llvm/trunk/test/MC/AArch64/arm64-adr.s&p1=llvm/trunk/test/MC/ARM64/adr.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/adr.s (original)
+++ llvm/trunk/test/MC/AArch64/arm64-adr.s Sat May 24 07:50:23 2014
@@ -8,9 +8,9 @@ adr x0, foo
// CHECK: adr x0, #0 // encoding: [0x00,0x00,0x00,0x10]
// CHECK: adr x0, #1 // encoding: [0x00,0x00,0x00,0x30]
// CHECK: adr x0, .Ltmp0 // encoding: [A,A,A,0x10'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm64_pcrel_adr_imm21
+// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_aarch64_pcrel_adr_imm21
// CHECK: adr x0, foo // encoding: [A,A,A,0x10'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_arm64_pcrel_adr_imm21
+// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_aarch64_pcrel_adr_imm21
adrp x0, #0
adrp x0, #4096
@@ -19,9 +19,9 @@ adrp x0, foo
// CHECK: adrp x0, #0 // encoding: [0x00,0x00,0x00,0x90]
// CHECK: adrp x0, #4096 // encoding: [0x00,0x00,0x00,0xb0]
// CHECK: adrp x0, .Ltmp0 // encoding: [A,A,A,0x90'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_aarch64_pcrel_adrp_imm21
// CHECK: adrp x0, foo // encoding: [A,A,A,0x90'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_aarch64_pcrel_adrp_imm21
adr x0, #0xffffffff
adrp x0, #0xffffffff
Copied: llvm/trunk/test/MC/AArch64/arm64-advsimd.s (from r209576, llvm/trunk/test/MC/ARM64/advsimd.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-advsimd.s?p2=llvm/trunk/test/MC/AArch64/arm64-advsimd.s&p1=llvm/trunk/test/MC/ARM64/advsimd.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-aliases.s (from r209576, llvm/trunk/test/MC/ARM64/aliases.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-aliases.s?p2=llvm/trunk/test/MC/AArch64/arm64-aliases.s&p1=llvm/trunk/test/MC/ARM64/aliases.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-arithmetic-encoding.s (from r209576, llvm/trunk/test/MC/ARM64/arithmetic-encoding.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-arithmetic-encoding.s?p2=llvm/trunk/test/MC/AArch64/arm64-arithmetic-encoding.s&p1=llvm/trunk/test/MC/ARM64/arithmetic-encoding.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-arm64-fixup.s (from r209576, llvm/trunk/test/MC/ARM64/arm64-fixup.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-arm64-fixup.s?p2=llvm/trunk/test/MC/AArch64/arm64-arm64-fixup.s&p1=llvm/trunk/test/MC/ARM64/arm64-fixup.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/arm64-fixup.s (original)
+++ llvm/trunk/test/MC/AArch64/arm64-arm64-fixup.s Sat May 24 07:50:23 2014
@@ -3,8 +3,8 @@
foo:
adr x3, Lbar
; CHECK: adr x3, Lbar ; encoding: [0x03'A',A,A,0x10'A']
-; CHECK: fixup A - offset: 0, value: Lbar, kind: fixup_arm64_pcrel_adr_imm21
+; CHECK: fixup A - offset: 0, value: Lbar, kind: fixup_aarch64_pcrel_adr_imm21
Lbar:
adrp x3, _printf at page
; CHECK: adrp x3, _printf at PAGE ; encoding: [0x03'A',A,A,0x90'A']
-; CHECK: fixup A - offset: 0, value: _printf at PAGE, kind: fixup_arm64_pcrel_adrp_imm21
+; CHECK: fixup A - offset: 0, value: _printf at PAGE, kind: fixup_aarch64_pcrel_adrp_imm21
Copied: llvm/trunk/test/MC/AArch64/arm64-basic-a64-instructions.s (from r209576, llvm/trunk/test/MC/ARM64/basic-a64-instructions.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-basic-a64-instructions.s?p2=llvm/trunk/test/MC/AArch64/arm64-basic-a64-instructions.s&p1=llvm/trunk/test/MC/ARM64/basic-a64-instructions.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-be-datalayout.s (from r209576, llvm/trunk/test/MC/ARM64/be-datalayout.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-be-datalayout.s?p2=llvm/trunk/test/MC/AArch64/arm64-be-datalayout.s&p1=llvm/trunk/test/MC/ARM64/be-datalayout.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-bitfield-encoding.s (from r209576, llvm/trunk/test/MC/ARM64/bitfield-encoding.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-bitfield-encoding.s?p2=llvm/trunk/test/MC/AArch64/arm64-bitfield-encoding.s&p1=llvm/trunk/test/MC/ARM64/bitfield-encoding.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-branch-encoding.s (from r209576, llvm/trunk/test/MC/ARM64/branch-encoding.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-branch-encoding.s?p2=llvm/trunk/test/MC/AArch64/arm64-branch-encoding.s&p1=llvm/trunk/test/MC/ARM64/branch-encoding.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/branch-encoding.s (original)
+++ llvm/trunk/test/MC/AArch64/arm64-branch-encoding.s Sat May 24 07:50:23 2014
@@ -20,7 +20,7 @@ foo:
; CHECK: encoding: [0x20,0x01,0x3f,0xd6]
bl L1
; CHECK: bl L1 ; encoding: [A,A,A,0b100101AA]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_call26
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_call26
;-----------------------------------------------------------------------------
; Contitional branch instructions.
@@ -28,52 +28,52 @@ foo:
b L1
; CHECK: b L1 ; encoding: [A,A,A,0b000101AA]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch26
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch26
b.eq L1
; CHECK: b.eq L1 ; encoding: [0bAAA00000,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.ne L1
; CHECK: b.ne L1 ; encoding: [0bAAA00001,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.cs L1
; CHECK: b.hs L1 ; encoding: [0bAAA00010,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.cc L1
; CHECK: b.lo L1 ; encoding: [0bAAA00011,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.mi L1
; CHECK: b.mi L1 ; encoding: [0bAAA00100,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.pl L1
; CHECK: b.pl L1 ; encoding: [0bAAA00101,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.vs L1
; CHECK: b.vs L1 ; encoding: [0bAAA00110,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.vc L1
; CHECK: b.vc L1 ; encoding: [0bAAA00111,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.hi L1
; CHECK: b.hi L1 ; encoding: [0bAAA01000,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.ls L1
; CHECK: b.ls L1 ; encoding: [0bAAA01001,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.ge L1
; CHECK: b.ge L1 ; encoding: [0bAAA01010,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.lt L1
; CHECK: b.lt L1 ; encoding: [0bAAA01011,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.gt L1
; CHECK: b.gt L1 ; encoding: [0bAAA01100,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.le L1
; CHECK: b.le L1 ; encoding: [0bAAA01101,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
b.al L1
; CHECK: b.al L1 ; encoding: [0bAAA01110,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19
L1:
b #28
; CHECK: b #28
Copied: llvm/trunk/test/MC/AArch64/arm64-condbr-without-dots.s (from r209576, llvm/trunk/test/MC/ARM64/condbr-without-dots.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-condbr-without-dots.s?p2=llvm/trunk/test/MC/AArch64/arm64-condbr-without-dots.s&p1=llvm/trunk/test/MC/ARM64/condbr-without-dots.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-crypto.s (from r209576, llvm/trunk/test/MC/ARM64/crypto.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-crypto.s?p2=llvm/trunk/test/MC/AArch64/arm64-crypto.s&p1=llvm/trunk/test/MC/ARM64/crypto.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-diagno-predicate.s (from r209576, llvm/trunk/test/MC/ARM64/diagno-predicate.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-diagno-predicate.s?p2=llvm/trunk/test/MC/AArch64/arm64-diagno-predicate.s&p1=llvm/trunk/test/MC/ARM64/diagno-predicate.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-diags.s (from r209576, llvm/trunk/test/MC/ARM64/diags.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-diags.s?p2=llvm/trunk/test/MC/AArch64/arm64-diags.s&p1=llvm/trunk/test/MC/ARM64/diags.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/diags.s (original)
+++ llvm/trunk/test/MC/AArch64/arm64-diags.s Sat May 24 07:50:23 2014
@@ -8,7 +8,7 @@ foo:
ldr x3, (foo + 4)
ldr x3, [foo + 4]
; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58]
-; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_arm64_ldr_pcrel_imm19
+; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm19
; CHECK-ERRORS: error: invalid operand for instruction
; The last argument should be flagged as an error. rdar://9576009
Copied: llvm/trunk/test/MC/AArch64/arm64-directive_loh.s (from r209576, llvm/trunk/test/MC/ARM64/directive_loh.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-directive_loh.s?p2=llvm/trunk/test/MC/AArch64/arm64-directive_loh.s&p1=llvm/trunk/test/MC/ARM64/directive_loh.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s (from r209576, llvm/trunk/test/MC/ARM64/elf-reloc-condbr.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s?p2=llvm/trunk/test/MC/AArch64/arm64-elf-reloc-condbr.s&p1=llvm/trunk/test/MC/ARM64/elf-reloc-condbr.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s (from r209576, llvm/trunk/test/MC/ARM64/elf-relocs.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s?p2=llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s&p1=llvm/trunk/test/MC/ARM64/elf-relocs.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-fp-encoding.s (from r209576, llvm/trunk/test/MC/ARM64/fp-encoding.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-fp-encoding.s?p2=llvm/trunk/test/MC/AArch64/arm64-fp-encoding.s&p1=llvm/trunk/test/MC/ARM64/fp-encoding.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-large-relocs.s (from r209576, llvm/trunk/test/MC/ARM64/large-relocs.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-large-relocs.s?p2=llvm/trunk/test/MC/AArch64/arm64-large-relocs.s&p1=llvm/trunk/test/MC/ARM64/large-relocs.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/large-relocs.s (original)
+++ llvm/trunk/test/MC/AArch64/arm64-large-relocs.s Sat May 24 07:50:23 2014
@@ -4,9 +4,9 @@
movz x2, #:abs_g0:sym
movk w3, #:abs_g0_nc:sym
// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_aarch64_movw
// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_aarch64_movw
// CHECK-OBJ: 0 R_AARCH64_MOVW_UABS_G0 sym
// CHECK-OBJ: 4 R_AARCH64_MOVW_UABS_G0_NC sym
@@ -14,9 +14,9 @@
movz x4, #:abs_g1:sym
movk w5, #:abs_g1_nc:sym
// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_aarch64_movw
// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_aarch64_movw
// CHECK-OBJ: 8 R_AARCH64_MOVW_UABS_G1 sym
// CHECK-OBJ: c R_AARCH64_MOVW_UABS_G1_NC sym
@@ -24,15 +24,15 @@
movz x6, #:abs_g2:sym
movk x7, #:abs_g2_nc:sym
// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_aarch64_movw
// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_aarch64_movw
// CHECK-OBJ: 10 R_AARCH64_MOVW_UABS_G2 sym
// CHECK-OBJ: 14 R_AARCH64_MOVW_UABS_G2_NC sym
movz x8, #:abs_g3:sym
// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_aarch64_movw
// CHECK-OBJ: 18 R_AARCH64_MOVW_UABS_G3 sym
Copied: llvm/trunk/test/MC/AArch64/arm64-leaf-compact-unwind.s (from r209576, llvm/trunk/test/MC/ARM64/leaf-compact-unwind.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-leaf-compact-unwind.s?p2=llvm/trunk/test/MC/AArch64/arm64-leaf-compact-unwind.s&p1=llvm/trunk/test/MC/ARM64/leaf-compact-unwind.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-logical-encoding.s (from r209576, llvm/trunk/test/MC/ARM64/logical-encoding.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-logical-encoding.s?p2=llvm/trunk/test/MC/AArch64/arm64-logical-encoding.s&p1=llvm/trunk/test/MC/ARM64/logical-encoding.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-mapping-across-sections.s (from r209576, llvm/trunk/test/MC/ARM64/mapping-across-sections.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-mapping-across-sections.s?p2=llvm/trunk/test/MC/AArch64/arm64-mapping-across-sections.s&p1=llvm/trunk/test/MC/ARM64/mapping-across-sections.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-mapping-within-section.s (from r209576, llvm/trunk/test/MC/ARM64/mapping-within-section.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-mapping-within-section.s?p2=llvm/trunk/test/MC/AArch64/arm64-mapping-within-section.s&p1=llvm/trunk/test/MC/ARM64/mapping-within-section.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-memory.s (from r209576, llvm/trunk/test/MC/ARM64/memory.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-memory.s?p2=llvm/trunk/test/MC/AArch64/arm64-memory.s&p1=llvm/trunk/test/MC/ARM64/memory.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-nv-cond.s (from r209576, llvm/trunk/test/MC/ARM64/nv-cond.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-nv-cond.s?p2=llvm/trunk/test/MC/AArch64/arm64-nv-cond.s&p1=llvm/trunk/test/MC/ARM64/nv-cond.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-optional-hash.s (from r209576, llvm/trunk/test/MC/ARM64/optional-hash.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-optional-hash.s?p2=llvm/trunk/test/MC/AArch64/arm64-optional-hash.s&p1=llvm/trunk/test/MC/ARM64/optional-hash.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-separator.s (from r209576, llvm/trunk/test/MC/ARM64/separator.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-separator.s?p2=llvm/trunk/test/MC/AArch64/arm64-separator.s&p1=llvm/trunk/test/MC/ARM64/separator.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-simd-ldst.s (from r209576, llvm/trunk/test/MC/ARM64/simd-ldst.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-simd-ldst.s?p2=llvm/trunk/test/MC/AArch64/arm64-simd-ldst.s&p1=llvm/trunk/test/MC/ARM64/simd-ldst.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-small-data-fixups.s (from r209576, llvm/trunk/test/MC/ARM64/small-data-fixups.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-small-data-fixups.s?p2=llvm/trunk/test/MC/AArch64/arm64-small-data-fixups.s&p1=llvm/trunk/test/MC/ARM64/small-data-fixups.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-spsel-sysreg.s (from r209576, llvm/trunk/test/MC/ARM64/spsel-sysreg.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-spsel-sysreg.s?p2=llvm/trunk/test/MC/AArch64/arm64-spsel-sysreg.s&p1=llvm/trunk/test/MC/ARM64/spsel-sysreg.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-system-encoding.s (from r209576, llvm/trunk/test/MC/ARM64/system-encoding.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-system-encoding.s?p2=llvm/trunk/test/MC/AArch64/arm64-system-encoding.s&p1=llvm/trunk/test/MC/ARM64/system-encoding.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-target-specific-sysreg.s (from r209576, llvm/trunk/test/MC/ARM64/target-specific-sysreg.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-target-specific-sysreg.s?p2=llvm/trunk/test/MC/AArch64/arm64-target-specific-sysreg.s&p1=llvm/trunk/test/MC/ARM64/target-specific-sysreg.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-tls-modifiers-darwin.s (from r209576, llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-tls-modifiers-darwin.s?p2=llvm/trunk/test/MC/AArch64/arm64-tls-modifiers-darwin.s&p1=llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-tls-relocs.s (from r209576, llvm/trunk/test/MC/ARM64/tls-relocs.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-tls-relocs.s?p2=llvm/trunk/test/MC/AArch64/arm64-tls-relocs.s&p1=llvm/trunk/test/MC/ARM64/tls-relocs.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/tls-relocs.s (original)
+++ llvm/trunk/test/MC/AArch64/arm64-tls-relocs.s Sat May 24 07:50:23 2014
@@ -9,14 +9,14 @@
movz x15, #:gottprel_g1:var
// CHECK: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_aarch64_movw
// CHECK-ELF: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM:[^ ]+]]
movk x13, #:gottprel_g0_nc:var
// CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]]
@@ -25,11 +25,11 @@
ldr x10, [x0, #:gottprel_lo12:var]
ldr x9, :gottprel:var
// CHECK: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_pcrel_adrp_imm21
// CHECK: ldr x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
// CHECK: ldr x9, :gottprel:var // encoding: [0bAAA01001,A,A,0x58]
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_ldr_pcrel_imm19
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]]
@@ -43,9 +43,9 @@
movz x3, #:tprel_g2:var
movn x4, #:tprel_g2:var
// CHECK: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw
// CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
@@ -55,11 +55,11 @@
movn x6, #:tprel_g1:var
movz w7, #:tprel_g1:var
// CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
// CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
// CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
@@ -69,9 +69,9 @@
movk x9, #:tprel_g1_nc:var
movk w10, #:tprel_g1_nc:var
// CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw
// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
@@ -81,11 +81,11 @@
movn x12, #:tprel_g0:var
movz w13, #:tprel_g0:var
// CHECK: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
// CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
// CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
@@ -95,9 +95,9 @@
movk x15, #:tprel_g0_nc:var
movk w16, #:tprel_g0_nc:var
// CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw
// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
@@ -105,14 +105,14 @@
add x21, x22, #:tprel_lo12:var
// CHECK: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_add_imm12
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]]
add x25, x26, #:tprel_lo12_nc:var
// CHECK: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_add_imm12
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]]
@@ -120,9 +120,9 @@
ldrb w29, [x30, #:tprel_lo12:var]
ldrsb x29, [x28, #:tprel_lo12_nc:var]
// CHECK: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1
// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]]
@@ -131,9 +131,9 @@
strh w27, [x26, #:tprel_lo12:var]
ldrsh x25, [x24, #:tprel_lo12_nc:var]
// CHECK: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2
// CHECK: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]]
@@ -142,9 +142,9 @@
ldr w23, [x22, #:tprel_lo12:var]
ldrsw x21, [x20, #:tprel_lo12_nc:var]
// CHECK: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4
// CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]]
@@ -152,9 +152,9 @@
ldr x19, [x18, #:tprel_lo12:var]
str x17, [x16, #:tprel_lo12_nc:var]
// CHECK: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
// CHECK: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]]
@@ -167,9 +167,9 @@
movz x3, #:dtprel_g2:var
movn x4, #:dtprel_g2:var
// CHECK: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw
// CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]
@@ -179,11 +179,11 @@
movn x6, #:dtprel_g1:var
movz w7, #:dtprel_g1:var
// CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
// CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
// CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
@@ -193,9 +193,9 @@
movk x9, #:dtprel_g1_nc:var
movk w10, #:dtprel_g1_nc:var
// CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw
// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
@@ -205,11 +205,11 @@
movn x12, #:dtprel_g0:var
movz w13, #:dtprel_g0:var
// CHECK: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
// CHECK: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
// CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
@@ -219,9 +219,9 @@
movk x15, #:dtprel_g0_nc:var
movk w16, #:dtprel_g0_nc:var
// CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw
// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
@@ -229,14 +229,14 @@
add x21, x22, #:dtprel_lo12:var
// CHECK: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_add_imm12
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]]
add x25, x26, #:dtprel_lo12_nc:var
// CHECK: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_add_imm12
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]]
@@ -244,9 +244,9 @@
ldrb w29, [x30, #:dtprel_lo12:var]
ldrsb x29, [x28, #:dtprel_lo12_nc:var]
// CHECK: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1
// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]]
@@ -255,9 +255,9 @@
strh w27, [x26, #:dtprel_lo12:var]
ldrsh x25, [x24, #:dtprel_lo12_nc:var]
// CHECK: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2
// CHECK: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]]
@@ -266,9 +266,9 @@
ldr w23, [x22, #:dtprel_lo12:var]
ldrsw x21, [x20, #:dtprel_lo12_nc:var]
// CHECK: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4
// CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]]
@@ -276,9 +276,9 @@
ldr x19, [x18, #:dtprel_lo12:var]
str x17, [x16, #:dtprel_lo12_nc:var]
// CHECK: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
// CHECK: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]]
@@ -294,13 +294,13 @@
blr x3
// CHECK: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_aarch64_pcrel_adrp_imm21
// CHECK: ldr x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
// CHECK: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_add_imm12
+// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12
// CHECK: .tlsdesccall var // encoding: []
-// CHECK-NEXT: // fixup A - offset: 0, value: var, kind: fixup_arm64_tlsdesc_call
+// CHECK-NEXT: // fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call
// CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6]
Copied: llvm/trunk/test/MC/AArch64/arm64-v128_lo-diagnostics.s (from r209576, llvm/trunk/test/MC/ARM64/v128_lo-diagnostics.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-v128_lo-diagnostics.s?p2=llvm/trunk/test/MC/AArch64/arm64-v128_lo-diagnostics.s&p1=llvm/trunk/test/MC/ARM64/v128_lo-diagnostics.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-variable-exprs.s (from r209576, llvm/trunk/test/MC/ARM64/variable-exprs.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-variable-exprs.s?p2=llvm/trunk/test/MC/AArch64/arm64-variable-exprs.s&p1=llvm/trunk/test/MC/ARM64/variable-exprs.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-vector-lists.s (from r209576, llvm/trunk/test/MC/ARM64/vector-lists.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-vector-lists.s?p2=llvm/trunk/test/MC/AArch64/arm64-vector-lists.s&p1=llvm/trunk/test/MC/ARM64/vector-lists.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/AArch64/arm64-verbose-vector-case.s (from r209576, llvm/trunk/test/MC/ARM64/verbose-vector-case.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-verbose-vector-case.s?p2=llvm/trunk/test/MC/AArch64/arm64-verbose-vector-case.s&p1=llvm/trunk/test/MC/ARM64/verbose-vector-case.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Modified: llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple arm64-none-linux-gnu < %s 2> %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-ERROR-ARM64 < %t %s
//------------------------------------------------------------------------------
Modified: llvm/trunk/test/MC/AArch64/basic-a64-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/basic-a64-instructions.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/basic-a64-instructions.s (original)
+++ llvm/trunk/test/MC/AArch64/basic-a64-instructions.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s
.globl _func
// Check that the assembler can handle the documented syntax from the ARM ARM.
@@ -127,7 +127,7 @@ _func:
// CHECK: adds w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x2b]
// CHECK: adds w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x2b]
// CHECK: adds w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x2b]
-// CHECK-ARM64: cmn w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b]
+// CHECK: cmn w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b]
// CHECK: adds w2, w3, w5, sxtx // encoding: [0x62,0xe0,0x25,0x2b]
// subs
@@ -255,7 +255,7 @@ _func:
// CHECK: sub sp, x3, x7, lsl #4 // encoding: [0x7f,0x70,0x27,0xcb]
// CHECK: add w2, wsp, w3, lsl #1 // encoding: [0xe2,0x47,0x23,0x0b]
// CHECK: cmp wsp, w9 // encoding: [0xff,0x43,0x29,0x6b]
-// CHECK-ARM64: cmn wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b]
+// CHECK: cmn wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b]
// CHECK: subs x3, sp, x9, lsl #2 // encoding: [0xe3,0x6b,0x29,0xeb]
//------------------------------------------------------------------------------
@@ -349,8 +349,8 @@ _func:
// A relocation check (default to lo12, which is the only sane relocation anyway really)
add x0, x4, #:lo12:var
-// CHECK-ARM64: add x0, x4, :lo12:var // encoding: [0x80,0bAAAAAA00,0b00AAAAAA,0x91]
-// CHECK-ARM64: // fixup A - offset: 0, value: :lo12:var, kind: fixup_arm64_add_imm12
+// CHECK: add x0, x4, :lo12:var // encoding: [0x80,0bAAAAAA00,0b00AAAAAA,0x91]
+// CHECK: // fixup A - offset: 0, value: :lo12:var, kind: fixup_aarch64_add_imm12
//------------------------------------------------------------------------------
// Add-sub (shifted register)
@@ -484,7 +484,7 @@ _func:
sub w4, w6, wzr
// CHECK: sub w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x4b]
// CHECK: sub wzr, w3, w5 // encoding: [0x7f,0x00,0x05,0x4b]
-// CHECK-ARM64: neg w20, w4 // encoding: [0xf4,0x03,0x04,0x4b]
+// CHECK: neg w20, w4 // encoding: [0xf4,0x03,0x04,0x4b]
// CHECK: sub w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x4b]
sub w11, w13, w15, lsl #0
@@ -514,7 +514,7 @@ _func:
sub x4, x6, xzr
// CHECK: sub x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xcb]
// CHECK: sub xzr, x3, x5 // encoding: [0x7f,0x00,0x05,0xcb]
-// CHECK-ARM64: neg x20, x4 // encoding: [0xf4,0x03,0x04,0xcb]
+// CHECK: neg x20, x4 // encoding: [0xf4,0x03,0x04,0xcb]
// CHECK: sub x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xcb]
sub x11, x13, x15, lsl #0
@@ -544,7 +544,7 @@ _func:
subs w4, w6, wzr
// CHECK: subs w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x6b]
// CHECK: {{subs wzr,|cmp}} w3, w5 // encoding: [0x7f,0x00,0x05,0x6b]
-// CHECK-ARM64: negs w20, w4 // encoding: [0xf4,0x03,0x04,0x6b]
+// CHECK: negs w20, w4 // encoding: [0xf4,0x03,0x04,0x6b]
// CHECK: subs w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x6b]
subs w11, w13, w15, lsl #0
@@ -574,7 +574,7 @@ _func:
subs x4, x6, xzr
// CHECK: subs x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xeb]
// CHECK: {{subs xzr,|cmp}} x3, x5 // encoding: [0x7f,0x00,0x05,0xeb]
-// CHECK-ARM64: negs x20, x4 // encoding: [0xf4,0x03,0x04,0xeb]
+// CHECK: negs x20, x4 // encoding: [0xf4,0x03,0x04,0xeb]
// CHECK: subs x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xeb]
subs x11, x13, x15, lsl #0
@@ -713,17 +713,17 @@ _func:
neg w29, w30
neg w30, wzr
neg wzr, w0
-// CHECK-ARM64: neg w29, w30 // encoding: [0xfd,0x03,0x1e,0x4b]
-// CHECK-ARM64: neg w30, wzr // encoding: [0xfe,0x03,0x1f,0x4b]
-// CHECK-ARM64: neg wzr, w0 // encoding: [0xff,0x03,0x00,0x4b]
+// CHECK: neg w29, w30 // encoding: [0xfd,0x03,0x1e,0x4b]
+// CHECK: neg w30, wzr // encoding: [0xfe,0x03,0x1f,0x4b]
+// CHECK: neg wzr, w0 // encoding: [0xff,0x03,0x00,0x4b]
neg w28, w27, lsl #0
neg w26, w25, lsl #29
neg w24, w23, lsl #31
-// CHECK-ARM64: neg w28, w27 // encoding: [0xfc,0x03,0x1b,0x4b]
-// CHECK-ARM64: neg w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
-// CHECK-ARM64: neg w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
+// CHECK: neg w28, w27 // encoding: [0xfc,0x03,0x1b,0x4b]
+// CHECK: neg w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
+// CHECK: neg w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
neg w22, w21, lsr #0
neg w20, w19, lsr #1
@@ -742,17 +742,17 @@ _func:
neg x29, x30
neg x30, xzr
neg xzr, x0
-// CHECK-ARM64: neg x29, x30 // encoding: [0xfd,0x03,0x1e,0xcb]
-// CHECK-ARM64: neg x30, xzr // encoding: [0xfe,0x03,0x1f,0xcb]
-// CHECK-ARM64: neg xzr, x0 // encoding: [0xff,0x03,0x00,0xcb]
+// CHECK: neg x29, x30 // encoding: [0xfd,0x03,0x1e,0xcb]
+// CHECK: neg x30, xzr // encoding: [0xfe,0x03,0x1f,0xcb]
+// CHECK: neg xzr, x0 // encoding: [0xff,0x03,0x00,0xcb]
neg x28, x27, lsl #0
neg x26, x25, lsl #29
neg x24, x23, lsl #31
-// CHECK-ARM64: neg x28, x27 // encoding: [0xfc,0x03,0x1b,0xcb]
-// CHECK-ARM64: neg x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
-// CHECK-ARM64: neg x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
+// CHECK: neg x28, x27 // encoding: [0xfc,0x03,0x1b,0xcb]
+// CHECK: neg x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
+// CHECK: neg x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
neg x22, x21, lsr #0
neg x20, x19, lsr #1
@@ -771,17 +771,17 @@ _func:
negs w29, w30
negs w30, wzr
negs wzr, w0
-// CHECK-ARM64: negs w29, w30 // encoding: [0xfd,0x03,0x1e,0x6b]
-// CHECK-ARM64: negs w30, wzr // encoding: [0xfe,0x03,0x1f,0x6b]
-// CHECK-ARM64: cmp wzr, w0 // encoding: [0xff,0x03,0x00,0x6b]
+// CHECK: negs w29, w30 // encoding: [0xfd,0x03,0x1e,0x6b]
+// CHECK: negs w30, wzr // encoding: [0xfe,0x03,0x1f,0x6b]
+// CHECK: cmp wzr, w0 // encoding: [0xff,0x03,0x00,0x6b]
negs w28, w27, lsl #0
negs w26, w25, lsl #29
negs w24, w23, lsl #31
-// CHECK-ARM64: negs w28, w27 // encoding: [0xfc,0x03,0x1b,0x6b]
-// CHECK-ARM64: negs w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
-// CHECK-ARM64: negs w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
+// CHECK: negs w28, w27 // encoding: [0xfc,0x03,0x1b,0x6b]
+// CHECK: negs w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
+// CHECK: negs w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
negs w22, w21, lsr #0
negs w20, w19, lsr #1
@@ -800,17 +800,17 @@ _func:
negs x29, x30
negs x30, xzr
negs xzr, x0
-// CHECK-ARM64: negs x29, x30 // encoding: [0xfd,0x03,0x1e,0xeb]
-// CHECK-ARM64: negs x30, xzr // encoding: [0xfe,0x03,0x1f,0xeb]
-// CHECK-ARM64: cmp xzr, x0 // encoding: [0xff,0x03,0x00,0xeb]
+// CHECK: negs x29, x30 // encoding: [0xfd,0x03,0x1e,0xeb]
+// CHECK: negs x30, xzr // encoding: [0xfe,0x03,0x1f,0xeb]
+// CHECK: cmp xzr, x0 // encoding: [0xff,0x03,0x00,0xeb]
negs x28, x27, lsl #0
negs x26, x25, lsl #29
negs x24, x23, lsl #31
-// CHECK-ARM64: negs x28, x27 // encoding: [0xfc,0x03,0x1b,0xeb]
-// CHECK-ARM64: negs x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
-// CHECK-ARM64: negs x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
+// CHECK: negs x28, x27 // encoding: [0xfc,0x03,0x1b,0xeb]
+// CHECK: negs x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
+// CHECK: negs x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
negs x22, x21, lsr #0
negs x20, x19, lsr #1
@@ -938,28 +938,28 @@ _func:
sbfm wzr, wzr, #31, #31
sbfm w12, w9, #0, #0
-// CHECK-ARM64: sbfx x1, x2, #3, #2 // encoding: [0x41,0x10,0x43,0x93]
-// CHECK-ARM64: asr x3, x4, #63 // encoding: [0x83,0xfc,0x7f,0x93]
-// CHECK-ARM64: asr wzr, wzr, #31 // encoding: [0xff,0x7f,0x1f,0x13]
-// CHECK-ARM64: sbfx w12, w9, #0, #1 // encoding: [0x2c,0x01,0x00,0x13]
+// CHECK: sbfx x1, x2, #3, #2 // encoding: [0x41,0x10,0x43,0x93]
+// CHECK: asr x3, x4, #63 // encoding: [0x83,0xfc,0x7f,0x93]
+// CHECK: asr wzr, wzr, #31 // encoding: [0xff,0x7f,0x1f,0x13]
+// CHECK: sbfx w12, w9, #0, #1 // encoding: [0x2c,0x01,0x00,0x13]
ubfm x4, x5, #12, #10
ubfm xzr, x4, #0, #0
ubfm x4, xzr, #63, #5
ubfm x5, x6, #12, #63
-// CHECK-ARM64: ubfiz x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xd3]
-// CHECK-ARM64: ubfx xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xd3]
-// CHECK-ARM64: ubfiz x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xd3]
-// CHECK-ARM64: lsr x5, x6, #12 // encoding: [0xc5,0xfc,0x4c,0xd3]
+// CHECK: ubfiz x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xd3]
+// CHECK: ubfx xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xd3]
+// CHECK: ubfiz x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xd3]
+// CHECK: lsr x5, x6, #12 // encoding: [0xc5,0xfc,0x4c,0xd3]
bfm x4, x5, #12, #10
bfm xzr, x4, #0, #0
bfm x4, xzr, #63, #5
bfm x5, x6, #12, #63
-// CHECK-ARM64: bfi x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xb3]
-// CHECK-ARM64: bfxil xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xb3]
-// CHECK-ARM64: bfi x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xb3]
-// CHECK-ARM64: bfxil x5, x6, #12, #52 // encoding: [0xc5,0xfc,0x4c,0xb3]
+// CHECK: bfi x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xb3]
+// CHECK: bfxil xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xb3]
+// CHECK: bfi x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xb3]
+// CHECK: bfxil x5, x6, #12, #52 // encoding: [0xc5,0xfc,0x4c,0xb3]
sxtb w1, w2
sxtb xzr, w3
@@ -1018,9 +1018,9 @@ _func:
sbfiz xzr, xzr, #10, #11
// CHECK: {{sbfiz|sbfx}} w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13]
// CHECK: sbfiz x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0x93]
-// CHECK-ARM64: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93]
+// CHECK: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93]
// CHECK: sbfiz x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0x93]
-// CHECK-ARM64: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13]
+// CHECK: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13]
// CHECK: sbfiz w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x13]
// CHECK: sbfiz w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x13]
// CHECK: sbfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0x93]
@@ -1034,12 +1034,12 @@ _func:
sbfx w13, w14, #29, #3
sbfx xzr, xzr, #10, #11
// CHECK: sbfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13]
-// CHECK-ARM64: asr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0x93]
-// CHECK-ARM64: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93]
-// CHECK-ARM64: asr x9, x10, #5 // encoding: [0x49,0xfd,0x45,0x93]
-// CHECK-ARM64: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13]
-// CHECK-ARM64: asr w11, w12, #31 // encoding: [0x8b,0x7d,0x1f,0x13]
-// CHECK-ARM64: asr w13, w14, #29 // encoding: [0xcd,0x7d,0x1d,0x13]
+// CHECK: asr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0x93]
+// CHECK: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93]
+// CHECK: asr x9, x10, #5 // encoding: [0x49,0xfd,0x45,0x93]
+// CHECK: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13]
+// CHECK: asr w11, w12, #31 // encoding: [0x8b,0x7d,0x1f,0x13]
+// CHECK: asr w13, w14, #29 // encoding: [0xcd,0x7d,0x1d,0x13]
// CHECK: sbfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0x93]
bfi w9, w10, #0, #1
@@ -1051,14 +1051,14 @@ _func:
bfi w13, w14, #29, #3
bfi xzr, xzr, #10, #11
-// CHECK-ARM64: bfxil w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x33]
-// CHECK-ARM64: bfi x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0xb3]
-// CHECK-ARM64: bfxil x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xb3]
-// CHECK-ARM64: bfi x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0xb3]
-// CHECK-ARM64: bfxil w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x33]
-// CHECK-ARM64: bfi w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x33]
-// CHECK-ARM64: bfi w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x33]
-// CHECK-ARM64: bfi xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xb3]
+// CHECK: bfxil w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x33]
+// CHECK: bfi x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0xb3]
+// CHECK: bfxil x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xb3]
+// CHECK: bfi x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0xb3]
+// CHECK: bfxil w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x33]
+// CHECK: bfi w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x33]
+// CHECK: bfi w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x33]
+// CHECK: bfi xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xb3]
bfxil w9, w10, #0, #1
bfxil x2, x3, #63, #1
@@ -1086,14 +1086,14 @@ _func:
ubfiz w13, w14, #29, #3
ubfiz xzr, xzr, #10, #11
-// CHECK-ARM64: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53]
-// CHECK-ARM64: lsl x2, x3, #63 // encoding: [0x62,0x00,0x41,0xd3]
-// CHECK-ARM64: lsr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0xd3]
-// CHECK-ARM64: lsl x9, x10, #5 // encoding: [0x49,0xe9,0x7b,0xd3]
-// CHECK-ARM64: lsr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x53]
-// CHECK-ARM64: lsl w11, w12, #31 // encoding: [0x8b,0x01,0x01,0x53]
-// CHECK-ARM64: lsl w13, w14, #29 // encoding: [0xcd,0x09,0x03,0x53]
-// CHECK-ARM64: ubfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xd3]
+// CHECK: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53]
+// CHECK: lsl x2, x3, #63 // encoding: [0x62,0x00,0x41,0xd3]
+// CHECK: lsr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0xd3]
+// CHECK: lsl x9, x10, #5 // encoding: [0x49,0xe9,0x7b,0xd3]
+// CHECK: lsr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x53]
+// CHECK: lsl w11, w12, #31 // encoding: [0x8b,0x01,0x01,0x53]
+// CHECK: lsl w13, w14, #29 // encoding: [0xcd,0x09,0x03,0x53]
+// CHECK: ubfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xd3]
ubfx w9, w10, #0, #1
ubfx x2, x3, #63, #1
@@ -1104,14 +1104,14 @@ _func:
ubfx w13, w14, #29, #3
ubfx xzr, xzr, #10, #11
-// CHECK-ARM64: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53]
-// CHECK-ARM64: lsr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0xd3]
-// CHECK-ARM64: lsr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0xd3]
-// CHECK-ARM64: lsr x9, x10, #5 // encoding: [0x49,0xfd,0x45,0xd3]
-// CHECK-ARM64: lsr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x53]
-// CHECK-ARM64: lsr w11, w12, #31 // encoding: [0x8b,0x7d,0x1f,0x53]
-// CHECK-ARM64: lsr w13, w14, #29 // encoding: [0xcd,0x7d,0x1d,0x53]
-// CHECK-ARM64: ubfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0xd3]
+// CHECK: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53]
+// CHECK: lsr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0xd3]
+// CHECK: lsr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0xd3]
+// CHECK: lsr x9, x10, #5 // encoding: [0x49,0xfd,0x45,0xd3]
+// CHECK: lsr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x53]
+// CHECK: lsr w11, w12, #31 // encoding: [0x8b,0x7d,0x1f,0x53]
+// CHECK: lsr w13, w14, #29 // encoding: [0xcd,0x7d,0x1d,0x53]
+// CHECK: ubfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0xd3]
//------------------------------------------------------------------------------
// Compare & branch (immediate)
//------------------------------------------------------------------------------
@@ -1120,22 +1120,22 @@ _func:
cbz x5, lbl
cbnz x2, lbl
cbnz x26, lbl
-// CHECK-ARM64: cbz w5, lbl // encoding: [0bAAA00101,A,A,0x34]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: cbz x5, lbl // encoding: [0bAAA00101,A,A,0xb4]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: cbnz x2, lbl // encoding: [0bAAA00010,A,A,0xb5]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: cbnz x26, lbl // encoding: [0bAAA11010,A,A,0xb5]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK: cbz w5, lbl // encoding: [0bAAA00101,A,A,0x34]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: cbz x5, lbl // encoding: [0bAAA00101,A,A,0xb4]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: cbnz x2, lbl // encoding: [0bAAA00010,A,A,0xb5]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: cbnz x26, lbl // encoding: [0bAAA11010,A,A,0xb5]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
cbz wzr, lbl
cbnz xzr, lbl
-// CHECK-ARM64: cbz wzr, lbl // encoding: [0bAAA11111,A,A,0x34]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: cbnz xzr, lbl // encoding: [0bAAA11111,A,A,0xb5]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK: cbz wzr, lbl // encoding: [0bAAA11111,A,A,0x34]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: cbnz xzr, lbl // encoding: [0bAAA11111,A,A,0xb5]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
cbz w5, #0
cbnz x3, #-4
@@ -1168,40 +1168,40 @@ _func:
b.le lbl
b.al lbl
-// CHECK-ARM64: b.eq lbl // encoding: [0bAAA00000,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.ne lbl // encoding: [0bAAA00001,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.hs lbl // encoding: [0bAAA00010,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.hs lbl // encoding: [0bAAA00010,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.lo lbl // encoding: [0bAAA00011,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.lo lbl // encoding: [0bAAA00011,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.mi lbl // encoding: [0bAAA00100,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.pl lbl // encoding: [0bAAA00101,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.vs lbl // encoding: [0bAAA00110,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.vc lbl // encoding: [0bAAA00111,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.hi lbl // encoding: [0bAAA01000,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.ls lbl // encoding: [0bAAA01001,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.ge lbl // encoding: [0bAAA01010,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.lt lbl // encoding: [0bAAA01011,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.gt lbl // encoding: [0bAAA01100,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.le lbl // encoding: [0bAAA01101,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
-// CHECK-ARM64: b.al lbl // encoding: [0bAAA01110,A,A,0x54]
-// CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19
+// CHECK: b.eq lbl // encoding: [0bAAA00000,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.ne lbl // encoding: [0bAAA00001,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.hs lbl // encoding: [0bAAA00010,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.hs lbl // encoding: [0bAAA00010,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.lo lbl // encoding: [0bAAA00011,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.lo lbl // encoding: [0bAAA00011,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.mi lbl // encoding: [0bAAA00100,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.pl lbl // encoding: [0bAAA00101,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.vs lbl // encoding: [0bAAA00110,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.vc lbl // encoding: [0bAAA00111,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.hi lbl // encoding: [0bAAA01000,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.ls lbl // encoding: [0bAAA01001,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.ge lbl // encoding: [0bAAA01010,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.lt lbl // encoding: [0bAAA01011,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.gt lbl // encoding: [0bAAA01100,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.le lbl // encoding: [0bAAA01101,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
+// CHECK: b.al lbl // encoding: [0bAAA01110,A,A,0x54]
+// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
// ARM64 has these in a separate file
beq lbl
@@ -2186,23 +2186,23 @@ _func:
ldr x29, there
ldrsw xzr, everywhere
-// CHECK-ARM64: ldr w3, here // encoding: [0bAAA00011,A,A,0x18]
-// CHECK-ARM64: // fixup A - offset: 0, value: here, kind: fixup_arm64_ldr_pcrel_imm19
-// CHECK-ARM64: ldr x29, there // encoding: [0bAAA11101,A,A,0x58]
-// CHECK-ARM64: // fixup A - offset: 0, value: there, kind: fixup_arm64_ldr_pcrel_imm19
-// CHECK-ARM64: ldrsw xzr, everywhere // encoding: [0bAAA11111,A,A,0x98]
-// CHECK-ARM64: // fixup A - offset: 0, value: everywhere, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK: ldr w3, here // encoding: [0bAAA00011,A,A,0x18]
+// CHECK: // fixup A - offset: 0, value: here, kind: fixup_aarch64_ldr_pcrel_imm19
+// CHECK: ldr x29, there // encoding: [0bAAA11101,A,A,0x58]
+// CHECK: // fixup A - offset: 0, value: there, kind: fixup_aarch64_ldr_pcrel_imm19
+// CHECK: ldrsw xzr, everywhere // encoding: [0bAAA11111,A,A,0x98]
+// CHECK: // fixup A - offset: 0, value: everywhere, kind: fixup_aarch64_ldr_pcrel_imm19
ldr s0, who_knows
ldr d0, i_dont
ldr q0, there_must_be_a_better_way
-// CHECK-ARM64: ldr s0, who_knows // encoding: [0bAAA00000,A,A,0x1c]
-// CHECK-ARM64: // fixup A - offset: 0, value: who_knows, kind: fixup_arm64_ldr_pcrel_imm19
-// CHECK-ARM64: ldr d0, i_dont // encoding: [0bAAA00000,A,A,0x5c]
-// CHECK-ARM64: // fixup A - offset: 0, value: i_dont, kind: fixup_arm64_ldr_pcrel_imm19
-// CHECK-ARM64: ldr q0, there_must_be_a_better_way // encoding: [0bAAA00000,A,A,0x9c]
-// CHECK-ARM64: // fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK: ldr s0, who_knows // encoding: [0bAAA00000,A,A,0x1c]
+// CHECK: // fixup A - offset: 0, value: who_knows, kind: fixup_aarch64_ldr_pcrel_imm19
+// CHECK: ldr d0, i_dont // encoding: [0bAAA00000,A,A,0x5c]
+// CHECK: // fixup A - offset: 0, value: i_dont, kind: fixup_aarch64_ldr_pcrel_imm19
+// CHECK: ldr q0, there_must_be_a_better_way // encoding: [0bAAA00000,A,A,0x9c]
+// CHECK: // fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_aarch64_ldr_pcrel_imm19
ldr w0, #1048572
ldr x10, #-1048576
@@ -2212,10 +2212,10 @@ _func:
prfm pldl1strm, nowhere
prfm #22, somewhere
-// CHECK-ARM64: prfm pldl1strm, nowhere // encoding: [0bAAA00001,A,A,0xd8]
-// CHECK-ARM64: // fixup A - offset: 0, value: nowhere, kind: fixup_arm64_ldr_pcrel_imm19
-// CHECK-ARM64: prfm #22, somewhere // encoding: [0bAAA10110,A,A,0xd8]
-// CHECK-ARM64: // fixup A - offset: 0, value: somewhere, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK: prfm pldl1strm, nowhere // encoding: [0bAAA00001,A,A,0xd8]
+// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_ldr_pcrel_imm19
+// CHECK: prfm #22, somewhere // encoding: [0bAAA10110,A,A,0xd8]
+// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_ldr_pcrel_imm19
//------------------------------------------------------------------------------
// Load/store exclusive
@@ -2431,18 +2431,18 @@ _func:
ldr x15, [x5, #:lo12:sym]
ldr q3, [x2, #:lo12:sym]
-// CHECK-ARM64: str x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b00AAAAAA,0xf9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK-ARM64: ldrb w15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0x39]
-// CHECK-ARM64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK-ARM64: ldrsh x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0x79]
-// CHECK-ARM64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale2
-// CHECK-ARM64: ldrsw x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0xb9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale4
-// CHECK-ARM64: ldr x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0xf9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK-ARM64: ldr q3, [x2, :lo12:sym] // encoding: [0x43,0bAAAAAA00,0b11AAAAAA,0x3d]
-// CHECK-ARM64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale16
+// CHECK: str x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b00AAAAAA,0xf9]
+// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale8
+// CHECK: ldrb w15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0x39]
+// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale1
+// CHECK: ldrsh x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0x79]
+// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale2
+// CHECK: ldrsw x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0xb9]
+// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale4
+// CHECK: ldr x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0xf9]
+// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale8
+// CHECK: ldr q3, [x2, :lo12:sym] // encoding: [0x43,0bAAAAAA00,0b11AAAAAA,0x3d]
+// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale16
prfm pldl1keep, [sp, #8]
prfm pldl1strm, [x3]
@@ -3323,34 +3323,34 @@ _func:
movz x2, #:abs_g0:sym
movk w3, #:abs_g0_nc:sym
-// CHECK-ARM64: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_arm64_movw
+// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_aarch64_movw
+// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_aarch64_movw
movz x4, #:abs_g1:sym
movk w5, #:abs_g1_nc:sym
-// CHECK-ARM64: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_arm64_movw
+// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_aarch64_movw
+// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_aarch64_movw
movz x6, #:abs_g2:sym
movk x7, #:abs_g2_nc:sym
-// CHECK-ARM64: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_arm64_movw
+// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_aarch64_movw
+// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_aarch64_movw
movz x8, #:abs_g3:sym
movk x9, #:abs_g3:sym
-// CHECK-ARM64: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movk x9, #:abs_g3:sym // encoding: [0bAAA01001,A,0b111AAAAA,0xf2]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw
+// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_aarch64_movw
+// CHECK: movk x9, #:abs_g3:sym // encoding: [0bAAA01001,A,0b111AAAAA,0xf2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_aarch64_movw
movn x30, #:abs_g0_s:sym
@@ -3358,36 +3358,36 @@ _func:
movn w10, #:abs_g0_s:sym
movz w25, #:abs_g0_s:sym
-// CHECK-ARM64: movn x30, #:abs_g0_s:sym // encoding: [0bAAA11110,A,0b100AAAAA,0x92]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movz x19, #:abs_g0_s:sym // encoding: [0bAAA10011,A,0b100AAAAA,0xd2]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movn w10, #:abs_g0_s:sym // encoding: [0bAAA01010,A,0b100AAAAA,0x12]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movz w25, #:abs_g0_s:sym // encoding: [0bAAA11001,A,0b100AAAAA,0x52]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_arm64_movw
+// CHECK: movn x30, #:abs_g0_s:sym // encoding: [0bAAA11110,A,0b100AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw
+// CHECK: movz x19, #:abs_g0_s:sym // encoding: [0bAAA10011,A,0b100AAAAA,0xd2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw
+// CHECK: movn w10, #:abs_g0_s:sym // encoding: [0bAAA01010,A,0b100AAAAA,0x12]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw
+// CHECK: movz w25, #:abs_g0_s:sym // encoding: [0bAAA11001,A,0b100AAAAA,0x52]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw
movn x30, #:abs_g1_s:sym
movz x19, #:abs_g1_s:sym
movn w10, #:abs_g1_s:sym
movz w25, #:abs_g1_s:sym
-// CHECK-ARM64: movn x30, #:abs_g1_s:sym // encoding: [0bAAA11110,A,0b101AAAAA,0x92]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movz x19, #:abs_g1_s:sym // encoding: [0bAAA10011,A,0b101AAAAA,0xd2]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movn w10, #:abs_g1_s:sym // encoding: [0bAAA01010,A,0b101AAAAA,0x12]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movz w25, #:abs_g1_s:sym // encoding: [0bAAA11001,A,0b101AAAAA,0x52]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_arm64_movw
+// CHECK: movn x30, #:abs_g1_s:sym // encoding: [0bAAA11110,A,0b101AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw
+// CHECK: movz x19, #:abs_g1_s:sym // encoding: [0bAAA10011,A,0b101AAAAA,0xd2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw
+// CHECK: movn w10, #:abs_g1_s:sym // encoding: [0bAAA01010,A,0b101AAAAA,0x12]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw
+// CHECK: movz w25, #:abs_g1_s:sym // encoding: [0bAAA11001,A,0b101AAAAA,0x52]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw
movn x30, #:abs_g2_s:sym
movz x19, #:abs_g2_s:sym
-// CHECK-ARM64: movn x30, #:abs_g2_s:sym // encoding: [0bAAA11110,A,0b110AAAAA,0x92]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_arm64_movw
-// CHECK-ARM64: movz x19, #:abs_g2_s:sym // encoding: [0bAAA10011,A,0b110AAAAA,0xd2]
-// CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_arm64_movw
+// CHECK: movn x30, #:abs_g2_s:sym // encoding: [0bAAA11110,A,0b110AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_aarch64_movw
+// CHECK: movz x19, #:abs_g2_s:sym // encoding: [0bAAA10011,A,0b110AAAAA,0xd2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_aarch64_movw
//------------------------------------------------------------------------------
// PC-relative addressing
@@ -3396,15 +3396,15 @@ _func:
adr x2, loc
adr xzr, loc
-// CHECK-ARM64: adr x2, loc // encoding: [0x02'A',A,A,0x10'A']
-// CHECK-ARM64: // fixup A - offset: 0, value: loc, kind: fixup_arm64_pcrel_adr_imm21
-// CHECK-ARM64: adr xzr, loc // encoding: [0x1f'A',A,A,0x10'A']
-// CHECK-ARM64: // fixup A - offset: 0, value: loc, kind: fixup_arm64_pcrel_adr_imm21
+// CHECK: adr x2, loc // encoding: [0x02'A',A,A,0x10'A']
+// CHECK: // fixup A - offset: 0, value: loc, kind: fixup_aarch64_pcrel_adr_imm21
+// CHECK: adr xzr, loc // encoding: [0x1f'A',A,A,0x10'A']
+// CHECK: // fixup A - offset: 0, value: loc, kind: fixup_aarch64_pcrel_adr_imm21
adrp x29, loc
-// CHECK-ARM64: adrp x29, loc // encoding: [0x1d'A',A,A,0x90'A']
-// CHECK-ARM64: // fixup A - offset: 0, value: loc, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK: adrp x29, loc // encoding: [0x1d'A',A,A,0x90'A']
+// CHECK: // fixup A - offset: 0, value: loc, kind: fixup_aarch64_pcrel_adrp_imm21
adrp x30, #4096
adr x20, #0
adr x9, #-1
@@ -4782,24 +4782,24 @@ _func:
tbz xzr, #63, elsewhere
tbnz x5, #45, nowhere
-// CHECK-ARM64: tbz w5, #0, somewhere // encoding: [0bAAA00101,A,0b00000AAA,0x36]
-// CHECK-ARM64: // fixup A - offset: 0, value: somewhere, kind: fixup_arm64_pcrel_branch14
-// CHECK-ARM64: tbz xzr, #63, elsewhere // encoding: [0bAAA11111,A,0b11111AAA,0xb6]
-// CHECK-ARM64: // fixup A - offset: 0, value: elsewhere, kind: fixup_arm64_pcrel_branch14
-// CHECK-ARM64: tbnz x5, #45, nowhere // encoding: [0bAAA00101,A,0b01101AAA,0xb7]
-// CHECK-ARM64: // fixup A - offset: 0, value: nowhere, kind: fixup_arm64_pcrel_branch14
+// CHECK: tbz w5, #0, somewhere // encoding: [0bAAA00101,A,0b00000AAA,0x36]
+// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_pcrel_branch14
+// CHECK: tbz xzr, #63, elsewhere // encoding: [0bAAA11111,A,0b11111AAA,0xb6]
+// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_aarch64_pcrel_branch14
+// CHECK: tbnz x5, #45, nowhere // encoding: [0bAAA00101,A,0b01101AAA,0xb7]
+// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_pcrel_branch14
tbnz w3, #2, there
tbnz wzr, #31, nowhere
tbz w5, #12, anywhere
-// CHECK-ARM64: tbnz w3, #2, there // encoding: [0bAAA00011,A,0b00010AAA,0x37]
-// CHECK-ARM64: // fixup A - offset: 0, value: there, kind: fixup_arm64_pcrel_branch14
-// CHECK-ARM64: tbnz wzr, #31, nowhere // encoding: [0bAAA11111,A,0b11111AAA,0x37]
-// CHECK-ARM64: // fixup A - offset: 0, value: nowhere, kind: fixup_arm64_pcrel_branch14
-// CHECK-ARM64: tbz w5, #12, anywhere // encoding: [0bAAA00101,A,0b01100AAA,0x36]
-// CHECK-ARM64: // fixup A - offset: 0, value: anywhere, kind: fixup_arm64_pcrel_branch14
+// CHECK: tbnz w3, #2, there // encoding: [0bAAA00011,A,0b00010AAA,0x37]
+// CHECK: // fixup A - offset: 0, value: there, kind: fixup_aarch64_pcrel_branch14
+// CHECK: tbnz wzr, #31, nowhere // encoding: [0bAAA11111,A,0b11111AAA,0x37]
+// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_pcrel_branch14
+// CHECK: tbz w5, #12, anywhere // encoding: [0bAAA00101,A,0b01100AAA,0x36]
+// CHECK: // fixup A - offset: 0, value: anywhere, kind: fixup_aarch64_pcrel_branch14
//------------------------------------------------------------------------------
// Unconditional branch (immediate)
@@ -4808,10 +4808,10 @@ _func:
b somewhere
bl elsewhere
-// CHECK-ARM64: b somewhere // encoding: [A,A,A,0b000101AA]
-// CHECK-ARM64: // fixup A - offset: 0, value: somewhere, kind: fixup_arm64_pcrel_branch26
-// CHECK-ARM64: bl elsewhere // encoding: [A,A,A,0b100101AA]
-// CHECK-ARM64: // fixup A - offset: 0, value: elsewhere, kind: fixup_arm64_pcrel_call26
+// CHECK: b somewhere // encoding: [A,A,A,0b000101AA]
+// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_pcrel_branch26
+// CHECK: bl elsewhere // encoding: [A,A,A,0b100101AA]
+// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_aarch64_pcrel_call26
b #4
bl #0
Modified: llvm/trunk/test/MC/AArch64/basic-pic.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/basic-pic.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/basic-pic.s (original)
+++ llvm/trunk/test/MC/AArch64/basic-pic.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o -| llvm-objdump -r - | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o -| llvm-objdump -r - | FileCheck %s
// CHECK: RELOCATION RECORDS FOR [.rela.text]
Modified: llvm/trunk/test/MC/AArch64/elf-extern.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/elf-extern.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/elf-extern.s (original)
+++ llvm/trunk/test/MC/AArch64/elf-extern.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc < %s -triple=arm64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s
+// RUN: llvm-mc < %s -triple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s
// External symbols are a different concept to global variables but should still
// get relocations and so on when used.
Modified: llvm/trunk/test/MC/AArch64/elf-objdump.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/elf-objdump.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/elf-objdump.s (original)
+++ llvm/trunk/test/MC/AArch64/elf-objdump.s Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
// 64 bit little endian
-// RUN: llvm-mc -filetype=obj -triple arm64-none-linux-gnu %s -o - | llvm-objdump -d -
+// RUN: llvm-mc -filetype=obj -triple aarch64-none-linux-gnu %s -o - | llvm-objdump -d -
// We just want to see if llvm-objdump works at all.
// CHECK: .text
Modified: llvm/trunk/test/MC/AArch64/elf-reloc-addsubimm.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/elf-reloc-addsubimm.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/elf-reloc-addsubimm.s (original)
+++ llvm/trunk/test/MC/AArch64/elf-reloc-addsubimm.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
add x2, x3, #:lo12:some_label
Modified: llvm/trunk/test/MC/AArch64/elf-reloc-ldrlit.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/elf-reloc-ldrlit.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/elf-reloc-ldrlit.s (original)
+++ llvm/trunk/test/MC/AArch64/elf-reloc-ldrlit.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
ldr x0, some_label
Modified: llvm/trunk/test/MC/AArch64/elf-reloc-ldstunsimm.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/elf-reloc-ldstunsimm.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/elf-reloc-ldstunsimm.s (original)
+++ llvm/trunk/test/MC/AArch64/elf-reloc-ldstunsimm.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+fp-armv8 -filetype=obj %s -o - | \
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+fp-armv8 -filetype=obj %s -o - | \
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
ldrb w0, [sp, #:lo12:some_label]
Modified: llvm/trunk/test/MC/AArch64/elf-reloc-movw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/elf-reloc-movw.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/elf-reloc-movw.s (original)
+++ llvm/trunk/test/MC/AArch64/elf-reloc-movw.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
movz x0, #:abs_g0:some_label
Modified: llvm/trunk/test/MC/AArch64/elf-reloc-pcreladdressing.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/elf-reloc-pcreladdressing.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/elf-reloc-pcreladdressing.s (original)
+++ llvm/trunk/test/MC/AArch64/elf-reloc-pcreladdressing.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
adr x2, some_label
Modified: llvm/trunk/test/MC/AArch64/elf-reloc-tstb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/elf-reloc-tstb.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/elf-reloc-tstb.s (original)
+++ llvm/trunk/test/MC/AArch64/elf-reloc-tstb.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
tbz x6, #45, somewhere
Modified: llvm/trunk/test/MC/AArch64/elf-reloc-uncondbrimm.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/elf-reloc-uncondbrimm.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/elf-reloc-uncondbrimm.s (original)
+++ llvm/trunk/test/MC/AArch64/elf-reloc-uncondbrimm.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
b somewhere
Modified: llvm/trunk/test/MC/AArch64/gicv3-regs-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/gicv3-regs-diagnostics.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/gicv3-regs-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/gicv3-regs-diagnostics.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple arm64-none-linux-gnu < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
// Write-only
mrs x10, icc_eoir1_el1
Modified: llvm/trunk/test/MC/AArch64/gicv3-regs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/gicv3-regs.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/gicv3-regs.s (original)
+++ llvm/trunk/test/MC/AArch64/gicv3-regs.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
- // RUN: llvm-mc -triple arm64-none-linux-gnu -show-encoding < %s | FileCheck %s
+ // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
mrs x8, icc_iar1_el1
mrs x26, icc_iar0_el1
Modified: llvm/trunk/test/MC/AArch64/inline-asm-modifiers.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/inline-asm-modifiers.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/inline-asm-modifiers.s (original)
+++ llvm/trunk/test/MC/AArch64/inline-asm-modifiers.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -mattr=+fp-armv8 < %s | llvm-objdump -r - | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -mattr=+fp-armv8 < %s | llvm-objdump -r - | FileCheck %s
.file "<stdin>"
.text
Modified: llvm/trunk/test/MC/AArch64/jump-table.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/jump-table.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/jump-table.s (original)
+++ llvm/trunk/test/MC/AArch64/jump-table.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc < %s -triple=arm64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s
+// RUN: llvm-mc < %s -triple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s
.file "<stdin>"
.text
Modified: llvm/trunk/test/MC/AArch64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/lit.local.cfg?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/lit.local.cfg (original)
+++ llvm/trunk/test/MC/AArch64/lit.local.cfg Sat May 24 07:50:23 2014
@@ -1,3 +1,3 @@
targets = set(config.root.targets_to_build.split())
-if 'ARM64' not in targets:
+if 'AArch64' not in targets:
config.unsupported = True
Modified: llvm/trunk/test/MC/AArch64/mapping-across-sections.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/mapping-across-sections.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/mapping-across-sections.s (original)
+++ llvm/trunk/test/MC/AArch64/mapping-across-sections.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
.text
add w0, w0, w0
Modified: llvm/trunk/test/MC/AArch64/mapping-within-section.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/mapping-within-section.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/mapping-within-section.s (original)
+++ llvm/trunk/test/MC/AArch64/mapping-within-section.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
.text
// $x at 0x0000
Modified: llvm/trunk/test/MC/AArch64/neon-3vdiff.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-3vdiff.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-3vdiff.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-3vdiff.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+crypto -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+crypto -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-aba-abd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-aba-abd.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-aba-abd.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-aba-abd.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-add-pairwise.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-add-pairwise.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-add-pairwise.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-add-pairwise.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-add-sub-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-add-sub-instructions.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-add-sub-instructions.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-add-sub-instructions.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-bitwise-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-bitwise-instructions.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-bitwise-instructions.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-bitwise-instructions.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-compare-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-compare-instructions.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-compare-instructions.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-compare-instructions.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-diagnostics.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-diagnostics.s Sat May 24 07:50:23 2014
@@ -1,6 +1,5 @@
-
-// RUN: not llvm-mc -triple arm64-none-linux-gnu -mattr=+neon < %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-ARM64-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
//------------------------------------------------------------------------------
// Vector Integer Add/sub
@@ -589,12 +588,12 @@
// CHECK-ERROR: fcmgt v0.2d, v31.2s, v16.2s
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
-// CHECK-ARM64-ERROR: fcmgt v4.4s, v7.4s, v15.4h
-// CHECK-ARM64-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
-// CHECK-ARM64-ERROR: fcmlt v29.2d, v5.2d, v2.16b
-// CHECK-ARM64-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: fcmgt v4.4s, v7.4s, v15.4h
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: fcmlt v29.2d, v5.2d, v2.16b
+// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Vector Compare Mask Equal to Zero (Integer)
@@ -684,12 +683,12 @@
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: expected floating-point constant #0.0
-// CHECK-ARM64-ERROR: fcmeq v0.8b, v1.4h, #1.0
-// CHECK-ARM64-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
-// CHECK-ARM64-ERROR: fcmeq v0.8b, v1.4h, #1
-// CHECK-ARM64-ERROR: ^
+// CHECK-ERROR: error: expected floating-point constant #0.0
+// CHECK-ERROR: fcmeq v0.8b, v1.4h, #1.0
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: fcmeq v0.8b, v1.4h, #1
+// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
@@ -709,12 +708,12 @@
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: expected floating-point constant #0.0
-// CHECK-ARM64-ERROR: fcmle v17.8h, v15.2d, #-1.0
-// CHECK-ARM64-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
-// CHECK-ARM64-ERROR: fcmle v17.8h, v15.2d, #2
-// CHECK-ARM64-ERROR: ^
+// CHECK-ERROR: error: expected floating-point constant #0.0
+// CHECK-ERROR: fcmle v17.8h, v15.2d, #-1.0
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: fcmle v17.8h, v15.2d, #2
+// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Vector Compare Mask Greater Than Zero (Floating Point)
@@ -733,12 +732,12 @@
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: expected floating-point constant #0.0
-// CHECK-ARM64-ERROR: fcmlt v29.2d, v5.2d, #255.0
-// CHECK-ARM64-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
-// CHECK-ARM64-ERROR: fcmlt v29.2d, v5.2d, #255
-// CHECK-ARM64-ERROR: ^
+// CHECK-ERROR: error: expected floating-point constant #0.0
+// CHECK-ERROR: fcmlt v29.2d, v5.2d, #255.0
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: fcmlt v29.2d, v5.2d, #255
+// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Vector Compare Mask Less Than or Equal To Zero (Floating Point)
@@ -757,12 +756,12 @@
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: expected floating-point constant #0.0
-// CHECK-ARM64-ERROR: fcmle v17.2d, v15.2d, #15.0
-// CHECK-ARM64-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
-// CHECK-ARM64-ERROR: fcmle v17.2d, v15.2d, #15
-// CHECK-ARM64-ERROR: ^
+// CHECK-ERROR: error: expected floating-point constant #0.0
+// CHECK-ERROR: fcmle v17.2d, v15.2d, #15.0
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: fcmle v17.2d, v15.2d, #15
+// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Vector Compare Mask Less Than Zero (Floating Point)
@@ -781,12 +780,12 @@
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: expected floating-point constant #0.0
-// CHECK-ARM64-ERROR: fcmlt v29.2d, v5.2d, #16.0
-// CHECK-ARM64-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
-// CHECK-ARM64-ERROR: fcmlt v29.2d, v5.2d, #2
-// CHECK-ARM64-ERROR: ^
+// CHECK-ERROR: error: expected floating-point constant #0.0
+// CHECK-ERROR: fcmlt v29.2d, v5.2d, #16.0
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: fcmlt v29.2d, v5.2d, #2
+// CHECK-ERROR: ^
/-----------------------------------------------------------------------
// Vector Integer Halving Add (Signed)
@@ -1300,9 +1299,9 @@
shl v0.2d, v1.2d, #64
-// CHECK-ARM64-ERROR: error: unexpected token in argument list
-// CHECK-ARM64-ERROR: shl v0.4s, v15,2s, #3
-// CHECK-ARM64-ERROR: ^
+// CHECK-ERROR: error: unexpected token in argument list
+// CHECK-ERROR: shl v0.4s, v15,2s, #3
+// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: shl v0.2d, v17.4s, #3
@@ -2633,9 +2632,9 @@
pmull2 v0.2d, v1.4s, v2.4s
-// CHECK-ARM64-ERROR: error: unexpected token in argument list
-// CHECK-ARM64-ERROR: pmull2 v0.4s, v1.8h v2.8h
-// CHECK-ARM64-ERROR: ^
+// CHECK-ERROR: error: unexpected token in argument list
+// CHECK-ERROR: pmull2 v0.4s, v1.8h v2.8h
+// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: pmull2 v0.2d, v1.4s, v2.4s
@@ -2959,19 +2958,19 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: mla v0.2d, v1.2d, v16.d[1]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mla v0.2s, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mla v0.4s, v1.4s, v2.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: mla v0.2h, v1.2h, v2.h[1]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mla v0.4h, v1.4h, v2.h[8]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mla v0.8h, v1.8h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -2993,19 +2992,19 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: mls v0.2d, v1.2d, v16.d[1]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mls v0.2s, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mls v0.4s, v1.4s, v2.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: mls v0.2h, v1.2h, v2.h[1]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mls v0.4h, v1.4h, v2.h[8]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mls v0.8h, v1.8h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3030,22 +3029,22 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: fmla v0.8h, v1.8h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmla v0.2s, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmla v0.2s, v1.2s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmla v3.4s, v8.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmla v3.4s, v8.4s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmla v0.2d, v1.2d, v2.d[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmla v0.2d, v1.2d, v22.d[2]
// CHECK-ERROR: ^
@@ -3064,22 +3063,22 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: fmls v0.8h, v1.8h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmls v0.2s, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmls v0.2s, v1.2s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmls v3.4s, v8.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmls v3.4s, v8.4s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmls v0.2d, v1.2d, v2.d[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmls v0.2d, v1.2d, v22.d[2]
// CHECK-ERROR: ^
@@ -3099,7 +3098,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smlal v0.4h, v1.4h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlal v0.4s, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3108,16 +3107,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smlal v0.2s, v1.2s, v2.s[1]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlal v0.2d, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlal v0.2d, v1.2s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smlal2 v0.4h, v1.8h, v1.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlal2 v0.4s, v1.8h, v1.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3126,10 +3125,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smlal2 v0.2s, v1.4s, v1.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlal2 v0.2d, v1.4s, v1.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlal2 v0.2d, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3149,7 +3148,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smlsl v0.4h, v1.4h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlsl v0.4s, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3158,16 +3157,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smlsl v0.2s, v1.2s, v2.s[1]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlsl v0.2d, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlsl v0.2d, v1.2s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smlsl2 v0.4h, v1.8h, v1.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlsl2 v0.4s, v1.8h, v1.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3176,10 +3175,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smlsl2 v0.2s, v1.4s, v1.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlsl2 v0.2d, v1.4s, v1.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smlsl2 v0.2d, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3199,7 +3198,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umlal v0.4h, v1.4h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlal v0.4s, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3208,16 +3207,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umlal v0.2s, v1.2s, v2.s[1]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlal v0.2d, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlal v0.2d, v1.2s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umlal2 v0.4h, v1.8h, v1.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlal2 v0.4s, v1.8h, v1.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3226,10 +3225,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umlal2 v0.2s, v1.4s, v1.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlal2 v0.2d, v1.4s, v1.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlal2 v0.2d, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3249,7 +3248,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umlsl v0.4h, v1.4h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlsl v0.4s, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3258,16 +3257,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umlsl v0.2s, v1.2s, v2.s[3]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlsl v0.2d, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlsl v0.2d, v1.2s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umlsl2 v0.4h, v1.8h, v1.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlsl2 v0.4s, v1.8h, v1.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3276,10 +3275,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umlsl2 v0.2s, v1.4s, v1.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlsl2 v0.2d, v1.4s, v1.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umlsl2 v0.2d, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3299,7 +3298,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlal v0.4h, v1.4h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlal v0.4s, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3308,16 +3307,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlal v0.2s, v1.2s, v2.s[3]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlal v0.2d, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlal v0.2d, v1.2s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlal2 v0.4h, v1.8h, v1.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlal2 v0.4s, v1.8h, v1.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3326,10 +3325,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlal2 v0.2s, v1.4s, v1.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v1.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3349,7 +3348,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlsl v0.4h, v1.4h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlsl v0.4s, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3358,16 +3357,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlsl v0.2s, v1.2s, v2.s[3]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlsl2 v0.4h, v1.8h, v1.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlsl2 v0.4s, v1.8h, v1.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3376,10 +3375,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlsl2 v0.2s, v1.4s, v1.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v1.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3393,28 +3392,28 @@
mul v0.4s, v1.4s, v22.s[4]
mul v0.2d, v1.2d, v2.d[1]
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mul v0.4h, v1.4h, v2.h[8]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: mul v0.4h, v1.4h, v16.h[8]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mul v0.8h, v1.8h, v2.h[8]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: invalid operand for instruction
+// CHECK-ERROR: invalid operand for instruction
// CHECK-ERROR: mul v0.8h, v1.8h, v16.h[8]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mul v0.2s, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mul v0.2s, v1.2s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mul v0.4s, v1.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: mul v0.4s, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3432,22 +3431,22 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: fmul v0.4h, v1.4h, v2.h[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmul v0.2s, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmul v0.2s, v1.2s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmul v0.4s, v1.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmul v0.4s, v1.4s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmul v0.2d, v1.2d, v2.d[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmul v0.2d, v1.2d, v22.d[2]
// CHECK-ERROR: ^
@@ -3462,22 +3461,22 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: fmulx v0.4h, v1.4h, v2.h[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmulx v0.2s, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmulx v0.2s, v1.2s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmulx v0.4s, v1.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmulx v0.4s, v1.4s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmulx v0.2d, v1.2d, v2.d[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmulx v0.2d, v1.2d, v22.d[2]
// CHECK-ERROR: ^
@@ -3497,7 +3496,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smull v0.4h, v1.4h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smull v0.4s, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3506,16 +3505,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smull v0.2s, v1.2s, v2.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smull v0.2d, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smull v0.2d, v1.2s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smull2 v0.4h, v1.8h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smull2 v0.4s, v1.8h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3524,10 +3523,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: smull2 v0.2s, v1.4s, v2.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smull2 v0.2d, v1.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: smull2 v0.2d, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3547,7 +3546,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umull v0.4h, v1.4h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umull v0.4s, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3556,16 +3555,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umull v0.2s, v1.2s, v2.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umull v0.2d, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umull v0.2d, v1.2s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umull2 v0.4h, v1.8h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umull2 v0.4s, v1.8h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3574,10 +3573,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: umull2 v0.2s, v1.4s, v2.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umull2 v0.2d, v1.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: umull2 v0.2d, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3597,7 +3596,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmull v0.4h, v1.4h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmull v0.4s, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3606,16 +3605,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmull v0.2s, v1.2s, v2.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmull v0.2d, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmull v0.2d, v1.2s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmull2 v0.4h, v1.8h, v2.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmull2 v0.4s, v1.8h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3624,10 +3623,10 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmull2 v0.2s, v1.4s, v2.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v22.s[4]
// CHECK-ERROR: ^
@@ -3641,28 +3640,28 @@
sqdmulh v0.4s, v1.4s, v22.s[4]
sqdmulh v0.2d, v1.2d, v22.d[1]
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmulh v0.4h, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmulh v0.4h, v1.4h, v16.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmulh v0.8h, v1.8h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmulh v0.8h, v1.8h, v16.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmulh v0.2s, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmulh v0.2s, v1.2s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmulh v0.4s, v1.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmulh v0.4s, v1.4s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3679,28 +3678,28 @@
sqrdmulh v0.4s, v1.4s, v22.s[4]
sqrdmulh v0.2d, v1.2d, v22.d[1]
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v16.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v2.h[8]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v16.h[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v22.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v2.s[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v22.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3918,13 +3917,13 @@
ld1 {v4}, [x0]
ld1 {v32.16b}, [x0]
ld1 {v15.8h}, [x32]
-// CHECK-ARM64-ERROR: error: vector register expected
+// CHECK-ERROR: error: vector register expected
// CHECK-ERROR: ld1 {x3}, [x2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ld1 {v4}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: vector register expected
+// CHECK-ERROR: error: vector register expected
// CHECK-ERROR: ld1 {v32.16b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3938,13 +3937,13 @@
ld1 {v1.8h-v1.8h}, [x0]
ld1 {v15.8h-v17.4h}, [x15]
ld1 {v0.8b-v2.8b, [x0]
-// CHECK-ARM64-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: ld1 {v0.16b, v2.16b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
// CHECK-ERROR: ld1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: unexpected token in argument list
+// CHECK-ERROR: error: unexpected token in argument list
// CHECK-ERROR: ld1 v0.8b, v1.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
@@ -3953,7 +3952,7 @@
// CHECK-ERROR: error: invalid number of vectors
// CHECK-ERROR: ld1 {v1.8h-v1.8h}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld1 {v15.8h-v17.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: '}' expected
@@ -3965,15 +3964,15 @@
ld2 {v15.4h, v16.4h, v17.4h}, [x32]
ld2 {v15.8h-v16.4h}, [x15]
ld2 {v0.2d-v2.2d}, [x0]
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld2 {v15.8h, v16.4h}, [x15]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: ld2 {v0.8b, v2.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: ld2 {v15.4h, v16.4h, v17.4h}, [x32]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld2 {v15.8h-v16.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -3985,16 +3984,16 @@
ld3 {v0.8b, v2.8b, v3.8b}, [x0]
ld3 {v15.8h-v17.4h}, [x15]
ld3 {v31.4s-v2.4s}, [sp]
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld3 {v15.8h, v16.8h, v17.4h}, [x15]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: ld3 {v0.8b, v2.8b, v3.8b}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld3 {v15.8h-v17.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4006,16 +4005,16 @@
ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31]
ld4 {v15.8h-v18.4h}, [x15]
ld4 {v31.2s-v1.2s}, [x31]
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
// CHECK-ERROR: ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld4 {v15.8h-v18.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4026,13 +4025,13 @@
st1 {v4}, [x0]
st1 {v32.16b}, [x0]
st1 {v15.8h}, [x32]
-// CHECK-ARM64-ERROR: error: vector register expected
+// CHECK-ERROR: error: vector register expected
// CHECK-ERROR: st1 {x3}, [x2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: st1 {v4}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: vector register expected
+// CHECK-ERROR: error: vector register expected
// CHECK-ERROR: st1 {v32.16b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4046,13 +4045,13 @@
st1 {v1.8h-v1.8h}, [x0]
st1 {v15.8h-v17.4h}, [x15]
st1 {v0.8b-v2.8b, [x0]
-// CHECK-ARM64-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: st1 {v0.16b, v2.16b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
// CHECK-ERROR: st1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: unexpected token in argument list
+// CHECK-ERROR: error: unexpected token in argument list
// CHECK-ERROR: st1 v0.8b, v1.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
@@ -4061,7 +4060,7 @@
// CHECK-ERROR: error: invalid number of vectors
// CHECK-ERROR: st1 {v1.8h-v1.8h}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st1 {v15.8h-v17.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: '}' expected
@@ -4073,16 +4072,16 @@
st2 {v15.4h, v16.4h, v17.4h}, [x30]
st2 {v15.8h-v16.4h}, [x15]
st2 {v0.2d-v2.2d}, [x0]
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st2 {v15.8h, v16.4h}, [x15]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: st2 {v0.8b, v2.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: st2 {v15.4h, v16.4h, v17.4h}, [x30]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st2 {v15.8h-v16.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4094,16 +4093,16 @@
st3 {v0.8b, v2.8b, v3.8b}, [x0]
st3 {v15.8h-v17.4h}, [x15]
st3 {v31.4s-v2.4s}, [sp]
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st3 {v15.8h, v16.8h, v17.4h}, [x15]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: st3 {v0.8b, v2.8b, v3.8b}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st3 {v15.8h-v17.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4115,16 +4114,16 @@
st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31]
st4 {v15.8h-v18.4h}, [x15]
st4 {v31.2s-v1.2s}, [x31]
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
// CHECK-ERROR: st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st4 {v15.8h-v18.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4141,7 +4140,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ld1 {v0.16b}, [x0], #8
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: ld1 {v0.8h, v1.16h}, [x0], x1
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4157,7 +4156,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ld3 {v5.2s, v6.2s, v7.2s}, [x1], #48
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1
// CHECK-ERROR: ^
@@ -4167,7 +4166,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: st1 {v0.16b}, [x0], #8
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid vector kind qualifier
+// CHECK-ERROR: error: invalid vector kind qualifier
// CHECK-ERROR: st1 {v0.8h, v1.16h}, [x0], x1
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4183,7 +4182,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: st3 {v5.2s, v6.2s, v7.2s}, [x1], #48
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1
// CHECK-ERROR: ^
@@ -4195,16 +4194,16 @@
ld2r {v31.4s, v0.2s}, [sp]
ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp]
-// CHECK-ARM64-ERROR: error: vector register expected
+// CHECK-ERROR: error: vector register expected
// CHECK-ERROR: ld1r {x1}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld2r {v31.4s, v0.2s}, [sp]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp]
// CHECK-ERROR: ^
@@ -4216,16 +4215,16 @@
ld2 {v15.h, v16.h}[8], [x15]
ld3 {v31.s, v0.s, v1.s}[-1], [sp]
ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0]
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: ld1 {v0.b}[16], [x0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: ld2 {v15.h, v16.h}[8], [x15]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: vector lane must be an integer in range
+// CHECK-ERROR: error: vector lane must be an integer in range
// CHECK-ERROR: ld3 {v31.s, v0.s, v1.s}[-1], [sp]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0]
// CHECK-ERROR: ^
@@ -4233,16 +4232,16 @@
st2 {v31.s, v0.s}[3], [8]
st3 {v15.h, v16.h, v17.h}[-1], [x15]
st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0]
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: st1 {v0.d}[16], [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: st2 {v31.s, v0.s}[3], [8]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: vector lane must be an integer in range
+// CHECK-ERROR: error: vector lane must be an integer in range
// CHECK-ERROR: st3 {v15.h, v16.h, v17.h}[-1], [x15]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0]
// CHECK-ERROR: ^
@@ -4281,7 +4280,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ld2 {v15.h, v16.h}[0], [x15], #3
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: mismatched register size suffix
+// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld3 {v31.s, v0.s, v1.d}[0], [sp], x9
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4315,16 +4314,16 @@
ins v20.s[1], s30
ins v1.d[0], d7
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: ins v2.b[16], w1
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: ins v7.h[8], w14
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: ins v20.s[5], w30
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: ins v1.d[2], x7
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -4351,19 +4350,19 @@
smov x14, v6.d[1]
smov x20, v9.d[0]
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR smov w1, v0.b[16]
// CHECK-ERROR ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR smov w14, v6.h[8]
// CHECK-ERROR ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR smov x1, v0.b[16]
// CHECK-ERROR ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR smov x14, v6.h[8]
// CHECK-ERROR ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR smov x20, v9.s[5]
// CHECK-ERROR ^
// CHECK-ERROR error: invalid operand for instruction
@@ -4390,16 +4389,16 @@
umov s20, v9.s[2]
umov d7, v18.d[1]
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR umov w1, v0.b[16]
// CHECK-ERROR ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR umov w14, v6.h[8]
// CHECK-ERROR ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR umov w20, v9.s[5]
// CHECK-ERROR ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR umov x7, v18.d[3]
// CHECK-ERROR ^
// CHECK-ERROR error: invalid operand for instruction
@@ -4815,7 +4814,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlal s17, h27, s12
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlal d19, s24, d12
// CHECK-ERROR: ^
@@ -4829,7 +4828,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlsl s14, h12, s25
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlsl d12, s23, d13
// CHECK-ERROR: ^
@@ -4843,7 +4842,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmull s12, h22, s12
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmull d15, s22, d12
// CHECK-ERROR: ^
@@ -6885,7 +6884,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: fmul h0, h1, v1.s[0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmul s2, s29, v10.s[4]
// CHECK-ERROR: ^
@@ -6904,7 +6903,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: fmulx h0, h1, v1.d[0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmulx d2, d29, v10.d[3]
// CHECK-ERROR: ^
@@ -6923,7 +6922,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: fmla d30, s11, v1.d[1]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: fmla s16, s22, v16.s[5]
// CHECK-ERROR: ^
@@ -6942,7 +6941,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: fmls h7, h17, v26.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: error: vector lane must be an integer in range [0, 1]
+// CHECK-ERROR: error: vector lane must be an integer in range [0, 1]
// CHECK-ERROR: fmls d16, d22, v16.d[-1]
// CHECK-ERROR: ^
@@ -6964,7 +6963,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlal s8, s9, v14.s[1]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlal d4, s5, v1.s[5]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -6989,7 +6988,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmlsl d1, h1, v13.s[0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmlsl d1, s1, v13.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -7016,7 +7015,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmull s1, s1, v4.s[0]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmull s12, h17, v9.h[9]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -7041,7 +7040,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqdmulh s25, s26, v27.h[3]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqdmulh s25, s26, v27.s[4]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -7066,7 +7065,7 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: sqrdmulh s5, h6, v7.s[2]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: sqrdmulh h31, h30, v14.h[9]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
@@ -7098,16 +7097,16 @@
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: dup d0, v17.s[3]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: dup d0, v17.d[4]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: dup s0, v1.s[7]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: dup h0, v31.h[16]
// CHECK-ERROR: ^
-// CHECK-ARM64-ERROR: vector lane must be an integer in range
+// CHECK-ERROR: vector lane must be an integer in range
// CHECK-ERROR: dup b1, v3.b[16]
// CHECK-ERROR: ^
Modified: llvm/trunk/test/MC/AArch64/neon-facge-facgt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-facge-facgt.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-facge-facgt.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-facge-facgt.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-frsqrt-frecp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-frsqrt-frecp.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-frsqrt-frecp.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-frsqrt-frecp.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-halving-add-sub.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-halving-add-sub.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-halving-add-sub.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-halving-add-sub.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-max-min-pairwise.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-max-min-pairwise.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-max-min-pairwise.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-max-min-pairwise.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-max-min.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-max-min.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-max-min.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-max-min.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-mla-mls-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-mla-mls-instructions.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-mla-mls-instructions.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-mla-mls-instructions.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-mov.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-mov.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-mov.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-mov.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-mul-div-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-mul-div-instructions.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-mul-div-instructions.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-mul-div-instructions.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-rounding-halving-add.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-rounding-halving-add.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-rounding-halving-add.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-rounding-halving-add.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-rounding-shift.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-rounding-shift.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-rounding-shift.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-rounding-shift.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-saturating-add-sub.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-saturating-add-sub.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-saturating-add-sub.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-saturating-add-sub.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-saturating-rounding-shift.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-saturating-rounding-shift.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-saturating-rounding-shift.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-saturating-rounding-shift.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-saturating-shift.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-saturating-shift.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-saturating-shift.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-saturating-shift.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-abs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-abs.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-abs.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-abs.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-add-sub.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-add-sub.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-add-sub.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-add-sub.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//------------------------------------------------------------------------------
// Scalar Integer Add
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-mla.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-mla.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-mla.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-mla.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//------------------------------------------------------------------------------
// Floating Point fused multiply-add (scalar, by element)
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-mul.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-mul.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-mul.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-mul.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//------------------------------------------------------------------------------
// Floating Point multiply (scalar, by element)
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//-----------------------------------------------------------------------------
// Signed saturating doubling multiply-add long (scalar, by element)
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//-----------------------------------------------------------------------------
// Signed saturating doubling multiply long (scalar, by element)
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-compare.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-compare.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-compare.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-compare.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-dup.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-dup.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-dup.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-dup.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//------------------------------------------------------------------------------
// Duplicate element (scalar)
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-extract-narrow.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-extract-narrow.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-extract-narrow.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-extract-narrow.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-fp-compare.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-fp-compare.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-fp-compare.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-fp-compare.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-mul.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-mul.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-mul.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-mul.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-neg.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-neg.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-neg.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-neg.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-recip.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-recip.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-recip.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-recip.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-reduce-pairwise.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-reduce-pairwise.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-reduce-pairwise.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-reduce-pairwise.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//----------------------------------------------------------------------
// Scalar Reduce Add Pairwise (Integer)
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-rounding-shift.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-rounding-shift.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-rounding-shift.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-rounding-shift.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//------------------------------------------------------------------------------
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-saturating-add-sub.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-saturating-add-sub.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-saturating-add-sub.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-saturating-add-sub.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//------------------------------------------------------------------------------
// Scalar Integer Saturating Add (Signed)
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//------------------------------------------------------------------------------
// Scalar Integer Saturating Rounding Shift Lef (Signed)
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-saturating-shift.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-saturating-shift.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-saturating-shift.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-saturating-shift.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//------------------------------------------------------------------------------
// Scalar Integer Saturating Shift Lef (Signed)
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-shift-imm.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-shift-imm.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-shift-imm.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-shift-imm.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-shift.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-shift.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-shift.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-shift.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
//------------------------------------------------------------------------------
// Scalar Integer Shift Lef (Signed)
Modified: llvm/trunk/test/MC/AArch64/neon-shift-left-long.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-shift-left-long.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-shift-left-long.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-shift-left-long.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-shift.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-shift.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-shift.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-shift.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-simd-copy.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-simd-copy.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-simd-copy.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-simd-copy.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-simd-shift.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-simd-shift.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-simd-shift.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-simd-shift.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-sxtl.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-sxtl.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-sxtl.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-sxtl.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/neon-uxtl.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-uxtl.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-uxtl.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-uxtl.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
Modified: llvm/trunk/test/MC/AArch64/noneon-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/noneon-diagnostics.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/noneon-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/noneon-diagnostics.s Sat May 24 07:50:23 2014
@@ -1,48 +1,29 @@
-// RUN: not llvm-mc -triple arm64-none-linux-gnu -mattr=-neon < %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-ARM64-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-neon < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
fmla v3.4s, v12.4s, v17.4s
fmla v1.2d, v30.2d, v20.2d
fmla v9.2s, v9.2s, v0.2s
-// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR: error: instruction requires: neon
// CHECK-ERROR-NEXT: fmla v3.4s, v12.4s, v17.4s
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT: error: instruction requires: neon
// CHECK-ERROR-NEXT: fmla v1.2d, v30.2d, v20.2d
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT: error: instruction requires: neon
// CHECK-ERROR-NEXT: fmla v9.2s, v9.2s, v0.2s
// CHECK-ERROR-NEXT: ^
-// CHECK-ARM64-ERROR: error: instruction requires: neon
-// CHECK-ARM64-ERROR-NEXT: fmla v3.4s, v12.4s, v17.4s
-// CHECK-ARM64-ERROR-NEXT: ^
-// CHECK-ARM64-ERROR-NEXT: error: instruction requires: neon
-// CHECK-ARM64-ERROR-NEXT: fmla v1.2d, v30.2d, v20.2d
-// CHECK-ARM64-ERROR-NEXT: ^
-// CHECK-ARM64-ERROR-NEXT: error: instruction requires: neon
-// CHECK-ARM64-ERROR-NEXT: fmla v9.2s, v9.2s, v0.2s
-// CHECK-ARM64-ERROR-NEXT: ^
-
fmls v3.4s, v12.4s, v17.4s
fmls v1.2d, v30.2d, v20.2d
fmls v9.2s, v9.2s, v0.2s
-// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled
+
+// CHECK-ERROR: error: instruction requires: neon
// CHECK-ERROR-NEXT: fmls v3.4s, v12.4s, v17.4s
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT: error: instruction requires: neon
// CHECK-ERROR-NEXT: fmls v1.2d, v30.2d, v20.2d
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT: error: instruction requires: neon
// CHECK-ERROR-NEXT: fmls v9.2s, v9.2s, v0.2s
// CHECK-ERROR-NEXT: ^
-
-// CHECK-ARM64-ERROR: error: instruction requires: neon
-// CHECK-ARM64-ERROR-NEXT: fmls v3.4s, v12.4s, v17.4s
-// CHECK-ARM64-ERROR-NEXT: ^
-// CHECK-ARM64-ERROR-NEXT: error: instruction requires: neon
-// CHECK-ARM64-ERROR-NEXT: fmls v1.2d, v30.2d, v20.2d
-// CHECK-ARM64-ERROR-NEXT: ^
-// CHECK-ARM64-ERROR-NEXT: error: instruction requires: neon
-// CHECK-ARM64-ERROR-NEXT: fmls v9.2s, v9.2s, v0.2s
-// CHECK-ARM64-ERROR-NEXT: ^
Modified: llvm/trunk/test/MC/AArch64/optional-hash.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/optional-hash.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/optional-hash.s (original)
+++ llvm/trunk/test/MC/AArch64/optional-hash.s Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
// PR18929
-// RUN: llvm-mc < %s -triple=arm64-linux-gnueabi -mattr=+fp-armv8,+neon -filetype=obj -o - \
+// RUN: llvm-mc < %s -triple=aarch64-linux-gnueabi -mattr=+fp-armv8,+neon -filetype=obj -o - \
// RUN: | llvm-objdump --disassemble -arch=arm64 -mattr=+fp-armv8,+neon - | FileCheck %s
.text
Modified: llvm/trunk/test/MC/AArch64/tls-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/tls-relocs.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/tls-relocs.s (original)
+++ llvm/trunk/test/MC/AArch64/tls-relocs.s Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -show-encoding < %s | FileCheck %s --check-prefix=CHECK-ARM64
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s -o - | \
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s -o - | \
// RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s
// TLS local-dynamic forms
@@ -8,14 +8,14 @@
movz x3, #:dtprel_g2:var
movn x4, #:dtprel_g2:var
-// CHECK-ARM64: movz x1, #:dtprel_g2:var // encoding: [0bAAA00001,A,0b110AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn x2, #:dtprel_g2:var // encoding: [0bAAA00010,A,0b110AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
+// CHECK: movz x1, #:dtprel_g2:var // encoding: [0bAAA00001,A,0b110AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw
+// CHECK: movn x2, #:dtprel_g2:var // encoding: [0bAAA00010,A,0b110AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw
+// CHECK: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw
+// CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw
// CHECK-ELF: Relocations [
// CHECK-ELF-NEXT: Section (2) .rela.text {
@@ -30,14 +30,14 @@
movz w7, #:dtprel_g1:var
movn w8, #:dtprel_g1:var
-// CHECK-ARM64: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn w8, #:dtprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+// CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
+// CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
+// CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
+// CHECK: movn w8, #:dtprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0x10 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
// CHECK-ELF-NEXT: 0x14 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
@@ -48,10 +48,10 @@
movk x9, #:dtprel_g1_nc:var
movk w10, #:dtprel_g1_nc:var
-// CHECK-ARM64: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movk w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw
+// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0x20 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
// CHECK-ELF-NEXT: 0x24 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
@@ -62,14 +62,14 @@
movz w13, #:dtprel_g0:var
movn w14, #:dtprel_g0:var
-// CHECK-ARM64: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn w14, #:dtprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+// CHECK: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
+// CHECK: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
+// CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
+// CHECK: movn w14, #:dtprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0x28 R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
// CHECK-ELF-NEXT: 0x2C R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
@@ -80,10 +80,10 @@
movk x15, #:dtprel_g0_nc:var
movk w16, #:dtprel_g0_nc:var
-// CHECK-ARM64: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw
+// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
+// CHECK: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0x38 R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
// CHECK-ELF-NEXT: 0x3C R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
@@ -92,10 +92,10 @@
add x17, x18, #:dtprel_hi12:var, lsl #12
add w19, w20, #:dtprel_hi12:var, lsl #12
-// CHECK-ARM64: add x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_arm64_add_imm12
-// CHECK-ARM64: add w19, w20, :dtprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_arm64_add_imm12
+// CHECK: add x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12
+// CHECK: add w19, w20, :dtprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11]
+// CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: 0x40 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]]
// CHECK-ELF-NEXT: 0x44 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]]
@@ -104,10 +104,10 @@
add x21, x22, #:dtprel_lo12:var
add w23, w24, #:dtprel_lo12:var
-// CHECK-ARM64: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_add_imm12
-// CHECK-ARM64: add w23, w24, :dtprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_add_imm12
+// CHECK: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12
+// CHECK: add w23, w24, :dtprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: 0x48 R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0x4C R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]]
@@ -116,10 +116,10 @@
add x25, x26, #:dtprel_lo12_nc:var
add w27, w28, #:dtprel_lo12_nc:var
-// CHECK-ARM64: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_add_imm12
-// CHECK-ARM64: add w27, w28, :dtprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_add_imm12
+// CHECK: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12
+// CHECK: add w27, w28, :dtprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: 0x50 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]]
// CHECK-ELF-NEXT: 0x54 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]]
@@ -128,10 +128,10 @@
ldrb w29, [x30, #:dtprel_lo12:var]
ldrsb x29, [x28, #:dtprel_lo12_nc:var]
-// CHECK-ARM64: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK-ARM64: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1
+// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1
// CHECK-ELF-NEXT: 0x58 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0x5C R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]]
@@ -140,10 +140,10 @@
strh w27, [x26, #:dtprel_lo12:var]
ldrsh x25, [x24, #:dtprel_lo12_nc:var]
-// CHECK-ARM64: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
-// CHECK-ARM64: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2
+// CHECK: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2
// CHECK-ELF-NEXT: 0x60 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0x64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]]
@@ -152,10 +152,10 @@
ldr w23, [x22, #:dtprel_lo12:var]
ldrsw x21, [x20, #:dtprel_lo12_nc:var]
-// CHECK-ARM64: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
-// CHECK-ARM64: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4
+// CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4
// CHECK-ELF-NEXT: 0x68 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0x6C R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]]
@@ -164,10 +164,10 @@
ldr x19, [x18, #:dtprel_lo12:var]
str x17, [x16, #:dtprel_lo12_nc:var]
-// CHECK-ARM64: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK-ARM64: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
+// CHECK: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
+// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8
// CHECK-ELF-NEXT: 0x70 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0x74 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]]
@@ -177,10 +177,10 @@
movz x15, #:gottprel_g1:var
movz w14, #:gottprel_g1:var
-// CHECK-ARM64: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movz w14, #:gottprel_g1:var // encoding: [0bAAA01110,A,0b101AAAAA,0x12]
-// CHECK-ARM64: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_arm64_movw
+// CHECK: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_aarch64_movw
+// CHECK: movz w14, #:gottprel_g1:var // encoding: [0bAAA01110,A,0b101AAAAA,0x12]
+// CHECK: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0x78 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]]
// CHECK-ELF-NEXT: 0x7C R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]]
@@ -189,10 +189,10 @@
movk x13, #:gottprel_g0_nc:var
movk w12, #:gottprel_g0_nc:var
-// CHECK-ARM64: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2]
-// CHECK-ARM64: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movk w12, #:gottprel_g0_nc:var // encoding: [0bAAA01100,A,0b100AAAAA,0x72]
-// CHECK-ARM64: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2]
+// CHECK: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_aarch64_movw
+// CHECK: movk w12, #:gottprel_g0_nc:var // encoding: [0bAAA01100,A,0b100AAAAA,0x72]
+// CHECK: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0x80 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]]
// CHECK-ELF-NEXT: 0x84 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]]
@@ -202,12 +202,12 @@
ldr x10, [x0, #:gottprel_lo12:var]
ldr x9, :gottprel:var
-// CHECK-ARM64: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A']
-// CHECK-ARM64: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_adrp_imm21
-// CHECK-ARM64: ldr x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK-ARM64: ldr x9, :gottprel:var // encoding: [0bAAA01001,A,A,0x58]
-// CHECK-ARM64: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_ldr_pcrel_imm19
+// CHECK: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A']
+// CHECK: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_pcrel_adrp_imm21
+// CHECK: ldr x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9]
+// CHECK: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
+// CHECK: ldr x9, :gottprel:var // encoding: [0bAAA01001,A,A,0x58]
+// CHECK: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_ldr_pcrel_imm19
// CHECK-ELF-NEXT: 0x88 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]]
// CHECK-ELF-NEXT: 0x8C R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]]
@@ -218,10 +218,10 @@
movz x3, #:tprel_g2:var
movn x4, #:tprel_g2:var
-// CHECK-ARM64: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
+// CHECK: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw
+// CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0x94 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
// CHECK-ELF-NEXT: 0x98 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
@@ -232,14 +232,14 @@
movz w7, #:tprel_g1:var
movn w8, #:tprel_g1:var
-// CHECK-ARM64: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn w8, #:tprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+// CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
+// CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
+// CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
+// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
+// CHECK: movn w8, #:tprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12]
+// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0x9C R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
// CHECK-ELF-NEXT: 0xA0 R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
@@ -250,10 +250,10 @@
movk x9, #:tprel_g1_nc:var
movk w10, #:tprel_g1_nc:var
-// CHECK-ARM64: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movk w10, #:tprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
+// CHECK: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw
+// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
+// CHECK: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0xAC R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
// CHECK-ELF-NEXT: 0xB0 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
@@ -264,14 +264,14 @@
movz w13, #:tprel_g0:var
movn w14, #:tprel_g0:var
-// CHECK-ARM64: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movn w14, #:tprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+// CHECK: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
+// CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
+// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
+// CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
+// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
+// CHECK: movn w14, #:tprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12]
+// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0xB4 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
// CHECK-ELF-NEXT: 0xB8 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
@@ -282,10 +282,10 @@
movk x15, #:tprel_g0_nc:var
movk w16, #:tprel_g0_nc:var
-// CHECK-ARM64: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
-// CHECK-ARM64: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
+// CHECK: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw
+// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
+// CHECK: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw
// CHECK-ELF-NEXT: 0xC4 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
// CHECK-ELF-NEXT: 0xC8 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
@@ -294,10 +294,10 @@
add x17, x18, #:tprel_hi12:var, lsl #12
add w19, w20, #:tprel_hi12:var, lsl #12
-// CHECK-ARM64: add x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_arm64_add_imm12
-// CHECK-ARM64: add w19, w20, :tprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_arm64_add_imm12
+// CHECK: add x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12
+// CHECK: add w19, w20, :tprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11]
+// CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: 0xCC R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]]
// CHECK-ELF-NEXT: 0xD0 R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]]
@@ -306,10 +306,10 @@
add x21, x22, #:tprel_lo12:var
add w23, w24, #:tprel_lo12:var
-// CHECK-ARM64: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_add_imm12
-// CHECK-ARM64: add w23, w24, :tprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_add_imm12
+// CHECK: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12
+// CHECK: add w23, w24, :tprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: 0xD4 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0xD8 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]]
@@ -318,10 +318,10 @@
add x25, x26, #:tprel_lo12_nc:var
add w27, w28, #:tprel_lo12_nc:var
-// CHECK-ARM64: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_add_imm12
-// CHECK-ARM64: add w27, w28, :tprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_add_imm12
+// CHECK: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12
+// CHECK: add w27, w28, :tprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12
// CHECK-ELF-NEXT: 0xDC R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]]
// CHECK-ELF-NEXT: 0xE0 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]]
@@ -330,10 +330,10 @@
ldrb w29, [x30, #:tprel_lo12:var]
ldrsb x29, [x28, #:tprel_lo12_nc:var]
-// CHECK-ARM64: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK-ARM64: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1
+// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1
// CHECK-ELF-NEXT: 0xE4 R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0xE8 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]]
@@ -342,10 +342,10 @@
strh w27, [x26, #:tprel_lo12:var]
ldrsh x25, [x24, #:tprel_lo12_nc:var]
-// CHECK-ARM64: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
-// CHECK-ARM64: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2
+// CHECK: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2
// CHECK-ELF-NEXT: 0xEC R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0xF0 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]]
@@ -354,10 +354,10 @@
ldr w23, [x22, #:tprel_lo12:var]
ldrsw x21, [x20, #:tprel_lo12_nc:var]
-// CHECK-ARM64: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
-// CHECK-ARM64: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4
+// CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4
// CHECK-ELF-NEXT: 0xF4 R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0xF8 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]]
@@ -365,10 +365,10 @@
ldr x19, [x18, #:tprel_lo12:var]
str x17, [x16, #:tprel_lo12_nc:var]
-// CHECK-ARM64: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK-ARM64: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
+// CHECK: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
+// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8
// CHECK-ELF-NEXT: 0xFC R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]]
// CHECK-ELF-NEXT: 0x100 R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]]
@@ -381,15 +381,15 @@
blr x3
-// CHECK-ARM64: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A']
-// CHECK-ARM64: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_arm64_pcrel_adrp_imm21
-// CHECK-ARM64: ldr x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK-ARM64: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
-// CHECK-ARM64: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_add_imm12
-// CHECK-ARM64: .tlsdesccall var // encoding: []
-// CHECK-ARM64: // fixup A - offset: 0, value: var, kind: fixup_arm64_tlsdesc_call
-// CHECK-ARM64: blr x3 // encoding: [0x60,0x00,0x3f,0xd6]
+// CHECK: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A']
+// CHECK: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_aarch64_pcrel_adrp_imm21
+// CHECK: ldr x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9]
+// CHECK: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
+// CHECK: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
+// CHECK: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12
+// CHECK: .tlsdesccall var // encoding: []
+// CHECK: // fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call
+// CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6]
// CHECK-ELF-NEXT: 0x104 R_AARCH64_TLSDESC_ADR_PAGE [[VARSYM]]
// CHECK-ELF-NEXT: 0x108 R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]]
Modified: llvm/trunk/test/MC/AArch64/trace-regs-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/trace-regs-diagnostics.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/trace-regs-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/trace-regs-diagnostics.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple arm64-none-linux-gnu < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
// Write-only
mrs x12, trcoslar
mrs x10, trclar
Modified: llvm/trunk/test/MC/AArch64/trace-regs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/trace-regs.s?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/trace-regs.s (original)
+++ llvm/trunk/test/MC/AArch64/trace-regs.s Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
mrs x8, trcstatr
mrs x9, trcidr8
Removed: llvm/trunk/test/MC/ARM64/adr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/adr.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/adr.s (original)
+++ llvm/trunk/test/MC/ARM64/adr.s (removed)
@@ -1,31 +0,0 @@
-// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s
-// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-adr x0, #0
-adr x0, #1
-adr x0, 1f
-adr x0, foo
-// CHECK: adr x0, #0 // encoding: [0x00,0x00,0x00,0x10]
-// CHECK: adr x0, #1 // encoding: [0x00,0x00,0x00,0x30]
-// CHECK: adr x0, .Ltmp0 // encoding: [A,A,A,0x10'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm64_pcrel_adr_imm21
-// CHECK: adr x0, foo // encoding: [A,A,A,0x10'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_arm64_pcrel_adr_imm21
-
-adrp x0, #0
-adrp x0, #4096
-adrp x0, 1f
-adrp x0, foo
-// CHECK: adrp x0, #0 // encoding: [0x00,0x00,0x00,0x90]
-// CHECK: adrp x0, #4096 // encoding: [0x00,0x00,0x00,0xb0]
-// CHECK: adrp x0, .Ltmp0 // encoding: [A,A,A,0x90'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm64_pcrel_adrp_imm21
-// CHECK: adrp x0, foo // encoding: [A,A,A,0x90'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_arm64_pcrel_adrp_imm21
-
-adr x0, #0xffffffff
-adrp x0, #0xffffffff
-adrp x0, #1
-// CHECK-ERRORS: error: expected label or encodable integer pc offset
-// CHECK-ERRORS: error: expected label or encodable integer pc offset
-// CHECK-ERRORS: error: expected label or encodable integer pc offset
Removed: llvm/trunk/test/MC/ARM64/advsimd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/advsimd.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/advsimd.s (original)
+++ llvm/trunk/test/MC/ARM64/advsimd.s (removed)
@@ -1,1997 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 -show-encoding < %s | FileCheck %s
-
-foo:
-
- abs.8b v0, v0
- abs.16b v0, v0
- abs.4h v0, v0
- abs.8h v0, v0
- abs.2s v0, v0
- abs.4s v0, v0
-
-; CHECK: abs.8b v0, v0 ; encoding: [0x00,0xb8,0x20,0x0e]
-; CHECK: abs.16b v0, v0 ; encoding: [0x00,0xb8,0x20,0x4e]
-; CHECK: abs.4h v0, v0 ; encoding: [0x00,0xb8,0x60,0x0e]
-; CHECK: abs.8h v0, v0 ; encoding: [0x00,0xb8,0x60,0x4e]
-; CHECK: abs.2s v0, v0 ; encoding: [0x00,0xb8,0xa0,0x0e]
-; CHECK: abs.4s v0, v0 ; encoding: [0x00,0xb8,0xa0,0x4e]
-
- add.8b v0, v0, v0
- add.16b v0, v0, v0
- add.4h v0, v0, v0
- add.8h v0, v0, v0
- add.2s v0, v0, v0
- add.4s v0, v0, v0
- add.2d v0, v0, v0
-
-; CHECK: add.8b v0, v0, v0 ; encoding: [0x00,0x84,0x20,0x0e]
-; CHECK: add.16b v0, v0, v0 ; encoding: [0x00,0x84,0x20,0x4e]
-; CHECK: add.4h v0, v0, v0 ; encoding: [0x00,0x84,0x60,0x0e]
-; CHECK: add.8h v0, v0, v0 ; encoding: [0x00,0x84,0x60,0x4e]
-; CHECK: add.2s v0, v0, v0 ; encoding: [0x00,0x84,0xa0,0x0e]
-; CHECK: add.4s v0, v0, v0 ; encoding: [0x00,0x84,0xa0,0x4e]
-; CHECK: add.2d v0, v0, v0 ; encoding: [0x00,0x84,0xe0,0x4e]
-
- add d1, d2, d3
-
-; CHECK: add d1, d2, d3 ; encoding: [0x41,0x84,0xe3,0x5e]
-
- addhn.8b v0, v0, v0
- addhn2.16b v0, v0, v0
- addhn.4h v0, v0, v0
- addhn2.8h v0, v0, v0
- addhn.2s v0, v0, v0
- addhn2.4s v0, v0, v0
-
-; CHECK: addhn.8b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x0e]
-; CHECK: addhn2.16b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x4e]
-; CHECK: addhn.4h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x0e]
-; CHECK: addhn2.8h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x4e]
-; CHECK: addhn.2s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x0e]
-; CHECK: addhn2.4s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x4e]
-
- addp.8b v0, v0, v0
- addp.16b v0, v0, v0
- addp.4h v0, v0, v0
- addp.8h v0, v0, v0
- addp.2s v0, v0, v0
- addp.4s v0, v0, v0
- addp.2d v0, v0, v0
-
-; CHECK: addp.8b v0, v0, v0 ; encoding: [0x00,0xbc,0x20,0x0e]
-; CHECK: addp.16b v0, v0, v0 ; encoding: [0x00,0xbc,0x20,0x4e]
-; CHECK: addp.4h v0, v0, v0 ; encoding: [0x00,0xbc,0x60,0x0e]
-; CHECK: addp.8h v0, v0, v0 ; encoding: [0x00,0xbc,0x60,0x4e]
-; CHECK: addp.2s v0, v0, v0 ; encoding: [0x00,0xbc,0xa0,0x0e]
-; CHECK: addp.4s v0, v0, v0 ; encoding: [0x00,0xbc,0xa0,0x4e]
-; CHECK: addp.2d v0, v0, v0 ; encoding: [0x00,0xbc,0xe0,0x4e]
-
- addp.2d d0, v0
-
-; CHECK: addp.2d d0, v0 ; encoding: [0x00,0xb8,0xf1,0x5e]
-
- addv.8b b0, v0
- addv.16b b0, v0
- addv.4h h0, v0
- addv.8h h0, v0
- addv.4s s0, v0
-
-; CHECK: addv.8b b0, v0 ; encoding: [0x00,0xb8,0x31,0x0e]
-; CHECK: addv.16b b0, v0 ; encoding: [0x00,0xb8,0x31,0x4e]
-; CHECK: addv.4h h0, v0 ; encoding: [0x00,0xb8,0x71,0x0e]
-; CHECK: addv.8h h0, v0 ; encoding: [0x00,0xb8,0x71,0x4e]
-; CHECK: addv.4s s0, v0 ; encoding: [0x00,0xb8,0xb1,0x4e]
-
-
-; INS/DUP
- dup.2d v0, x3
- dup.4s v0, w3
- dup.2s v0, w3
- dup.8h v0, w3
- dup.4h v0, w3
- dup.16b v0, w3
- dup.8b v0, w3
-
- dup v1.2d, x3
- dup v2.4s, w4
- dup v3.2s, w5
- dup v4.8h, w6
- dup v5.4h, w7
- dup v6.16b, w8
- dup v7.8b, w9
-
-; CHECK: dup.2d v0, x3 ; encoding: [0x60,0x0c,0x08,0x4e]
-; CHECK: dup.4s v0, w3 ; encoding: [0x60,0x0c,0x04,0x4e]
-; CHECK: dup.2s v0, w3 ; encoding: [0x60,0x0c,0x04,0x0e]
-; CHECK: dup.8h v0, w3 ; encoding: [0x60,0x0c,0x02,0x4e]
-; CHECK: dup.4h v0, w3 ; encoding: [0x60,0x0c,0x02,0x0e]
-; CHECK: dup.16b v0, w3 ; encoding: [0x60,0x0c,0x01,0x4e]
-; CHECK: dup.8b v0, w3 ; encoding: [0x60,0x0c,0x01,0x0e]
-
-; CHECK: dup.2d v1, x3 ; encoding: [0x61,0x0c,0x08,0x4e]
-; CHECK: dup.4s v2, w4 ; encoding: [0x82,0x0c,0x04,0x4e]
-; CHECK: dup.2s v3, w5 ; encoding: [0xa3,0x0c,0x04,0x0e]
-; CHECK: dup.8h v4, w6 ; encoding: [0xc4,0x0c,0x02,0x4e]
-; CHECK: dup.4h v5, w7 ; encoding: [0xe5,0x0c,0x02,0x0e]
-; CHECK: dup.16b v6, w8 ; encoding: [0x06,0x0d,0x01,0x4e]
-; CHECK: dup.8b v7, w9 ; encoding: [0x27,0x0d,0x01,0x0e]
-
- dup.2d v0, v3[1]
- dup.2s v0, v3[1]
- dup.4s v0, v3[1]
- dup.4h v0, v3[1]
- dup.8h v0, v3[1]
- dup.8b v0, v3[1]
- dup.16b v0, v3[1]
-
- dup v7.2d, v9.d[1]
- dup v6.2s, v8.s[1]
- dup v5.4s, v7.s[2]
- dup v4.4h, v6.h[3]
- dup v3.8h, v5.h[4]
- dup v2.8b, v4.b[5]
- dup v1.16b, v3.b[6]
-
-; CHECK: dup.2d v0, v3[1] ; encoding: [0x60,0x04,0x18,0x4e]
-; CHECK: dup.2s v0, v3[1] ; encoding: [0x60,0x04,0x0c,0x0e]
-; CHECK: dup.4s v0, v3[1] ; encoding: [0x60,0x04,0x0c,0x4e]
-; CHECK: dup.4h v0, v3[1] ; encoding: [0x60,0x04,0x06,0x0e]
-; CHECK: dup.8h v0, v3[1] ; encoding: [0x60,0x04,0x06,0x4e]
-; CHECK: dup.8b v0, v3[1] ; encoding: [0x60,0x04,0x03,0x0e]
-; CHECK: dup.16b v0, v3[1] ; encoding: [0x60,0x04,0x03,0x4e]
-
-; CHECK: dup.2d v7, v9[1] ; encoding: [0x27,0x05,0x18,0x4e]
-; CHECK: dup.2s v6, v8[1] ; encoding: [0x06,0x05,0x0c,0x0e]
-; CHECK: dup.4s v5, v7[2] ; encoding: [0xe5,0x04,0x14,0x4e]
-; CHECK: dup.4h v4, v6[3] ; encoding: [0xc4,0x04,0x0e,0x0e]
-; CHECK: dup.8h v3, v5[4] ; encoding: [0xa3,0x04,0x12,0x4e]
-; CHECK: dup.8b v2, v4[5] ; encoding: [0x82,0x04,0x0b,0x0e]
-; CHECK: dup.16b v1, v3[6] ; encoding: [0x61,0x04,0x0d,0x4e]
-
- dup b3, v4[1]
- dup h3, v4[1]
- dup s3, v4[1]
- dup d3, v4[1]
- dup b3, v4.b[1]
- dup h3, v4.h[1]
- dup s3, v4.s[1]
- dup d3, v4.d[1]
-
- mov b3, v4[1]
- mov h3, v4[1]
- mov s3, v4[1]
- mov d3, v4[1]
- mov b3, v4.b[1]
- mov h3, v4.h[1]
- mov s3, v4.s[1]
- mov d3, v4.d[1]
-
-; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e]
-; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e]
-; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e]
-; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e]
-; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e]
-; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e]
-; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e]
-; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e]
-
-; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e]
-; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e]
-; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e]
-; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e]
-; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e]
-; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e]
-; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e]
-; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e]
-
- smov.s x3, v2[2]
- smov x3, v2.s[2]
- umov.s w3, v2[2]
- umov w3, v2.s[2]
- umov.d x3, v2[1]
- umov x3, v2.d[1]
-
-; CHECK: smov.s x3, v2[2] ; encoding: [0x43,0x2c,0x14,0x4e]
-; CHECK: smov.s x3, v2[2] ; encoding: [0x43,0x2c,0x14,0x4e]
-; CHECK: mov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e]
-; CHECK: mov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e]
-; CHECK: mov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e]
-; CHECK: mov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e]
-
- ; MOV aliases for UMOV instructions above
-
- mov.s w2, v3[3]
- mov w5, v7.s[2]
- mov.d x11, v13[1]
- mov x17, v19.d[0]
-
-; CHECK: mov.s w2, v3[3] ; encoding: [0x62,0x3c,0x1c,0x0e]
-; CHECK: mov.s w5, v7[2] ; encoding: [0xe5,0x3c,0x14,0x0e]
-; CHECK: mov.d x11, v13[1] ; encoding: [0xab,0x3d,0x18,0x4e]
-; CHECK: mov.d x17, v19[0] ; encoding: [0x71,0x3e,0x08,0x4e]
-
- ins.d v2[1], x5
- ins.s v2[1], w5
- ins.h v2[1], w5
- ins.b v2[1], w5
-
- ins v2.d[1], x5
- ins v2.s[1], w5
- ins v2.h[1], w5
- ins v2.b[1], w5
-
-; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
-; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]
-; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]
-; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]
-
-; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
-; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]
-; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]
-; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]
-
- ins.d v2[1], v15[1]
- ins.s v2[1], v15[1]
- ins.h v2[1], v15[1]
- ins.b v2[1], v15[1]
-
- ins v2.d[1], v15.d[0]
- ins v2.s[3], v15.s[2]
- ins v2.h[7], v15.h[3]
- ins v2.b[10], v15.b[5]
-
-; CHECK: ins.d v2[1], v15[1] ; encoding: [0xe2,0x45,0x18,0x6e]
-; CHECK: ins.s v2[1], v15[1] ; encoding: [0xe2,0x25,0x0c,0x6e]
-; CHECK: ins.h v2[1], v15[1] ; encoding: [0xe2,0x15,0x06,0x6e]
-; CHECK: ins.b v2[1], v15[1] ; encoding: [0xe2,0x0d,0x03,0x6e]
-
-; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]
-; CHECK: ins.s v2[3], v15[2] ; encoding: [0xe2,0x45,0x1c,0x6e]
-; CHECK: ins.h v2[7], v15[3] ; encoding: [0xe2,0x35,0x1e,0x6e]
-; CHECK: ins.b v2[10], v15[5] ; encoding: [0xe2,0x2d,0x15,0x6e]
-
-; MOV aliases for the above INS instructions.
- mov.d v2[1], x5
- mov.s v3[1], w6
- mov.h v4[1], w7
- mov.b v5[1], w8
-
- mov v9.d[1], x2
- mov v8.s[1], w3
- mov v7.h[1], w4
- mov v6.b[1], w5
-
- mov.d v1[1], v10[1]
- mov.s v2[1], v11[1]
- mov.h v7[1], v12[1]
- mov.b v8[1], v15[1]
-
- mov v2.d[1], v15.d[0]
- mov v7.s[3], v16.s[2]
- mov v8.h[7], v17.h[3]
- mov v9.b[10], v18.b[5]
-
-; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
-; CHECK: ins.s v3[1], w6 ; encoding: [0xc3,0x1c,0x0c,0x4e]
-; CHECK: ins.h v4[1], w7 ; encoding: [0xe4,0x1c,0x06,0x4e]
-; CHECK: ins.b v5[1], w8 ; encoding: [0x05,0x1d,0x03,0x4e]
-; CHECK: ins.d v9[1], x2 ; encoding: [0x49,0x1c,0x18,0x4e]
-; CHECK: ins.s v8[1], w3 ; encoding: [0x68,0x1c,0x0c,0x4e]
-; CHECK: ins.h v7[1], w4 ; encoding: [0x87,0x1c,0x06,0x4e]
-; CHECK: ins.b v6[1], w5 ; encoding: [0xa6,0x1c,0x03,0x4e]
-; CHECK: ins.d v1[1], v10[1] ; encoding: [0x41,0x45,0x18,0x6e]
-; CHECK: ins.s v2[1], v11[1] ; encoding: [0x62,0x25,0x0c,0x6e]
-; CHECK: ins.h v7[1], v12[1] ; encoding: [0x87,0x15,0x06,0x6e]
-; CHECK: ins.b v8[1], v15[1] ; encoding: [0xe8,0x0d,0x03,0x6e]
-; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]
-; CHECK: ins.s v7[3], v16[2] ; encoding: [0x07,0x46,0x1c,0x6e]
-; CHECK: ins.h v8[7], v17[3] ; encoding: [0x28,0x36,0x1e,0x6e]
-; CHECK: ins.b v9[10], v18[5] ; encoding: [0x49,0x2e,0x15,0x6e]
-
-
- and.8b v0, v0, v0
- and.16b v0, v0, v0
-
-; CHECK: and.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x0e]
-; CHECK: and.16b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x4e]
-
- bic.8b v0, v0, v0
-
-; CHECK: bic.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x60,0x0e]
-
- cmeq.8b v0, v0, v0
- cmge.8b v0, v0, v0
- cmgt.8b v0, v0, v0
- cmhi.8b v0, v0, v0
- cmhs.8b v0, v0, v0
- cmtst.8b v0, v0, v0
- fabd.2s v0, v0, v0
- facge.2s v0, v0, v0
- facgt.2s v0, v0, v0
- faddp.2s v0, v0, v0
- fadd.2s v0, v0, v0
- fcmeq.2s v0, v0, v0
- fcmge.2s v0, v0, v0
- fcmgt.2s v0, v0, v0
- fdiv.2s v0, v0, v0
- fmaxnmp.2s v0, v0, v0
- fmaxnm.2s v0, v0, v0
- fmaxp.2s v0, v0, v0
- fmax.2s v0, v0, v0
- fminnmp.2s v0, v0, v0
- fminnm.2s v0, v0, v0
- fminp.2s v0, v0, v0
- fmin.2s v0, v0, v0
- fmla.2s v0, v0, v0
- fmls.2s v0, v0, v0
- fmulx.2s v0, v0, v0
- fmul.2s v0, v0, v0
- fmulx d2, d3, d1
- fmulx s2, s3, s1
- frecps.2s v0, v0, v0
- frsqrts.2s v0, v0, v0
- fsub.2s v0, v0, v0
- mla.8b v0, v0, v0
- mls.8b v0, v0, v0
- mul.8b v0, v0, v0
- pmul.8b v0, v0, v0
- saba.8b v0, v0, v0
- sabd.8b v0, v0, v0
- shadd.8b v0, v0, v0
- shsub.8b v0, v0, v0
- smaxp.8b v0, v0, v0
- smax.8b v0, v0, v0
- sminp.8b v0, v0, v0
- smin.8b v0, v0, v0
- sqadd.8b v0, v0, v0
- sqdmulh.4h v0, v0, v0
- sqrdmulh.4h v0, v0, v0
- sqrshl.8b v0, v0, v0
- sqshl.8b v0, v0, v0
- sqsub.8b v0, v0, v0
- srhadd.8b v0, v0, v0
- srshl.8b v0, v0, v0
- sshl.8b v0, v0, v0
- sub.8b v0, v0, v0
- uaba.8b v0, v0, v0
- uabd.8b v0, v0, v0
- uhadd.8b v0, v0, v0
- uhsub.8b v0, v0, v0
- umaxp.8b v0, v0, v0
- umax.8b v0, v0, v0
- uminp.8b v0, v0, v0
- umin.8b v0, v0, v0
- uqadd.8b v0, v0, v0
- uqrshl.8b v0, v0, v0
- uqshl.8b v0, v0, v0
- uqsub.8b v0, v0, v0
- urhadd.8b v0, v0, v0
- urshl.8b v0, v0, v0
- ushl.8b v0, v0, v0
-
-; CHECK: cmeq.8b v0, v0, v0 ; encoding: [0x00,0x8c,0x20,0x2e]
-; CHECK: cmge.8b v0, v0, v0 ; encoding: [0x00,0x3c,0x20,0x0e]
-; CHECK: cmgt.8b v0, v0, v0 ; encoding: [0x00,0x34,0x20,0x0e]
-; CHECK: cmhi.8b v0, v0, v0 ; encoding: [0x00,0x34,0x20,0x2e]
-; CHECK: cmhs.8b v0, v0, v0 ; encoding: [0x00,0x3c,0x20,0x2e]
-; CHECK: cmtst.8b v0, v0, v0 ; encoding: [0x00,0x8c,0x20,0x0e]
-; CHECK: fabd.2s v0, v0, v0 ; encoding: [0x00,0xd4,0xa0,0x2e]
-; CHECK: facge.2s v0, v0, v0 ; encoding: [0x00,0xec,0x20,0x2e]
-; CHECK: facgt.2s v0, v0, v0 ; encoding: [0x00,0xec,0xa0,0x2e]
-; CHECK: faddp.2s v0, v0, v0 ; encoding: [0x00,0xd4,0x20,0x2e]
-; CHECK: fadd.2s v0, v0, v0 ; encoding: [0x00,0xd4,0x20,0x0e]
-; CHECK: fcmeq.2s v0, v0, v0 ; encoding: [0x00,0xe4,0x20,0x0e]
-; CHECK: fcmge.2s v0, v0, v0 ; encoding: [0x00,0xe4,0x20,0x2e]
-; CHECK: fcmgt.2s v0, v0, v0 ; encoding: [0x00,0xe4,0xa0,0x2e]
-; CHECK: fdiv.2s v0, v0, v0 ; encoding: [0x00,0xfc,0x20,0x2e]
-; CHECK: fmaxnmp.2s v0, v0, v0 ; encoding: [0x00,0xc4,0x20,0x2e]
-; CHECK: fmaxnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0x20,0x0e]
-; CHECK: fmaxp.2s v0, v0, v0 ; encoding: [0x00,0xf4,0x20,0x2e]
-; CHECK: fmax.2s v0, v0, v0 ; encoding: [0x00,0xf4,0x20,0x0e]
-; CHECK: fminnmp.2s v0, v0, v0 ; encoding: [0x00,0xc4,0xa0,0x2e]
-; CHECK: fminnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0xa0,0x0e]
-; CHECK: fminp.2s v0, v0, v0 ; encoding: [0x00,0xf4,0xa0,0x2e]
-; CHECK: fmin.2s v0, v0, v0 ; encoding: [0x00,0xf4,0xa0,0x0e]
-; CHECK: fmla.2s v0, v0, v0 ; encoding: [0x00,0xcc,0x20,0x0e]
-; CHECK: fmls.2s v0, v0, v0 ; encoding: [0x00,0xcc,0xa0,0x0e]
-; CHECK: fmulx.2s v0, v0, v0 ; encoding: [0x00,0xdc,0x20,0x0e]
-
-; CHECK: fmul.2s v0, v0, v0 ; encoding: [0x00,0xdc,0x20,0x2e]
-; CHECK: fmulx d2, d3, d1 ; encoding: [0x62,0xdc,0x61,0x5e]
-; CHECK: fmulx s2, s3, s1 ; encoding: [0x62,0xdc,0x21,0x5e]
-; CHECK: frecps.2s v0, v0, v0 ; encoding: [0x00,0xfc,0x20,0x0e]
-; CHECK: frsqrts.2s v0, v0, v0 ; encoding: [0x00,0xfc,0xa0,0x0e]
-; CHECK: fsub.2s v0, v0, v0 ; encoding: [0x00,0xd4,0xa0,0x0e]
-; CHECK: mla.8b v0, v0, v0 ; encoding: [0x00,0x94,0x20,0x0e]
-; CHECK: mls.8b v0, v0, v0 ; encoding: [0x00,0x94,0x20,0x2e]
-; CHECK: mul.8b v0, v0, v0 ; encoding: [0x00,0x9c,0x20,0x0e]
-; CHECK: pmul.8b v0, v0, v0 ; encoding: [0x00,0x9c,0x20,0x2e]
-; CHECK: saba.8b v0, v0, v0 ; encoding: [0x00,0x7c,0x20,0x0e]
-; CHECK: sabd.8b v0, v0, v0 ; encoding: [0x00,0x74,0x20,0x0e]
-; CHECK: shadd.8b v0, v0, v0 ; encoding: [0x00,0x04,0x20,0x0e]
-; CHECK: shsub.8b v0, v0, v0 ; encoding: [0x00,0x24,0x20,0x0e]
-; CHECK: smaxp.8b v0, v0, v0 ; encoding: [0x00,0xa4,0x20,0x0e]
-; CHECK: smax.8b v0, v0, v0 ; encoding: [0x00,0x64,0x20,0x0e]
-; CHECK: sminp.8b v0, v0, v0 ; encoding: [0x00,0xac,0x20,0x0e]
-; CHECK: smin.8b v0, v0, v0 ; encoding: [0x00,0x6c,0x20,0x0e]
-; CHECK: sqadd.8b v0, v0, v0 ; encoding: [0x00,0x0c,0x20,0x0e]
-; CHECK: sqdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x0e]
-; CHECK: sqrdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x2e]
-; CHECK: sqrshl.8b v0, v0, v0 ; encoding: [0x00,0x5c,0x20,0x0e]
-; CHECK: sqshl.8b v0, v0, v0 ; encoding: [0x00,0x4c,0x20,0x0e]
-; CHECK: sqsub.8b v0, v0, v0 ; encoding: [0x00,0x2c,0x20,0x0e]
-; CHECK: srhadd.8b v0, v0, v0 ; encoding: [0x00,0x14,0x20,0x0e]
-; CHECK: srshl.8b v0, v0, v0 ; encoding: [0x00,0x54,0x20,0x0e]
-; CHECK: sshl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x0e]
-; CHECK: sub.8b v0, v0, v0 ; encoding: [0x00,0x84,0x20,0x2e]
-; CHECK: uaba.8b v0, v0, v0 ; encoding: [0x00,0x7c,0x20,0x2e]
-; CHECK: uabd.8b v0, v0, v0 ; encoding: [0x00,0x74,0x20,0x2e]
-; CHECK: uhadd.8b v0, v0, v0 ; encoding: [0x00,0x04,0x20,0x2e]
-; CHECK: uhsub.8b v0, v0, v0 ; encoding: [0x00,0x24,0x20,0x2e]
-; CHECK: umaxp.8b v0, v0, v0 ; encoding: [0x00,0xa4,0x20,0x2e]
-; CHECK: umax.8b v0, v0, v0 ; encoding: [0x00,0x64,0x20,0x2e]
-; CHECK: uminp.8b v0, v0, v0 ; encoding: [0x00,0xac,0x20,0x2e]
-; CHECK: umin.8b v0, v0, v0 ; encoding: [0x00,0x6c,0x20,0x2e]
-; CHECK: uqadd.8b v0, v0, v0 ; encoding: [0x00,0x0c,0x20,0x2e]
-; CHECK: uqrshl.8b v0, v0, v0 ; encoding: [0x00,0x5c,0x20,0x2e]
-; CHECK: uqshl.8b v0, v0, v0 ; encoding: [0x00,0x4c,0x20,0x2e]
-; CHECK: uqsub.8b v0, v0, v0 ; encoding: [0x00,0x2c,0x20,0x2e]
-; CHECK: urhadd.8b v0, v0, v0 ; encoding: [0x00,0x14,0x20,0x2e]
-; CHECK: urshl.8b v0, v0, v0 ; encoding: [0x00,0x54,0x20,0x2e]
-; CHECK: ushl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x2e]
-
- bif.8b v0, v0, v0
- bit.8b v0, v0, v0
- bsl.8b v0, v0, v0
- eor.8b v0, v0, v0
- orn.8b v0, v0, v0
- orr.8b v0, v0, v1
-
-; CHECK: bif.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xe0,0x2e]
-; CHECK: bit.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x2e]
-; CHECK: bsl.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x60,0x2e]
-; CHECK: eor.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x2e]
-; CHECK: orn.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xe0,0x0e]
-; CHECK: orr.8b v0, v0, v1 ; encoding: [0x00,0x1c,0xa1,0x0e]
-
- sadalp.4h v0, v0
- sadalp.8h v0, v0
- sadalp.2s v0, v0
- sadalp.4s v0, v0
- sadalp.1d v0, v0
- sadalp.2d v0, v0
-
-; CHECK: sadalp.4h v0, v0 ; encoding: [0x00,0x68,0x20,0x0e]
-; CHECK: sadalp.8h v0, v0 ; encoding: [0x00,0x68,0x20,0x4e]
-; CHECK: sadalp.2s v0, v0 ; encoding: [0x00,0x68,0x60,0x0e]
-; CHECK: sadalp.4s v0, v0 ; encoding: [0x00,0x68,0x60,0x4e]
-; CHECK: sadalp.1d v0, v0 ; encoding: [0x00,0x68,0xa0,0x0e]
-; CHECK: sadalp.2d v0, v0 ; encoding: [0x00,0x68,0xa0,0x4e]
-
- cls.8b v0, v0
- clz.8b v0, v0
- cnt.8b v0, v0
- fabs.2s v0, v0
- fneg.2s v0, v0
- frecpe.2s v0, v0
- frinta.2s v0, v0
- frintx.2s v0, v0
- frinti.2s v0, v0
- frintm.2s v0, v0
- frintn.2s v0, v0
- frintp.2s v0, v0
- frintz.2s v0, v0
- frsqrte.2s v0, v0
- fsqrt.2s v0, v0
- neg.8b v0, v0
- not.8b v0, v0
- rbit.8b v0, v0
- rev16.8b v0, v0
- rev32.8b v0, v0
- rev64.8b v0, v0
- sadalp.4h v0, v0
- saddlp.4h v0, v0
- scvtf.2s v0, v0
- sqabs.8b v0, v0
- sqneg.8b v0, v0
- sqxtn.8b v0, v0
- sqxtun.8b v0, v0
- suqadd.8b v0, v0
- uadalp.4h v0, v0
- uaddlp.4h v0, v0
- ucvtf.2s v0, v0
- uqxtn.8b v0, v0
- urecpe.2s v0, v0
- ursqrte.2s v0, v0
- usqadd.8b v0, v0
- xtn.8b v0, v0
- shll.8h v1, v2, #8
- shll.4s v3, v4, #16
- shll.2d v5, v6, #32
- shll2.8h v7, v8, #8
- shll2.4s v9, v10, #16
- shll2.2d v11, v12, #32
- shll v1.8h, v2.8b, #8
- shll v1.4s, v2.4h, #16
- shll v1.2d, v2.2s, #32
- shll2 v1.8h, v2.16b, #8
- shll2 v1.4s, v2.8h, #16
- shll2 v1.2d, v2.4s, #32
-
-; CHECK: cls.8b v0, v0 ; encoding: [0x00,0x48,0x20,0x0e]
-; CHECK: clz.8b v0, v0 ; encoding: [0x00,0x48,0x20,0x2e]
-; CHECK: cnt.8b v0, v0 ; encoding: [0x00,0x58,0x20,0x0e]
-; CHECK: fabs.2s v0, v0 ; encoding: [0x00,0xf8,0xa0,0x0e]
-; CHECK: fneg.2s v0, v0 ; encoding: [0x00,0xf8,0xa0,0x2e]
-; CHECK: frecpe.2s v0, v0 ; encoding: [0x00,0xd8,0xa1,0x0e]
-; CHECK: frinta.2s v0, v0 ; encoding: [0x00,0x88,0x21,0x2e]
-; CHECK: frintx.2s v0, v0 ; encoding: [0x00,0x98,0x21,0x2e]
-; CHECK: frinti.2s v0, v0 ; encoding: [0x00,0x98,0xa1,0x2e]
-; CHECK: frintm.2s v0, v0 ; encoding: [0x00,0x98,0x21,0x0e]
-; CHECK: frintn.2s v0, v0 ; encoding: [0x00,0x88,0x21,0x0e]
-; CHECK: frintp.2s v0, v0 ; encoding: [0x00,0x88,0xa1,0x0e]
-; CHECK: frintz.2s v0, v0 ; encoding: [0x00,0x98,0xa1,0x0e]
-; CHECK: frsqrte.2s v0, v0 ; encoding: [0x00,0xd8,0xa1,0x2e]
-; CHECK: fsqrt.2s v0, v0 ; encoding: [0x00,0xf8,0xa1,0x2e]
-; CHECK: neg.8b v0, v0 ; encoding: [0x00,0xb8,0x20,0x2e]
-; CHECK: mvn.8b v0, v0 ; encoding: [0x00,0x58,0x20,0x2e]
-; CHECK: rbit.8b v0, v0 ; encoding: [0x00,0x58,0x60,0x2e]
-; CHECK: rev16.8b v0, v0 ; encoding: [0x00,0x18,0x20,0x0e]
-; CHECK: rev32.8b v0, v0 ; encoding: [0x00,0x08,0x20,0x2e]
-; CHECK: rev64.8b v0, v0 ; encoding: [0x00,0x08,0x20,0x0e]
-; CHECK: sadalp.4h v0, v0 ; encoding: [0x00,0x68,0x20,0x0e]
-; CHECK: saddlp.4h v0, v0 ; encoding: [0x00,0x28,0x20,0x0e]
-; CHECK: scvtf.2s v0, v0 ; encoding: [0x00,0xd8,0x21,0x0e]
-; CHECK: sqabs.8b v0, v0 ; encoding: [0x00,0x78,0x20,0x0e]
-; CHECK: sqneg.8b v0, v0 ; encoding: [0x00,0x78,0x20,0x2e]
-; CHECK: sqxtn.8b v0, v0 ; encoding: [0x00,0x48,0x21,0x0e]
-; CHECK: sqxtun.8b v0, v0 ; encoding: [0x00,0x28,0x21,0x2e]
-; CHECK: suqadd.8b v0, v0 ; encoding: [0x00,0x38,0x20,0x0e]
-; CHECK: uadalp.4h v0, v0 ; encoding: [0x00,0x68,0x20,0x2e]
-; CHECK: uaddlp.4h v0, v0 ; encoding: [0x00,0x28,0x20,0x2e]
-; CHECK: ucvtf.2s v0, v0 ; encoding: [0x00,0xd8,0x21,0x2e]
-; CHECK: uqxtn.8b v0, v0 ; encoding: [0x00,0x48,0x21,0x2e]
-; CHECK: urecpe.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x0e]
-; CHECK: ursqrte.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x2e]
-; CHECK: usqadd.8b v0, v0 ; encoding: [0x00,0x38,0x20,0x2e]
-; CHECK: xtn.8b v0, v0 ; encoding: [0x00,0x28,0x21,0x0e]
-; CHECK: shll.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x2e]
-; CHECK: shll.4s v3, v4, #16 ; encoding: [0x83,0x38,0x61,0x2e]
-; CHECK: shll.2d v5, v6, #32 ; encoding: [0xc5,0x38,0xa1,0x2e]
-; CHECK: shll2.8h v7, v8, #8 ; encoding: [0x07,0x39,0x21,0x6e]
-; CHECK: shll2.4s v9, v10, #16 ; encoding: [0x49,0x39,0x61,0x6e]
-; CHECK: shll2.2d v11, v12, #32 ; encoding: [0x8b,0x39,0xa1,0x6e]
-; CHECK: shll.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x2e]
-; CHECK: shll.4s v1, v2, #16 ; encoding: [0x41,0x38,0x61,0x2e]
-; CHECK: shll.2d v1, v2, #32 ; encoding: [0x41,0x38,0xa1,0x2e]
-; CHECK: shll2.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x6e]
-; CHECK: shll2.4s v1, v2, #16 ; encoding: [0x41,0x38,0x61,0x6e]
-; CHECK: shll2.2d v1, v2, #32 ; encoding: [0x41,0x38,0xa1,0x6e]
-
-
- cmeq.8b v0, v0, #0
- cmeq.16b v0, v0, #0
- cmeq.4h v0, v0, #0
- cmeq.8h v0, v0, #0
- cmeq.2s v0, v0, #0
- cmeq.4s v0, v0, #0
- cmeq.2d v0, v0, #0
-
-; CHECK: cmeq.8b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x0e]
-; CHECK: cmeq.16b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x4e]
-; CHECK: cmeq.4h v0, v0, #0 ; encoding: [0x00,0x98,0x60,0x0e]
-; CHECK: cmeq.8h v0, v0, #0 ; encoding: [0x00,0x98,0x60,0x4e]
-; CHECK: cmeq.2s v0, v0, #0 ; encoding: [0x00,0x98,0xa0,0x0e]
-; CHECK: cmeq.4s v0, v0, #0 ; encoding: [0x00,0x98,0xa0,0x4e]
-; CHECK: cmeq.2d v0, v0, #0 ; encoding: [0x00,0x98,0xe0,0x4e]
-
- cmge.8b v0, v0, #0
- cmgt.8b v0, v0, #0
- cmle.8b v0, v0, #0
- cmlt.8b v0, v0, #0
- fcmeq.2s v0, v0, #0
- fcmge.2s v0, v0, #0
- fcmgt.2s v0, v0, #0
- fcmle.2s v0, v0, #0
- fcmlt.2s v0, v0, #0
-
-; ARM verbose mode aliases
- cmlt v8.8b, v14.8b, #0
- cmlt v8.16b, v14.16b, #0
- cmlt v8.4h, v14.4h, #0
- cmlt v8.8h, v14.8h, #0
- cmlt v8.2s, v14.2s, #0
- cmlt v8.4s, v14.4s, #0
- cmlt v8.2d, v14.2d, #0
-
-; CHECK: cmge.8b v0, v0, #0 ; encoding: [0x00,0x88,0x20,0x2e]
-; CHECK: cmgt.8b v0, v0, #0 ; encoding: [0x00,0x88,0x20,0x0e]
-; CHECK: cmle.8b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x2e]
-; CHECK: cmlt.8b v0, v0, #0 ; encoding: [0x00,0xa8,0x20,0x0e]
-; CHECK: fcmeq.2s v0, v0, #0.0 ; encoding: [0x00,0xd8,0xa0,0x0e]
-; CHECK: fcmge.2s v0, v0, #0.0 ; encoding: [0x00,0xc8,0xa0,0x2e]
-; CHECK: fcmgt.2s v0, v0, #0.0 ; encoding: [0x00,0xc8,0xa0,0x0e]
-; CHECK: fcmle.2s v0, v0, #0.0 ; encoding: [0x00,0xd8,0xa0,0x2e]
-; CHECK: fcmlt.2s v0, v0, #0.0 ; encoding: [0x00,0xe8,0xa0,0x0e]
-; CHECK: cmlt.8b v8, v14, #0 ; encoding: [0xc8,0xa9,0x20,0x0e]
-; CHECK: cmlt.16b v8, v14, #0 ; encoding: [0xc8,0xa9,0x20,0x4e]
-; CHECK: cmlt.4h v8, v14, #0 ; encoding: [0xc8,0xa9,0x60,0x0e]
-; CHECK: cmlt.8h v8, v14, #0 ; encoding: [0xc8,0xa9,0x60,0x4e]
-; CHECK: cmlt.2s v8, v14, #0 ; encoding: [0xc8,0xa9,0xa0,0x0e]
-; CHECK: cmlt.4s v8, v14, #0 ; encoding: [0xc8,0xa9,0xa0,0x4e]
-; CHECK: cmlt.2d v8, v14, #0 ; encoding: [0xc8,0xa9,0xe0,0x4e]
-
-
-;===-------------------------------------------------------------------------===
-; AdvSIMD Floating-point <-> Integer Conversions
-;===-------------------------------------------------------------------------===
-
- fcvtas.2s v0, v0
- fcvtas.4s v0, v0
- fcvtas.2d v0, v0
- fcvtas s0, s0
- fcvtas d0, d0
-
-; CHECK: fcvtas.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x0e]
-; CHECK: fcvtas.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x4e]
-; CHECK: fcvtas.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x4e]
-; CHECK: fcvtas s0, s0 ; encoding: [0x00,0xc8,0x21,0x5e]
-; CHECK: fcvtas d0, d0 ; encoding: [0x00,0xc8,0x61,0x5e]
-
- fcvtau.2s v0, v0
- fcvtau.4s v0, v0
- fcvtau.2d v0, v0
- fcvtau s0, s0
- fcvtau d0, d0
-
-; CHECK: fcvtau.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x2e]
-; CHECK: fcvtau.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x6e]
-; CHECK: fcvtau.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x6e]
-; CHECK: fcvtau s0, s0 ; encoding: [0x00,0xc8,0x21,0x7e]
-; CHECK: fcvtau d0, d0 ; encoding: [0x00,0xc8,0x61,0x7e]
-
- fcvtl v1.4s, v5.4h
- fcvtl v2.2d, v6.2s
- fcvtl2 v3.4s, v7.8h
- fcvtl2 v4.2d, v8.4s
-
-; CHECK: fcvtl v1.4s, v5.4h ; encoding: [0xa1,0x78,0x21,0x0e]
-; CHECK: fcvtl v2.2d, v6.2s ; encoding: [0xc2,0x78,0x61,0x0e]
-; CHECK: fcvtl2 v3.4s, v7.8h ; encoding: [0xe3,0x78,0x21,0x4e]
-; CHECK: fcvtl2 v4.2d, v8.4s ; encoding: [0x04,0x79,0x61,0x4e]
-
- fcvtms.2s v0, v0
- fcvtms.4s v0, v0
- fcvtms.2d v0, v0
- fcvtms s0, s0
- fcvtms d0, d0
-
-; CHECK: fcvtms.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x0e]
-; CHECK: fcvtms.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x4e]
-; CHECK: fcvtms.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x4e]
-; CHECK: fcvtms s0, s0 ; encoding: [0x00,0xb8,0x21,0x5e]
-; CHECK: fcvtms d0, d0 ; encoding: [0x00,0xb8,0x61,0x5e]
-
- fcvtmu.2s v0, v0
- fcvtmu.4s v0, v0
- fcvtmu.2d v0, v0
- fcvtmu s0, s0
- fcvtmu d0, d0
-
-; CHECK: fcvtmu.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x2e]
-; CHECK: fcvtmu.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x6e]
-; CHECK: fcvtmu.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x6e]
-; CHECK: fcvtmu s0, s0 ; encoding: [0x00,0xb8,0x21,0x7e]
-; CHECK: fcvtmu d0, d0 ; encoding: [0x00,0xb8,0x61,0x7e]
-
- fcvtns.2s v0, v0
- fcvtns.4s v0, v0
- fcvtns.2d v0, v0
- fcvtns s0, s0
- fcvtns d0, d0
-
-; CHECK: fcvtns.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x0e]
-; CHECK: fcvtns.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x4e]
-; CHECK: fcvtns.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x4e]
-; CHECK: fcvtns s0, s0 ; encoding: [0x00,0xa8,0x21,0x5e]
-; CHECK: fcvtns d0, d0 ; encoding: [0x00,0xa8,0x61,0x5e]
-
- fcvtnu.2s v0, v0
- fcvtnu.4s v0, v0
- fcvtnu.2d v0, v0
- fcvtnu s0, s0
- fcvtnu d0, d0
-
-; CHECK: fcvtnu.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x2e]
-; CHECK: fcvtnu.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x6e]
-; CHECK: fcvtnu.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x6e]
-; CHECK: fcvtnu s0, s0 ; encoding: [0x00,0xa8,0x21,0x7e]
-; CHECK: fcvtnu d0, d0 ; encoding: [0x00,0xa8,0x61,0x7e]
-
- fcvtn v2.4h, v4.4s
- fcvtn v3.2s, v5.2d
- fcvtn2 v4.8h, v6.4s
- fcvtn2 v5.4s, v7.2d
- fcvtxn v6.2s, v9.2d
- fcvtxn2 v7.4s, v8.2d
-
-; CHECK: fcvtn v2.4h, v4.4s ; encoding: [0x82,0x68,0x21,0x0e]
-; CHECK: fcvtn v3.2s, v5.2d ; encoding: [0xa3,0x68,0x61,0x0e]
-; CHECK: fcvtn2 v4.8h, v6.4s ; encoding: [0xc4,0x68,0x21,0x4e]
-; CHECK: fcvtn2 v5.4s, v7.2d ; encoding: [0xe5,0x68,0x61,0x4e]
-; CHECK: fcvtxn v6.2s, v9.2d ; encoding: [0x26,0x69,0x61,0x2e]
-; CHECK: fcvtxn2 v7.4s, v8.2d ; encoding: [0x07,0x69,0x61,0x6e]
-
- fcvtps.2s v0, v0
- fcvtps.4s v0, v0
- fcvtps.2d v0, v0
- fcvtps s0, s0
- fcvtps d0, d0
-
-; CHECK: fcvtps.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x0e]
-; CHECK: fcvtps.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x4e]
-; CHECK: fcvtps.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x4e]
-; CHECK: fcvtps s0, s0 ; encoding: [0x00,0xa8,0xa1,0x5e]
-; CHECK: fcvtps d0, d0 ; encoding: [0x00,0xa8,0xe1,0x5e]
-
- fcvtpu.2s v0, v0
- fcvtpu.4s v0, v0
- fcvtpu.2d v0, v0
- fcvtpu s0, s0
- fcvtpu d0, d0
-
-; CHECK: fcvtpu.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x2e]
-; CHECK: fcvtpu.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x6e]
-; CHECK: fcvtpu.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x6e]
-; CHECK: fcvtpu s0, s0 ; encoding: [0x00,0xa8,0xa1,0x7e]
-; CHECK: fcvtpu d0, d0 ; encoding: [0x00,0xa8,0xe1,0x7e]
-
- fcvtzs.2s v0, v0
- fcvtzs.4s v0, v0
- fcvtzs.2d v0, v0
- fcvtzs s0, s0
- fcvtzs d0, d0
-
-; CHECK: fcvtzs.2s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x0e]
-; CHECK: fcvtzs.4s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x4e]
-; CHECK: fcvtzs.2d v0, v0 ; encoding: [0x00,0xb8,0xe1,0x4e]
-; CHECK: fcvtzs s0, s0 ; encoding: [0x00,0xb8,0xa1,0x5e]
-; CHECK: fcvtzs d0, d0 ; encoding: [0x00,0xb8,0xe1,0x5e]
-
- fcvtzu.2s v0, v0
- fcvtzu.4s v0, v0
- fcvtzu.2d v0, v0
- fcvtzu s0, s0
- fcvtzu d0, d0
-
-; CHECK: fcvtzu.2s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x2e]
-; CHECK: fcvtzu.4s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x6e]
-; CHECK: fcvtzu.2d v0, v0 ; encoding: [0x00,0xb8,0xe1,0x6e]
-; CHECK: fcvtzu s0, s0 ; encoding: [0x00,0xb8,0xa1,0x7e]
-; CHECK: fcvtzu d0, d0 ; encoding: [0x00,0xb8,0xe1,0x7e]
-
-;===-------------------------------------------------------------------------===
-; AdvSIMD modified immediate instructions
-;===-------------------------------------------------------------------------===
-
- bic.2s v0, #1
- bic.2s v0, #1, lsl #0
- bic.2s v0, #1, lsl #8
- bic.2s v0, #1, lsl #16
- bic.2s v0, #1, lsl #24
-
-; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f]
-; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f]
-; CHECK: bic.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x2f]
-; CHECK: bic.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x2f]
-; CHECK: bic.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x2f]
-
- bic.4h v0, #1
- bic.4h v0, #1, lsl #0
- bic.4h v0, #1, lsl #8
-
-; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f]
-; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f]
-; CHECK: bic.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x2f]
-
- bic.4s v0, #1
- bic.4s v0, #1, lsl #0
- bic.4s v0, #1, lsl #8
- bic.4s v0, #1, lsl #16
- bic.4s v0, #1, lsl #24
-
-; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f]
-; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f]
-; CHECK: bic.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x6f]
-; CHECK: bic.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x6f]
-; CHECK: bic.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x6f]
-
- bic.8h v0, #1
- bic.8h v0, #1, lsl #0
- bic.8h v0, #1, lsl #8
-
-; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f]
-; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f]
-; CHECK: bic.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x6f]
-
- fmov.2d v0, #1.250000e-01
-
-; CHECK: fmov.2d v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x6f]
-
- fmov.2s v0, #1.250000e-01
- fmov.4s v0, #1.250000e-01
-
-; CHECK: fmov.2s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x0f]
-; CHECK: fmov.4s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x4f]
-
- orr.2s v0, #1
- orr.2s v0, #1, lsl #0
- orr.2s v0, #1, lsl #8
- orr.2s v0, #1, lsl #16
- orr.2s v0, #1, lsl #24
-
-; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f]
-; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f]
-; CHECK: orr.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x0f]
-; CHECK: orr.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x0f]
-; CHECK: orr.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x0f]
-
- orr.4h v0, #1
- orr.4h v0, #1, lsl #0
- orr.4h v0, #1, lsl #8
-
-; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f]
-; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f]
-; CHECK: orr.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x0f]
-
- orr.4s v0, #1
- orr.4s v0, #1, lsl #0
- orr.4s v0, #1, lsl #8
- orr.4s v0, #1, lsl #16
- orr.4s v0, #1, lsl #24
-
-; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f]
-; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f]
-; CHECK: orr.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x4f]
-; CHECK: orr.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x4f]
-; CHECK: orr.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x4f]
-
- orr.8h v0, #1
- orr.8h v0, #1, lsl #0
- orr.8h v0, #1, lsl #8
-
-; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f]
-; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f]
-; CHECK: orr.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x4f]
-
- movi d0, #0x000000000000ff
- movi.2d v0, #0x000000000000ff
-
-; CHECK: movi d0, #0x000000000000ff ; encoding: [0x20,0xe4,0x00,0x2f]
-; CHECK: movi.2d v0, #0x000000000000ff ; encoding: [0x20,0xe4,0x00,0x6f]
-
- movi.2s v0, #1
- movi.2s v0, #1, lsl #0
- movi.2s v0, #1, lsl #8
- movi.2s v0, #1, lsl #16
- movi.2s v0, #1, lsl #24
-
-; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f]
-; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f]
-; CHECK: movi.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x0f]
-; CHECK: movi.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x0f]
-; CHECK: movi.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x0f]
-
- movi.4s v0, #1
- movi.4s v0, #1, lsl #0
- movi.4s v0, #1, lsl #8
- movi.4s v0, #1, lsl #16
- movi.4s v0, #1, lsl #24
-
-; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f]
-; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f]
-; CHECK: movi.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x4f]
-; CHECK: movi.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x4f]
-; CHECK: movi.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x4f]
-
- movi.4h v0, #1
- movi.4h v0, #1, lsl #0
- movi.4h v0, #1, lsl #8
-
-; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f]
-; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f]
-; CHECK: movi.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x0f]
-
- movi.8h v0, #1
- movi.8h v0, #1, lsl #0
- movi.8h v0, #1, lsl #8
-
-; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f]
-; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f]
-; CHECK: movi.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x4f]
-
- movi.2s v0, #1, msl #8
- movi.2s v0, #1, msl #16
- movi.4s v0, #1, msl #8
- movi.4s v0, #1, msl #16
-
-; CHECK: movi.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x0f]
-; CHECK: movi.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x0f]
-; CHECK: movi.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x4f]
-; CHECK: movi.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x4f]
-
- movi.8b v0, #1
- movi.16b v0, #1
-
-; CHECK: movi.8b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x0f]
-; CHECK: movi.16b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x4f]
-
- mvni.2s v0, #1
- mvni.2s v0, #1, lsl #0
- mvni.2s v0, #1, lsl #8
- mvni.2s v0, #1, lsl #16
- mvni.2s v0, #1, lsl #24
-
-; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f]
-; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f]
-; CHECK: mvni.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x2f]
-; CHECK: mvni.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x2f]
-; CHECK: mvni.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x2f]
-
- mvni.4s v0, #1
- mvni.4s v0, #1, lsl #0
- mvni.4s v0, #1, lsl #8
- mvni.4s v0, #1, lsl #16
- mvni.4s v0, #1, lsl #24
-
-; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f]
-; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f]
-; CHECK: mvni.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x6f]
-; CHECK: mvni.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x6f]
-; CHECK: mvni.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x6f]
-
- mvni.4h v0, #1
- mvni.4h v0, #1, lsl #0
- mvni.4h v0, #1, lsl #8
-
-; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f]
-; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f]
-; CHECK: mvni.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x2f]
-
- mvni.8h v0, #1
- mvni.8h v0, #1, lsl #0
- mvni.8h v0, #1, lsl #8
-
-; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f]
-; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f]
-; CHECK: mvni.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x6f]
-
- mvni.2s v0, #1, msl #8
- mvni.2s v0, #1, msl #16
- mvni.4s v0, #1, msl #8
- mvni.4s v0, #1, msl #16
-
-; CHECK: mvni.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x2f]
-; CHECK: mvni.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x2f]
-; CHECK: mvni.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x6f]
-; CHECK: mvni.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x6f]
-
-;===-------------------------------------------------------------------------===
-; AdvSIMD scalar x index
-;===-------------------------------------------------------------------------===
-
- fmla.s s0, s0, v0[3]
- fmla.d d0, d0, v0[1]
- fmls.s s0, s0, v0[3]
- fmls.d d0, d0, v0[1]
- fmulx.s s0, s0, v0[3]
- fmulx.d d0, d0, v0[1]
- fmul.s s0, s0, v0[3]
- fmul.d d0, d0, v0[1]
- sqdmlal.h s0, h0, v0[7]
- sqdmlal.s d0, s0, v0[3]
- sqdmlsl.h s0, h0, v0[7]
- sqdmulh.h h0, h0, v0[7]
- sqdmulh.s s0, s0, v0[3]
- sqdmull.h s0, h0, v0[7]
- sqdmull.s d0, s0, v0[3]
- sqrdmulh.h h0, h0, v0[7]
- sqrdmulh.s s0, s0, v0[3]
-
-; CHECK: fmla.s s0, s0, v0[3] ; encoding: [0x00,0x18,0xa0,0x5f]
-; CHECK: fmla.d d0, d0, v0[1] ; encoding: [0x00,0x18,0xc0,0x5f]
-; CHECK: fmls.s s0, s0, v0[3] ; encoding: [0x00,0x58,0xa0,0x5f]
-; CHECK: fmls.d d0, d0, v0[1] ; encoding: [0x00,0x58,0xc0,0x5f]
-; CHECK: fmulx.s s0, s0, v0[3] ; encoding: [0x00,0x98,0xa0,0x7f]
-; CHECK: fmulx.d d0, d0, v0[1] ; encoding: [0x00,0x98,0xc0,0x7f]
-; CHECK: fmul.s s0, s0, v0[3] ; encoding: [0x00,0x98,0xa0,0x5f]
-; CHECK: fmul.d d0, d0, v0[1] ; encoding: [0x00,0x98,0xc0,0x5f]
-; CHECK: sqdmlal.h s0, h0, v0[7] ; encoding: [0x00,0x38,0x70,0x5f]
-; CHECK: sqdmlal.s d0, s0, v0[3] ; encoding: [0x00,0x38,0xa0,0x5f]
-; CHECK: sqdmlsl.h s0, h0, v0[7] ; encoding: [0x00,0x78,0x70,0x5f]
-; CHECK: sqdmulh.h h0, h0, v0[7] ; encoding: [0x00,0xc8,0x70,0x5f]
-; CHECK: sqdmulh.s s0, s0, v0[3] ; encoding: [0x00,0xc8,0xa0,0x5f]
-; CHECK: sqdmull.h s0, h0, v0[7] ; encoding: [0x00,0xb8,0x70,0x5f]
-; CHECK: sqdmull.s d0, s0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x5f]
-; CHECK: sqrdmulh.h h0, h0, v0[7] ; encoding: [0x00,0xd8,0x70,0x5f]
-; CHECK: sqrdmulh.s s0, s0, v0[3] ; encoding: [0x00,0xd8,0xa0,0x5f]
-
-;===-------------------------------------------------------------------------===
-; AdvSIMD SMLAL
-;===-------------------------------------------------------------------------===
- smlal.8h v1, v2, v3
- smlal.4s v1, v2, v3
- smlal.2d v1, v2, v3
- smlal2.8h v1, v2, v3
- smlal2.4s v1, v2, v3
- smlal2.2d v1, v2, v3
-
- smlal v13.8h, v8.8b, v0.8b
- smlal v13.4s, v8.4h, v0.4h
- smlal v13.2d, v8.2s, v0.2s
- smlal2 v13.8h, v8.16b, v0.16b
- smlal2 v13.4s, v8.8h, v0.8h
- smlal2 v13.2d, v8.4s, v0.4s
-
-; CHECK: smlal.8h v1, v2, v3 ; encoding: [0x41,0x80,0x23,0x0e]
-; CHECK: smlal.4s v1, v2, v3 ; encoding: [0x41,0x80,0x63,0x0e]
-; CHECK: smlal.2d v1, v2, v3 ; encoding: [0x41,0x80,0xa3,0x0e]
-; CHECK: smlal2.8h v1, v2, v3 ; encoding: [0x41,0x80,0x23,0x4e]
-; CHECK: smlal2.4s v1, v2, v3 ; encoding: [0x41,0x80,0x63,0x4e]
-; CHECK: smlal2.2d v1, v2, v3 ; encoding: [0x41,0x80,0xa3,0x4e]
-; CHECK: smlal.8h v13, v8, v0 ; encoding: [0x0d,0x81,0x20,0x0e]
-; CHECK: smlal.4s v13, v8, v0 ; encoding: [0x0d,0x81,0x60,0x0e]
-; CHECK: smlal.2d v13, v8, v0 ; encoding: [0x0d,0x81,0xa0,0x0e]
-; CHECK: smlal2.8h v13, v8, v0 ; encoding: [0x0d,0x81,0x20,0x4e]
-; CHECK: smlal2.4s v13, v8, v0 ; encoding: [0x0d,0x81,0x60,0x4e]
-; CHECK: smlal2.2d v13, v8, v0 ; encoding: [0x0d,0x81,0xa0,0x4e]
-
-
-;===-------------------------------------------------------------------------===
-; AdvSIMD scalar x index
-;===-------------------------------------------------------------------------===
-
- fmla.2s v0, v0, v0[0]
- fmla.4s v0, v0, v0[1]
- fmla.2d v0, v0, v0[1]
- fmls.2s v0, v0, v0[0]
- fmls.4s v0, v0, v0[1]
- fmls.2d v0, v0, v0[1]
- fmulx.2s v0, v0, v0[0]
- fmulx.4s v0, v0, v0[1]
- fmulx.2d v0, v0, v0[1]
- fmul.2s v0, v0, v0[0]
- fmul.4s v0, v0, v0[1]
- fmul.2d v0, v0, v0[1]
- mla.4h v0, v0, v0[0]
- mla.8h v0, v0, v0[1]
- mla.2s v0, v0, v0[2]
- mla.4s v0, v0, v0[3]
- mls.4h v0, v0, v0[0]
- mls.8h v0, v0, v0[1]
- mls.2s v0, v0, v0[2]
- mls.4s v0, v0, v0[3]
- mul.4h v0, v0, v0[0]
- mul.8h v0, v0, v0[1]
- mul.2s v0, v0, v0[2]
- mul.4s v0, v0, v0[3]
- smlal.4s v0, v0, v0[0]
- smlal2.4s v0, v0, v0[1]
- smlal.2d v0, v0, v0[2]
- smlal2.2d v0, v0, v0[3]
- smlsl.4s v0, v0, v0[0]
- smlsl2.4s v0, v0, v0[1]
- smlsl.2d v0, v0, v0[2]
- smlsl2.2d v0, v0, v0[3]
- smull.4s v0, v0, v0[0]
- smull2.4s v0, v0, v0[1]
- smull.2d v0, v0, v0[2]
- smull2.2d v0, v0, v0[3]
- sqdmlal.4s v0, v0, v0[0]
- sqdmlal2.4s v0, v0, v0[1]
- sqdmlal.2d v0, v0, v0[2]
- sqdmlal2.2d v0, v0, v0[3]
- sqdmlsl.4s v0, v0, v0[0]
- sqdmlsl2.4s v0, v0, v0[1]
- sqdmlsl.2d v0, v0, v0[2]
- sqdmlsl2.2d v0, v0, v0[3]
- sqdmulh.4h v0, v0, v0[0]
- sqdmulh.8h v0, v0, v0[1]
- sqdmulh.2s v0, v0, v0[2]
- sqdmulh.4s v0, v0, v0[3]
- sqdmull.4s v0, v0, v0[0]
- sqdmull2.4s v0, v0, v0[1]
- sqdmull.2d v0, v0, v0[2]
- sqdmull2.2d v0, v0, v0[3]
- sqrdmulh.4h v0, v0, v0[0]
- sqrdmulh.8h v0, v0, v0[1]
- sqrdmulh.2s v0, v0, v0[2]
- sqrdmulh.4s v0, v0, v0[3]
- umlal.4s v0, v0, v0[0]
- umlal2.4s v0, v0, v0[1]
- umlal.2d v0, v0, v0[2]
- umlal2.2d v0, v0, v0[3]
- umlsl.4s v0, v0, v0[0]
- umlsl2.4s v0, v0, v0[1]
- umlsl.2d v0, v0, v0[2]
- umlsl2.2d v0, v0, v0[3]
- umull.4s v0, v0, v0[0]
- umull2.4s v0, v0, v0[1]
- umull.2d v0, v0, v0[2]
- umull2.2d v0, v0, v0[3]
-
-; CHECK: fmla.2s v0, v0, v0[0] ; encoding: [0x00,0x10,0x80,0x0f]
-; CHECK: fmla.4s v0, v0, v0[1] ; encoding: [0x00,0x10,0xa0,0x4f]
-; CHECK: fmla.2d v0, v0, v0[1] ; encoding: [0x00,0x18,0xc0,0x4f]
-; CHECK: fmls.2s v0, v0, v0[0] ; encoding: [0x00,0x50,0x80,0x0f]
-; CHECK: fmls.4s v0, v0, v0[1] ; encoding: [0x00,0x50,0xa0,0x4f]
-; CHECK: fmls.2d v0, v0, v0[1] ; encoding: [0x00,0x58,0xc0,0x4f]
-; CHECK: fmulx.2s v0, v0, v0[0] ; encoding: [0x00,0x90,0x80,0x2f]
-; CHECK: fmulx.4s v0, v0, v0[1] ; encoding: [0x00,0x90,0xa0,0x6f]
-; CHECK: fmulx.2d v0, v0, v0[1] ; encoding: [0x00,0x98,0xc0,0x6f]
-; CHECK: fmul.2s v0, v0, v0[0] ; encoding: [0x00,0x90,0x80,0x0f]
-; CHECK: fmul.4s v0, v0, v0[1] ; encoding: [0x00,0x90,0xa0,0x4f]
-; CHECK: fmul.2d v0, v0, v0[1] ; encoding: [0x00,0x98,0xc0,0x4f]
-; CHECK: mla.4h v0, v0, v0[0] ; encoding: [0x00,0x00,0x40,0x2f]
-; CHECK: mla.8h v0, v0, v0[1] ; encoding: [0x00,0x00,0x50,0x6f]
-; CHECK: mla.2s v0, v0, v0[2] ; encoding: [0x00,0x08,0x80,0x2f]
-; CHECK: mla.4s v0, v0, v0[3] ; encoding: [0x00,0x08,0xa0,0x6f]
-; CHECK: mls.4h v0, v0, v0[0] ; encoding: [0x00,0x40,0x40,0x2f]
-; CHECK: mls.8h v0, v0, v0[1] ; encoding: [0x00,0x40,0x50,0x6f]
-; CHECK: mls.2s v0, v0, v0[2] ; encoding: [0x00,0x48,0x80,0x2f]
-; CHECK: mls.4s v0, v0, v0[3] ; encoding: [0x00,0x48,0xa0,0x6f]
-; CHECK: mul.4h v0, v0, v0[0] ; encoding: [0x00,0x80,0x40,0x0f]
-; CHECK: mul.8h v0, v0, v0[1] ; encoding: [0x00,0x80,0x50,0x4f]
-; CHECK: mul.2s v0, v0, v0[2] ; encoding: [0x00,0x88,0x80,0x0f]
-; CHECK: mul.4s v0, v0, v0[3] ; encoding: [0x00,0x88,0xa0,0x4f]
-; CHECK: smlal.4s v0, v0, v0[0] ; encoding: [0x00,0x20,0x40,0x0f]
-; CHECK: smlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x20,0x50,0x4f]
-; CHECK: smlal.2d v0, v0, v0[2] ; encoding: [0x00,0x28,0x80,0x0f]
-; CHECK: smlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x28,0xa0,0x4f]
-; CHECK: smlsl.4s v0, v0, v0[0] ; encoding: [0x00,0x60,0x40,0x0f]
-; CHECK: smlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x60,0x50,0x4f]
-; CHECK: smlsl.2d v0, v0, v0[2] ; encoding: [0x00,0x68,0x80,0x0f]
-; CHECK: smlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x68,0xa0,0x4f]
-; CHECK: smull.4s v0, v0, v0[0] ; encoding: [0x00,0xa0,0x40,0x0f]
-; CHECK: smull2.4s v0, v0, v0[1] ; encoding: [0x00,0xa0,0x50,0x4f]
-; CHECK: smull.2d v0, v0, v0[2] ; encoding: [0x00,0xa8,0x80,0x0f]
-; CHECK: smull2.2d v0, v0, v0[3] ; encoding: [0x00,0xa8,0xa0,0x4f]
-; CHECK: sqdmlal.4s v0, v0, v0[0] ; encoding: [0x00,0x30,0x40,0x0f]
-; CHECK: sqdmlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x30,0x50,0x4f]
-; CHECK: sqdmlal.2d v0, v0, v0[2] ; encoding: [0x00,0x38,0x80,0x0f]
-; CHECK: sqdmlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x38,0xa0,0x4f]
-; CHECK: sqdmlsl.4s v0, v0, v0[0] ; encoding: [0x00,0x70,0x40,0x0f]
-; CHECK: sqdmlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x70,0x50,0x4f]
-; CHECK: sqdmlsl.2d v0, v0, v0[2] ; encoding: [0x00,0x78,0x80,0x0f]
-; CHECK: sqdmlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x78,0xa0,0x4f]
-; CHECK: sqdmulh.4h v0, v0, v0[0] ; encoding: [0x00,0xc0,0x40,0x0f]
-; CHECK: sqdmulh.8h v0, v0, v0[1] ; encoding: [0x00,0xc0,0x50,0x4f]
-; CHECK: sqdmulh.2s v0, v0, v0[2] ; encoding: [0x00,0xc8,0x80,0x0f]
-; CHECK: sqdmulh.4s v0, v0, v0[3] ; encoding: [0x00,0xc8,0xa0,0x4f]
-; CHECK: sqdmull.4s v0, v0, v0[0] ; encoding: [0x00,0xb0,0x40,0x0f]
-; CHECK: sqdmull2.4s v0, v0, v0[1] ; encoding: [0x00,0xb0,0x50,0x4f]
-; CHECK: sqdmull.2d v0, v0, v0[2] ; encoding: [0x00,0xb8,0x80,0x0f]
-; CHECK: sqdmull2.2d v0, v0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x4f]
-; CHECK: sqrdmulh.4h v0, v0, v0[0] ; encoding: [0x00,0xd0,0x40,0x0f]
-; CHECK: sqrdmulh.8h v0, v0, v0[1] ; encoding: [0x00,0xd0,0x50,0x4f]
-; CHECK: sqrdmulh.2s v0, v0, v0[2] ; encoding: [0x00,0xd8,0x80,0x0f]
-; CHECK: sqrdmulh.4s v0, v0, v0[3] ; encoding: [0x00,0xd8,0xa0,0x4f]
-; CHECK: umlal.4s v0, v0, v0[0] ; encoding: [0x00,0x20,0x40,0x2f]
-; CHECK: umlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x20,0x50,0x6f]
-; CHECK: umlal.2d v0, v0, v0[2] ; encoding: [0x00,0x28,0x80,0x2f]
-; CHECK: umlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x28,0xa0,0x6f]
-; CHECK: umlsl.4s v0, v0, v0[0] ; encoding: [0x00,0x60,0x40,0x2f]
-; CHECK: umlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x60,0x50,0x6f]
-; CHECK: umlsl.2d v0, v0, v0[2] ; encoding: [0x00,0x68,0x80,0x2f]
-; CHECK: umlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x68,0xa0,0x6f]
-; CHECK: umull.4s v0, v0, v0[0] ; encoding: [0x00,0xa0,0x40,0x2f]
-; CHECK: umull2.4s v0, v0, v0[1] ; encoding: [0x00,0xa0,0x50,0x6f]
-; CHECK: umull.2d v0, v0, v0[2] ; encoding: [0x00,0xa8,0x80,0x2f]
-; CHECK: umull2.2d v0, v0, v0[3] ; encoding: [0x00,0xa8,0xa0,0x6f]
-
-
-;===-------------------------------------------------------------------------===
-; AdvSIMD scalar with shift
-;===-------------------------------------------------------------------------===
-
- fcvtzs s0, s0, #1
- fcvtzs d0, d0, #2
- fcvtzu s0, s0, #1
- fcvtzu d0, d0, #2
- shl d0, d0, #1
- sli d0, d0, #1
- sqrshrn b0, h0, #1
- sqrshrn h0, s0, #2
- sqrshrn s0, d0, #3
- sqrshrun b0, h0, #1
- sqrshrun h0, s0, #2
- sqrshrun s0, d0, #3
- sqshlu b0, b0, #1
- sqshlu h0, h0, #2
- sqshlu s0, s0, #3
- sqshlu d0, d0, #4
- sqshl b0, b0, #1
- sqshl h0, h0, #2
- sqshl s0, s0, #3
- sqshl d0, d0, #4
- sqshrn b0, h0, #1
- sqshrn h0, s0, #2
- sqshrn s0, d0, #3
- sqshrun b0, h0, #1
- sqshrun h0, s0, #2
- sqshrun s0, d0, #3
- sri d0, d0, #1
- srshr d0, d0, #1
- srsra d0, d0, #1
- sshr d0, d0, #1
- ucvtf s0, s0, #1
- ucvtf d0, d0, #2
- scvtf s0, s0, #1
- scvtf d0, d0, #2
- uqrshrn b0, h0, #1
- uqrshrn h0, s0, #2
- uqrshrn s0, d0, #3
- uqshl b0, b0, #1
- uqshl h0, h0, #2
- uqshl s0, s0, #3
- uqshl d0, d0, #4
- uqshrn b0, h0, #1
- uqshrn h0, s0, #2
- uqshrn s0, d0, #3
- urshr d0, d0, #1
- ursra d0, d0, #1
- ushr d0, d0, #1
- usra d0, d0, #1
-
-; CHECK: fcvtzs s0, s0, #1 ; encoding: [0x00,0xfc,0x3f,0x5f]
-; CHECK: fcvtzs d0, d0, #2 ; encoding: [0x00,0xfc,0x7e,0x5f]
-; CHECK: fcvtzu s0, s0, #1 ; encoding: [0x00,0xfc,0x3f,0x7f]
-; CHECK: fcvtzu d0, d0, #2 ; encoding: [0x00,0xfc,0x7e,0x7f]
-; CHECK: shl d0, d0, #1 ; encoding: [0x00,0x54,0x41,0x5f]
-; CHECK: sli d0, d0, #1 ; encoding: [0x00,0x54,0x41,0x7f]
-; CHECK: sqrshrn b0, h0, #1 ; encoding: [0x00,0x9c,0x0f,0x5f]
-; CHECK: sqrshrn h0, s0, #2 ; encoding: [0x00,0x9c,0x1e,0x5f]
-; CHECK: sqrshrn s0, d0, #3 ; encoding: [0x00,0x9c,0x3d,0x5f]
-; CHECK: sqrshrun b0, h0, #1 ; encoding: [0x00,0x8c,0x0f,0x7f]
-; CHECK: sqrshrun h0, s0, #2 ; encoding: [0x00,0x8c,0x1e,0x7f]
-; CHECK: sqrshrun s0, d0, #3 ; encoding: [0x00,0x8c,0x3d,0x7f]
-; CHECK: sqshlu b0, b0, #1 ; encoding: [0x00,0x64,0x09,0x7f]
-; CHECK: sqshlu h0, h0, #2 ; encoding: [0x00,0x64,0x12,0x7f]
-; CHECK: sqshlu s0, s0, #3 ; encoding: [0x00,0x64,0x23,0x7f]
-; CHECK: sqshlu d0, d0, #4 ; encoding: [0x00,0x64,0x44,0x7f]
-; CHECK: sqshl b0, b0, #1 ; encoding: [0x00,0x74,0x09,0x5f]
-; CHECK: sqshl h0, h0, #2 ; encoding: [0x00,0x74,0x12,0x5f]
-; CHECK: sqshl s0, s0, #3 ; encoding: [0x00,0x74,0x23,0x5f]
-; CHECK: sqshl d0, d0, #4 ; encoding: [0x00,0x74,0x44,0x5f]
-; CHECK: sqshrn b0, h0, #1 ; encoding: [0x00,0x94,0x0f,0x5f]
-; CHECK: sqshrn h0, s0, #2 ; encoding: [0x00,0x94,0x1e,0x5f]
-; CHECK: sqshrn s0, d0, #3 ; encoding: [0x00,0x94,0x3d,0x5f]
-; CHECK: sqshrun b0, h0, #1 ; encoding: [0x00,0x84,0x0f,0x7f]
-; CHECK: sqshrun h0, s0, #2 ; encoding: [0x00,0x84,0x1e,0x7f]
-; CHECK: sqshrun s0, d0, #3 ; encoding: [0x00,0x84,0x3d,0x7f]
-; CHECK: sri d0, d0, #1 ; encoding: [0x00,0x44,0x7f,0x7f]
-; CHECK: srshr d0, d0, #1 ; encoding: [0x00,0x24,0x7f,0x5f]
-; CHECK: srsra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x5f]
-; CHECK: sshr d0, d0, #1 ; encoding: [0x00,0x04,0x7f,0x5f]
-; CHECK: ucvtf s0, s0, #1 ; encoding: [0x00,0xe4,0x3f,0x7f]
-; CHECK: ucvtf d0, d0, #2 ; encoding: [0x00,0xe4,0x7e,0x7f]
-; check: scvtf s0, s0, #1 ; encoding: [0x00,0xe4,0x3f,0x5f]
-; check: scvtf d0, d0, #2 ; encoding: [0x00,0xe4,0x7e,0x5f]
-; CHECK: uqrshrn b0, h0, #1 ; encoding: [0x00,0x9c,0x0f,0x7f]
-; CHECK: uqrshrn h0, s0, #2 ; encoding: [0x00,0x9c,0x1e,0x7f]
-; CHECK: uqrshrn s0, d0, #3 ; encoding: [0x00,0x9c,0x3d,0x7f]
-; CHECK: uqshl b0, b0, #1 ; encoding: [0x00,0x74,0x09,0x7f]
-; CHECK: uqshl h0, h0, #2 ; encoding: [0x00,0x74,0x12,0x7f]
-; CHECK: uqshl s0, s0, #3 ; encoding: [0x00,0x74,0x23,0x7f]
-; CHECK: uqshl d0, d0, #4 ; encoding: [0x00,0x74,0x44,0x7f]
-; CHECK: uqshrn b0, h0, #1 ; encoding: [0x00,0x94,0x0f,0x7f]
-; CHECK: uqshrn h0, s0, #2 ; encoding: [0x00,0x94,0x1e,0x7f]
-; CHECK: uqshrn s0, d0, #3 ; encoding: [0x00,0x94,0x3d,0x7f]
-; CHECK: urshr d0, d0, #1 ; encoding: [0x00,0x24,0x7f,0x7f]
-; CHECK: ursra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x7f]
-; CHECK: ushr d0, d0, #1 ; encoding: [0x00,0x04,0x7f,0x7f]
-; CHECK: usra d0, d0, #1 ; encoding: [0x00,0x14,0x7f,0x7f]
-
-
-;===-------------------------------------------------------------------------===
-; AdvSIMD vector with shift
-;===-------------------------------------------------------------------------===
-
- fcvtzs.2s v0, v0, #1
- fcvtzs.4s v0, v0, #2
- fcvtzs.2d v0, v0, #3
- fcvtzu.2s v0, v0, #1
- fcvtzu.4s v0, v0, #2
- fcvtzu.2d v0, v0, #3
- rshrn.8b v0, v0, #1
- rshrn2.16b v0, v0, #2
- rshrn.4h v0, v0, #3
- rshrn2.8h v0, v0, #4
- rshrn.2s v0, v0, #5
- rshrn2.4s v0, v0, #6
- scvtf.2s v0, v0, #1
- scvtf.4s v0, v0, #2
- scvtf.2d v0, v0, #3
- shl.8b v0, v0, #1
- shl.16b v0, v0, #2
- shl.4h v0, v0, #3
- shl.8h v0, v0, #4
- shl.2s v0, v0, #5
- shl.4s v0, v0, #6
- shl.2d v0, v0, #7
- shrn.8b v0, v0, #1
- shrn2.16b v0, v0, #2
- shrn.4h v0, v0, #3
- shrn2.8h v0, v0, #4
- shrn.2s v0, v0, #5
- shrn2.4s v0, v0, #6
- sli.8b v0, v0, #1
- sli.16b v0, v0, #2
- sli.4h v0, v0, #3
- sli.8h v0, v0, #4
- sli.2s v0, v0, #5
- sli.4s v0, v0, #6
- sli.2d v0, v0, #7
- sqrshrn.8b v0, v0, #1
- sqrshrn2.16b v0, v0, #2
- sqrshrn.4h v0, v0, #3
- sqrshrn2.8h v0, v0, #4
- sqrshrn.2s v0, v0, #5
- sqrshrn2.4s v0, v0, #6
- sqrshrun.8b v0, v0, #1
- sqrshrun2.16b v0, v0, #2
- sqrshrun.4h v0, v0, #3
- sqrshrun2.8h v0, v0, #4
- sqrshrun.2s v0, v0, #5
- sqrshrun2.4s v0, v0, #6
- sqshlu.8b v0, v0, #1
- sqshlu.16b v0, v0, #2
- sqshlu.4h v0, v0, #3
- sqshlu.8h v0, v0, #4
- sqshlu.2s v0, v0, #5
- sqshlu.4s v0, v0, #6
- sqshlu.2d v0, v0, #7
- sqshl.8b v0, v0, #1
- sqshl.16b v0, v0, #2
- sqshl.4h v0, v0, #3
- sqshl.8h v0, v0, #4
- sqshl.2s v0, v0, #5
- sqshl.4s v0, v0, #6
- sqshl.2d v0, v0, #7
- sqshrn.8b v0, v0, #1
- sqshrn2.16b v0, v0, #2
- sqshrn.4h v0, v0, #3
- sqshrn2.8h v0, v0, #4
- sqshrn.2s v0, v0, #5
- sqshrn2.4s v0, v0, #6
- sqshrun.8b v0, v0, #1
- sqshrun2.16b v0, v0, #2
- sqshrun.4h v0, v0, #3
- sqshrun2.8h v0, v0, #4
- sqshrun.2s v0, v0, #5
- sqshrun2.4s v0, v0, #6
- sri.8b v0, v0, #1
- sri.16b v0, v0, #2
- sri.4h v0, v0, #3
- sri.8h v0, v0, #4
- sri.2s v0, v0, #5
- sri.4s v0, v0, #6
- sri.2d v0, v0, #7
- srshr.8b v0, v0, #1
- srshr.16b v0, v0, #2
- srshr.4h v0, v0, #3
- srshr.8h v0, v0, #4
- srshr.2s v0, v0, #5
- srshr.4s v0, v0, #6
- srshr.2d v0, v0, #7
- srsra.8b v0, v0, #1
- srsra.16b v0, v0, #2
- srsra.4h v0, v0, #3
- srsra.8h v0, v0, #4
- srsra.2s v0, v0, #5
- srsra.4s v0, v0, #6
- srsra.2d v0, v0, #7
- sshll.8h v0, v0, #1
- sshll2.8h v0, v0, #2
- sshll.4s v0, v0, #3
- sshll2.4s v0, v0, #4
- sshll.2d v0, v0, #5
- sshll2.2d v0, v0, #6
- sshr.8b v0, v0, #1
- sshr.16b v0, v0, #2
- sshr.4h v0, v0, #3
- sshr.8h v0, v0, #4
- sshr.2s v0, v0, #5
- sshr.4s v0, v0, #6
- sshr.2d v0, v0, #7
- sshr.8b v0, v0, #1
- ssra.16b v0, v0, #2
- ssra.4h v0, v0, #3
- ssra.8h v0, v0, #4
- ssra.2s v0, v0, #5
- ssra.4s v0, v0, #6
- ssra.2d v0, v0, #7
- ssra d0, d0, #64
- ucvtf.2s v0, v0, #1
- ucvtf.4s v0, v0, #2
- ucvtf.2d v0, v0, #3
- uqrshrn.8b v0, v0, #1
- uqrshrn2.16b v0, v0, #2
- uqrshrn.4h v0, v0, #3
- uqrshrn2.8h v0, v0, #4
- uqrshrn.2s v0, v0, #5
- uqrshrn2.4s v0, v0, #6
- uqshl.8b v0, v0, #1
- uqshl.16b v0, v0, #2
- uqshl.4h v0, v0, #3
- uqshl.8h v0, v0, #4
- uqshl.2s v0, v0, #5
- uqshl.4s v0, v0, #6
- uqshl.2d v0, v0, #7
- uqshrn.8b v0, v0, #1
- uqshrn2.16b v0, v0, #2
- uqshrn.4h v0, v0, #3
- uqshrn2.8h v0, v0, #4
- uqshrn.2s v0, v0, #5
- uqshrn2.4s v0, v0, #6
- urshr.8b v0, v0, #1
- urshr.16b v0, v0, #2
- urshr.4h v0, v0, #3
- urshr.8h v0, v0, #4
- urshr.2s v0, v0, #5
- urshr.4s v0, v0, #6
- urshr.2d v0, v0, #7
- ursra.8b v0, v0, #1
- ursra.16b v0, v0, #2
- ursra.4h v0, v0, #3
- ursra.8h v0, v0, #4
- ursra.2s v0, v0, #5
- ursra.4s v0, v0, #6
- ursra.2d v0, v0, #7
- ushll.8h v0, v0, #1
- ushll2.8h v0, v0, #2
- ushll.4s v0, v0, #3
- ushll2.4s v0, v0, #4
- ushll.2d v0, v0, #5
- ushll2.2d v0, v0, #6
- ushr.8b v0, v0, #1
- ushr.16b v0, v0, #2
- ushr.4h v0, v0, #3
- ushr.8h v0, v0, #4
- ushr.2s v0, v0, #5
- ushr.4s v0, v0, #6
- ushr.2d v0, v0, #7
- usra.8b v0, v0, #1
- usra.16b v0, v0, #2
- usra.4h v0, v0, #3
- usra.8h v0, v0, #4
- usra.2s v0, v0, #5
- usra.4s v0, v0, #6
- usra.2d v0, v0, #7
-
-; CHECK: fcvtzs.2s v0, v0, #1 ; encoding: [0x00,0xfc,0x3f,0x0f]
-; CHECK: fcvtzs.4s v0, v0, #2 ; encoding: [0x00,0xfc,0x3e,0x4f]
-; CHECK: fcvtzs.2d v0, v0, #3 ; encoding: [0x00,0xfc,0x7d,0x4f]
-; CHECK: fcvtzu.2s v0, v0, #1 ; encoding: [0x00,0xfc,0x3f,0x2f]
-; CHECK: fcvtzu.4s v0, v0, #2 ; encoding: [0x00,0xfc,0x3e,0x6f]
-; CHECK: fcvtzu.2d v0, v0, #3 ; encoding: [0x00,0xfc,0x7d,0x6f]
-; CHECK: rshrn.8b v0, v0, #1 ; encoding: [0x00,0x8c,0x0f,0x0f]
-; CHECK: rshrn2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x4f]
-; CHECK: rshrn.4h v0, v0, #3 ; encoding: [0x00,0x8c,0x1d,0x0f]
-; CHECK: rshrn2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x4f]
-; CHECK: rshrn.2s v0, v0, #5 ; encoding: [0x00,0x8c,0x3b,0x0f]
-; CHECK: rshrn2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x4f]
-; CHECK: scvtf.2s v0, v0, #1 ; encoding: [0x00,0xe4,0x3f,0x0f]
-; CHECK: scvtf.4s v0, v0, #2 ; encoding: [0x00,0xe4,0x3e,0x4f]
-; CHECK: scvtf.2d v0, v0, #3 ; encoding: [0x00,0xe4,0x7d,0x4f]
-; CHECK: shl.8b v0, v0, #1 ; encoding: [0x00,0x54,0x09,0x0f]
-; CHECK: shl.16b v0, v0, #2 ; encoding: [0x00,0x54,0x0a,0x4f]
-; CHECK: shl.4h v0, v0, #3 ; encoding: [0x00,0x54,0x13,0x0f]
-; CHECK: shl.8h v0, v0, #4 ; encoding: [0x00,0x54,0x14,0x4f]
-; CHECK: shl.2s v0, v0, #5 ; encoding: [0x00,0x54,0x25,0x0f]
-; CHECK: shl.4s v0, v0, #6 ; encoding: [0x00,0x54,0x26,0x4f]
-; CHECK: shl.2d v0, v0, #7 ; encoding: [0x00,0x54,0x47,0x4f]
-; CHECK: shrn.8b v0, v0, #1 ; encoding: [0x00,0x84,0x0f,0x0f]
-; CHECK: shrn2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x4f]
-; CHECK: shrn.4h v0, v0, #3 ; encoding: [0x00,0x84,0x1d,0x0f]
-; CHECK: shrn2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x4f]
-; CHECK: shrn.2s v0, v0, #5 ; encoding: [0x00,0x84,0x3b,0x0f]
-; CHECK: shrn2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x4f]
-; CHECK: sli.8b v0, v0, #1 ; encoding: [0x00,0x54,0x09,0x2f]
-; CHECK: sli.16b v0, v0, #2 ; encoding: [0x00,0x54,0x0a,0x6f]
-; CHECK: sli.4h v0, v0, #3 ; encoding: [0x00,0x54,0x13,0x2f]
-; CHECK: sli.8h v0, v0, #4 ; encoding: [0x00,0x54,0x14,0x6f]
-; CHECK: sli.2s v0, v0, #5 ; encoding: [0x00,0x54,0x25,0x2f]
-; CHECK: sli.4s v0, v0, #6 ; encoding: [0x00,0x54,0x26,0x6f]
-; CHECK: sli.2d v0, v0, #7 ; encoding: [0x00,0x54,0x47,0x6f]
-; CHECK: sqrshrn.8b v0, v0, #1 ; encoding: [0x00,0x9c,0x0f,0x0f]
-; CHECK: sqrshrn2.16b v0, v0, #2 ; encoding: [0x00,0x9c,0x0e,0x4f]
-; CHECK: sqrshrn.4h v0, v0, #3 ; encoding: [0x00,0x9c,0x1d,0x0f]
-; CHECK: sqrshrn2.8h v0, v0, #4 ; encoding: [0x00,0x9c,0x1c,0x4f]
-; CHECK: sqrshrn.2s v0, v0, #5 ; encoding: [0x00,0x9c,0x3b,0x0f]
-; CHECK: sqrshrn2.4s v0, v0, #6 ; encoding: [0x00,0x9c,0x3a,0x4f]
-; CHECK: sqrshrun.8b v0, v0, #1 ; encoding: [0x00,0x8c,0x0f,0x2f]
-; CHECK: sqrshrun2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x6f]
-; CHECK: sqrshrun.4h v0, v0, #3 ; encoding: [0x00,0x8c,0x1d,0x2f]
-; CHECK: sqrshrun2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x6f]
-; CHECK: sqrshrun.2s v0, v0, #5 ; encoding: [0x00,0x8c,0x3b,0x2f]
-; CHECK: sqrshrun2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x6f]
-; CHECK: sqshlu.8b v0, v0, #1 ; encoding: [0x00,0x64,0x09,0x2f]
-; CHECK: sqshlu.16b v0, v0, #2 ; encoding: [0x00,0x64,0x0a,0x6f]
-; CHECK: sqshlu.4h v0, v0, #3 ; encoding: [0x00,0x64,0x13,0x2f]
-; CHECK: sqshlu.8h v0, v0, #4 ; encoding: [0x00,0x64,0x14,0x6f]
-; CHECK: sqshlu.2s v0, v0, #5 ; encoding: [0x00,0x64,0x25,0x2f]
-; CHECK: sqshlu.4s v0, v0, #6 ; encoding: [0x00,0x64,0x26,0x6f]
-; CHECK: sqshlu.2d v0, v0, #7 ; encoding: [0x00,0x64,0x47,0x6f]
-; CHECK: sqshl.8b v0, v0, #1 ; encoding: [0x00,0x74,0x09,0x0f]
-; CHECK: sqshl.16b v0, v0, #2 ; encoding: [0x00,0x74,0x0a,0x4f]
-; CHECK: sqshl.4h v0, v0, #3 ; encoding: [0x00,0x74,0x13,0x0f]
-; CHECK: sqshl.8h v0, v0, #4 ; encoding: [0x00,0x74,0x14,0x4f]
-; CHECK: sqshl.2s v0, v0, #5 ; encoding: [0x00,0x74,0x25,0x0f]
-; CHECK: sqshl.4s v0, v0, #6 ; encoding: [0x00,0x74,0x26,0x4f]
-; CHECK: sqshl.2d v0, v0, #7 ; encoding: [0x00,0x74,0x47,0x4f]
-; CHECK: sqshrn.8b v0, v0, #1 ; encoding: [0x00,0x94,0x0f,0x0f]
-; CHECK: sqshrn2.16b v0, v0, #2 ; encoding: [0x00,0x94,0x0e,0x4f]
-; CHECK: sqshrn.4h v0, v0, #3 ; encoding: [0x00,0x94,0x1d,0x0f]
-; CHECK: sqshrn2.8h v0, v0, #4 ; encoding: [0x00,0x94,0x1c,0x4f]
-; CHECK: sqshrn.2s v0, v0, #5 ; encoding: [0x00,0x94,0x3b,0x0f]
-; CHECK: sqshrn2.4s v0, v0, #6 ; encoding: [0x00,0x94,0x3a,0x4f]
-; CHECK: sqshrun.8b v0, v0, #1 ; encoding: [0x00,0x84,0x0f,0x2f]
-; CHECK: sqshrun2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x6f]
-; CHECK: sqshrun.4h v0, v0, #3 ; encoding: [0x00,0x84,0x1d,0x2f]
-; CHECK: sqshrun2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x6f]
-; CHECK: sqshrun.2s v0, v0, #5 ; encoding: [0x00,0x84,0x3b,0x2f]
-; CHECK: sqshrun2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x6f]
-; CHECK: sri.8b v0, v0, #1 ; encoding: [0x00,0x44,0x0f,0x2f]
-; CHECK: sri.16b v0, v0, #2 ; encoding: [0x00,0x44,0x0e,0x6f]
-; CHECK: sri.4h v0, v0, #3 ; encoding: [0x00,0x44,0x1d,0x2f]
-; CHECK: sri.8h v0, v0, #4 ; encoding: [0x00,0x44,0x1c,0x6f]
-; CHECK: sri.2s v0, v0, #5 ; encoding: [0x00,0x44,0x3b,0x2f]
-; CHECK: sri.4s v0, v0, #6 ; encoding: [0x00,0x44,0x3a,0x6f]
-; CHECK: sri.2d v0, v0, #7 ; encoding: [0x00,0x44,0x79,0x6f]
-; CHECK: srshr.8b v0, v0, #1 ; encoding: [0x00,0x24,0x0f,0x0f]
-; CHECK: srshr.16b v0, v0, #2 ; encoding: [0x00,0x24,0x0e,0x4f]
-; CHECK: srshr.4h v0, v0, #3 ; encoding: [0x00,0x24,0x1d,0x0f]
-; CHECK: srshr.8h v0, v0, #4 ; encoding: [0x00,0x24,0x1c,0x4f]
-; CHECK: srshr.2s v0, v0, #5 ; encoding: [0x00,0x24,0x3b,0x0f]
-; CHECK: srshr.4s v0, v0, #6 ; encoding: [0x00,0x24,0x3a,0x4f]
-; CHECK: srshr.2d v0, v0, #7 ; encoding: [0x00,0x24,0x79,0x4f]
-; CHECK: srsra.8b v0, v0, #1 ; encoding: [0x00,0x34,0x0f,0x0f]
-; CHECK: srsra.16b v0, v0, #2 ; encoding: [0x00,0x34,0x0e,0x4f]
-; CHECK: srsra.4h v0, v0, #3 ; encoding: [0x00,0x34,0x1d,0x0f]
-; CHECK: srsra.8h v0, v0, #4 ; encoding: [0x00,0x34,0x1c,0x4f]
-; CHECK: srsra.2s v0, v0, #5 ; encoding: [0x00,0x34,0x3b,0x0f]
-; CHECK: srsra.4s v0, v0, #6 ; encoding: [0x00,0x34,0x3a,0x4f]
-; CHECK: srsra.2d v0, v0, #7 ; encoding: [0x00,0x34,0x79,0x4f]
-; CHECK: sshll.8h v0, v0, #1 ; encoding: [0x00,0xa4,0x09,0x0f]
-; CHECK: sshll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x4f]
-; CHECK: sshll.4s v0, v0, #3 ; encoding: [0x00,0xa4,0x13,0x0f]
-; CHECK: sshll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x4f]
-; CHECK: sshll.2d v0, v0, #5 ; encoding: [0x00,0xa4,0x25,0x0f]
-; CHECK: sshll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x4f]
-; CHECK: sshr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x0f]
-; CHECK: sshr.16b v0, v0, #2 ; encoding: [0x00,0x04,0x0e,0x4f]
-; CHECK: sshr.4h v0, v0, #3 ; encoding: [0x00,0x04,0x1d,0x0f]
-; CHECK: sshr.8h v0, v0, #4 ; encoding: [0x00,0x04,0x1c,0x4f]
-; CHECK: sshr.2s v0, v0, #5 ; encoding: [0x00,0x04,0x3b,0x0f]
-; CHECK: sshr.4s v0, v0, #6 ; encoding: [0x00,0x04,0x3a,0x4f]
-; CHECK: sshr.2d v0, v0, #7 ; encoding: [0x00,0x04,0x79,0x4f]
-; CHECK: sshr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x0f]
-; CHECK: ssra.16b v0, v0, #2 ; encoding: [0x00,0x14,0x0e,0x4f]
-; CHECK: ssra.4h v0, v0, #3 ; encoding: [0x00,0x14,0x1d,0x0f]
-; CHECK: ssra.8h v0, v0, #4 ; encoding: [0x00,0x14,0x1c,0x4f]
-; CHECK: ssra.2s v0, v0, #5 ; encoding: [0x00,0x14,0x3b,0x0f]
-; CHECK: ssra.4s v0, v0, #6 ; encoding: [0x00,0x14,0x3a,0x4f]
-; CHECK: ssra.2d v0, v0, #7 ; encoding: [0x00,0x14,0x79,0x4f]
-; CHECK: ssra d0, d0, #64 ; encoding: [0x00,0x14,0x40,0x5f]
-; CHECK: ucvtf.2s v0, v0, #1 ; encoding: [0x00,0xe4,0x3f,0x2f]
-; CHECK: ucvtf.4s v0, v0, #2 ; encoding: [0x00,0xe4,0x3e,0x6f]
-; CHECK: ucvtf.2d v0, v0, #3 ; encoding: [0x00,0xe4,0x7d,0x6f]
-; CHECK: uqrshrn.8b v0, v0, #1 ; encoding: [0x00,0x9c,0x0f,0x2f]
-; CHECK: uqrshrn2.16b v0, v0, #2 ; encoding: [0x00,0x9c,0x0e,0x6f]
-; CHECK: uqrshrn.4h v0, v0, #3 ; encoding: [0x00,0x9c,0x1d,0x2f]
-; CHECK: uqrshrn2.8h v0, v0, #4 ; encoding: [0x00,0x9c,0x1c,0x6f]
-; CHECK: uqrshrn.2s v0, v0, #5 ; encoding: [0x00,0x9c,0x3b,0x2f]
-; CHECK: uqrshrn2.4s v0, v0, #6 ; encoding: [0x00,0x9c,0x3a,0x6f]
-; CHECK: uqshl.8b v0, v0, #1 ; encoding: [0x00,0x74,0x09,0x2f]
-; CHECK: uqshl.16b v0, v0, #2 ; encoding: [0x00,0x74,0x0a,0x6f]
-; CHECK: uqshl.4h v0, v0, #3 ; encoding: [0x00,0x74,0x13,0x2f]
-; CHECK: uqshl.8h v0, v0, #4 ; encoding: [0x00,0x74,0x14,0x6f]
-; CHECK: uqshl.2s v0, v0, #5 ; encoding: [0x00,0x74,0x25,0x2f]
-; CHECK: uqshl.4s v0, v0, #6 ; encoding: [0x00,0x74,0x26,0x6f]
-; CHECK: uqshl.2d v0, v0, #7 ; encoding: [0x00,0x74,0x47,0x6f]
-; CHECK: uqshrn.8b v0, v0, #1 ; encoding: [0x00,0x94,0x0f,0x2f]
-; CHECK: uqshrn2.16b v0, v0, #2 ; encoding: [0x00,0x94,0x0e,0x6f]
-; CHECK: uqshrn.4h v0, v0, #3 ; encoding: [0x00,0x94,0x1d,0x2f]
-; CHECK: uqshrn2.8h v0, v0, #4 ; encoding: [0x00,0x94,0x1c,0x6f]
-; CHECK: uqshrn.2s v0, v0, #5 ; encoding: [0x00,0x94,0x3b,0x2f]
-; CHECK: uqshrn2.4s v0, v0, #6 ; encoding: [0x00,0x94,0x3a,0x6f]
-; CHECK: urshr.8b v0, v0, #1 ; encoding: [0x00,0x24,0x0f,0x2f]
-; CHECK: urshr.16b v0, v0, #2 ; encoding: [0x00,0x24,0x0e,0x6f]
-; CHECK: urshr.4h v0, v0, #3 ; encoding: [0x00,0x24,0x1d,0x2f]
-; CHECK: urshr.8h v0, v0, #4 ; encoding: [0x00,0x24,0x1c,0x6f]
-; CHECK: urshr.2s v0, v0, #5 ; encoding: [0x00,0x24,0x3b,0x2f]
-; CHECK: urshr.4s v0, v0, #6 ; encoding: [0x00,0x24,0x3a,0x6f]
-; CHECK: urshr.2d v0, v0, #7 ; encoding: [0x00,0x24,0x79,0x6f]
-; CHECK: ursra.8b v0, v0, #1 ; encoding: [0x00,0x34,0x0f,0x2f]
-; CHECK: ursra.16b v0, v0, #2 ; encoding: [0x00,0x34,0x0e,0x6f]
-; CHECK: ursra.4h v0, v0, #3 ; encoding: [0x00,0x34,0x1d,0x2f]
-; CHECK: ursra.8h v0, v0, #4 ; encoding: [0x00,0x34,0x1c,0x6f]
-; CHECK: ursra.2s v0, v0, #5 ; encoding: [0x00,0x34,0x3b,0x2f]
-; CHECK: ursra.4s v0, v0, #6 ; encoding: [0x00,0x34,0x3a,0x6f]
-; CHECK: ursra.2d v0, v0, #7 ; encoding: [0x00,0x34,0x79,0x6f]
-; CHECK: ushll.8h v0, v0, #1 ; encoding: [0x00,0xa4,0x09,0x2f]
-; CHECK: ushll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x6f]
-; CHECK: ushll.4s v0, v0, #3 ; encoding: [0x00,0xa4,0x13,0x2f]
-; CHECK: ushll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x6f]
-; CHECK: ushll.2d v0, v0, #5 ; encoding: [0x00,0xa4,0x25,0x2f]
-; CHECK: ushll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x6f]
-; CHECK: ushr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x2f]
-; CHECK: ushr.16b v0, v0, #2 ; encoding: [0x00,0x04,0x0e,0x6f]
-; CHECK: ushr.4h v0, v0, #3 ; encoding: [0x00,0x04,0x1d,0x2f]
-; CHECK: ushr.8h v0, v0, #4 ; encoding: [0x00,0x04,0x1c,0x6f]
-; CHECK: ushr.2s v0, v0, #5 ; encoding: [0x00,0x04,0x3b,0x2f]
-; CHECK: ushr.4s v0, v0, #6 ; encoding: [0x00,0x04,0x3a,0x6f]
-; CHECK: ushr.2d v0, v0, #7 ; encoding: [0x00,0x04,0x79,0x6f]
-; CHECK: usra.8b v0, v0, #1 ; encoding: [0x00,0x14,0x0f,0x2f]
-; CHECK: usra.16b v0, v0, #2 ; encoding: [0x00,0x14,0x0e,0x6f]
-; CHECK: usra.4h v0, v0, #3 ; encoding: [0x00,0x14,0x1d,0x2f]
-; CHECK: usra.8h v0, v0, #4 ; encoding: [0x00,0x14,0x1c,0x6f]
-; CHECK: usra.2s v0, v0, #5 ; encoding: [0x00,0x14,0x3b,0x2f]
-; CHECK: usra.4s v0, v0, #6 ; encoding: [0x00,0x14,0x3a,0x6f]
-; CHECK: usra.2d v0, v0, #7 ; encoding: [0x00,0x14,0x79,0x6f]
-
-
-; ARM Verbose syntax variants.
-
- rshrn v9.8b, v11.8h, #1
- rshrn2 v8.16b, v9.8h, #2
- rshrn v7.4h, v8.4s, #3
- rshrn2 v6.8h, v7.4s, #4
- rshrn v5.2s, v6.2d, #5
- rshrn2 v4.4s, v5.2d, #6
-
- shrn v9.8b, v11.8h, #1
- shrn2 v8.16b, v9.8h, #2
- shrn v7.4h, v8.4s, #3
- shrn2 v6.8h, v7.4s, #4
- shrn v5.2s, v6.2d, #5
- shrn2 v4.4s, v5.2d, #6
-
- sqrshrn v9.8b, v11.8h, #1
- sqrshrn2 v8.16b, v9.8h, #2
- sqrshrn v7.4h, v8.4s, #3
- sqrshrn2 v6.8h, v7.4s, #4
- sqrshrn v5.2s, v6.2d, #5
- sqrshrn2 v4.4s, v5.2d, #6
-
- sqshrn v9.8b, v11.8h, #1
- sqshrn2 v8.16b, v9.8h, #2
- sqshrn v7.4h, v8.4s, #3
- sqshrn2 v6.8h, v7.4s, #4
- sqshrn v5.2s, v6.2d, #5
- sqshrn2 v4.4s, v5.2d, #6
-
- sqrshrun v9.8b, v11.8h, #1
- sqrshrun2 v8.16b, v9.8h, #2
- sqrshrun v7.4h, v8.4s, #3
- sqrshrun2 v6.8h, v7.4s, #4
- sqrshrun v5.2s, v6.2d, #5
- sqrshrun2 v4.4s, v5.2d, #6
-
- sqshrun v9.8b, v11.8h, #1
- sqshrun2 v8.16b, v9.8h, #2
- sqshrun v7.4h, v8.4s, #3
- sqshrun2 v6.8h, v7.4s, #4
- sqshrun v5.2s, v6.2d, #5
- sqshrun2 v4.4s, v5.2d, #6
-
- uqrshrn v9.8b, v11.8h, #1
- uqrshrn2 v8.16b, v9.8h, #2
- uqrshrn v7.4h, v8.4s, #3
- uqrshrn2 v6.8h, v7.4s, #4
- uqrshrn v5.2s, v6.2d, #5
- uqrshrn2 v4.4s, v5.2d, #6
-
- uqshrn v9.8b, v11.8h, #1
- uqshrn2 v8.16b, v9.8h, #2
- uqshrn v7.4h, v8.4s, #3
- uqshrn2 v6.8h, v7.4s, #4
- uqshrn v5.2s, v6.2d, #5
- uqshrn2 v4.4s, v5.2d, #6
-
- sshll2 v10.8h, v3.16b, #6
- sshll2 v11.4s, v4.8h, #5
- sshll2 v12.2d, v5.4s, #4
- sshll v13.8h, v6.8b, #3
- sshll v14.4s, v7.4h, #2
- sshll v15.2d, v8.2s, #7
-
- ushll2 v10.8h, v3.16b, #6
- ushll2 v11.4s, v4.8h, #5
- ushll2 v12.2d, v5.4s, #4
- ushll v13.8h, v6.8b, #3
- ushll v14.4s, v7.4h, #2
- ushll v15.2d, v8.2s, #7
-
-
-; CHECK: rshrn.8b v9, v11, #1 ; encoding: [0x69,0x8d,0x0f,0x0f]
-; CHECK: rshrn2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x4f]
-; CHECK: rshrn.4h v7, v8, #3 ; encoding: [0x07,0x8d,0x1d,0x0f]
-; CHECK: rshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x8c,0x1c,0x4f]
-; CHECK: rshrn.2s v5, v6, #5 ; encoding: [0xc5,0x8c,0x3b,0x0f]
-; CHECK: rshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x8c,0x3a,0x4f]
-; CHECK: shrn.8b v9, v11, #1 ; encoding: [0x69,0x85,0x0f,0x0f]
-; CHECK: shrn2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x4f]
-; CHECK: shrn.4h v7, v8, #3 ; encoding: [0x07,0x85,0x1d,0x0f]
-; CHECK: shrn2.8h v6, v7, #4 ; encoding: [0xe6,0x84,0x1c,0x4f]
-; CHECK: shrn.2s v5, v6, #5 ; encoding: [0xc5,0x84,0x3b,0x0f]
-; CHECK: shrn2.4s v4, v5, #6 ; encoding: [0xa4,0x84,0x3a,0x4f]
-; CHECK: sqrshrn.8b v9, v11, #1 ; encoding: [0x69,0x9d,0x0f,0x0f]
-; CHECK: sqrshrn2.16b v8, v9, #2 ; encoding: [0x28,0x9d,0x0e,0x4f]
-; CHECK: sqrshrn.4h v7, v8, #3 ; encoding: [0x07,0x9d,0x1d,0x0f]
-; CHECK: sqrshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x9c,0x1c,0x4f]
-; CHECK: sqrshrn.2s v5, v6, #5 ; encoding: [0xc5,0x9c,0x3b,0x0f]
-; CHECK: sqrshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x9c,0x3a,0x4f]
-; CHECK: sqshrn.8b v9, v11, #1 ; encoding: [0x69,0x95,0x0f,0x0f]
-; CHECK: sqshrn2.16b v8, v9, #2 ; encoding: [0x28,0x95,0x0e,0x4f]
-; CHECK: sqshrn.4h v7, v8, #3 ; encoding: [0x07,0x95,0x1d,0x0f]
-; CHECK: sqshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x94,0x1c,0x4f]
-; CHECK: sqshrn.2s v5, v6, #5 ; encoding: [0xc5,0x94,0x3b,0x0f]
-; CHECK: sqshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x94,0x3a,0x4f]
-; CHECK: sqrshrun.8b v9, v11, #1 ; encoding: [0x69,0x8d,0x0f,0x2f]
-; CHECK: sqrshrun2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x6f]
-; CHECK: sqrshrun.4h v7, v8, #3 ; encoding: [0x07,0x8d,0x1d,0x2f]
-; CHECK: sqrshrun2.8h v6, v7, #4 ; encoding: [0xe6,0x8c,0x1c,0x6f]
-; CHECK: sqrshrun.2s v5, v6, #5 ; encoding: [0xc5,0x8c,0x3b,0x2f]
-; CHECK: sqrshrun2.4s v4, v5, #6 ; encoding: [0xa4,0x8c,0x3a,0x6f]
-; CHECK: sqshrun.8b v9, v11, #1 ; encoding: [0x69,0x85,0x0f,0x2f]
-; CHECK: sqshrun2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x6f]
-; CHECK: sqshrun.4h v7, v8, #3 ; encoding: [0x07,0x85,0x1d,0x2f]
-; CHECK: sqshrun2.8h v6, v7, #4 ; encoding: [0xe6,0x84,0x1c,0x6f]
-; CHECK: sqshrun.2s v5, v6, #5 ; encoding: [0xc5,0x84,0x3b,0x2f]
-; CHECK: sqshrun2.4s v4, v5, #6 ; encoding: [0xa4,0x84,0x3a,0x6f]
-; CHECK: uqrshrn.8b v9, v11, #1 ; encoding: [0x69,0x9d,0x0f,0x2f]
-; CHECK: uqrshrn2.16b v8, v9, #2 ; encoding: [0x28,0x9d,0x0e,0x6f]
-; CHECK: uqrshrn.4h v7, v8, #3 ; encoding: [0x07,0x9d,0x1d,0x2f]
-; CHECK: uqrshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x9c,0x1c,0x6f]
-; CHECK: uqrshrn.2s v5, v6, #5 ; encoding: [0xc5,0x9c,0x3b,0x2f]
-; CHECK: uqrshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x9c,0x3a,0x6f]
-; CHECK: uqshrn.8b v9, v11, #1 ; encoding: [0x69,0x95,0x0f,0x2f]
-; CHECK: uqshrn2.16b v8, v9, #2 ; encoding: [0x28,0x95,0x0e,0x6f]
-; CHECK: uqshrn.4h v7, v8, #3 ; encoding: [0x07,0x95,0x1d,0x2f]
-; CHECK: uqshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x94,0x1c,0x6f]
-; CHECK: uqshrn.2s v5, v6, #5 ; encoding: [0xc5,0x94,0x3b,0x2f]
-; CHECK: uqshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x94,0x3a,0x6f]
-; CHECK: sshll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x4f]
-; CHECK: sshll2.4s v11, v4, #5 ; encoding: [0x8b,0xa4,0x15,0x4f]
-; CHECK: sshll2.2d v12, v5, #4 ; encoding: [0xac,0xa4,0x24,0x4f]
-; CHECK: sshll.8h v13, v6, #3 ; encoding: [0xcd,0xa4,0x0b,0x0f]
-; CHECK: sshll.4s v14, v7, #2 ; encoding: [0xee,0xa4,0x12,0x0f]
-; CHECK: sshll.2d v15, v8, #7 ; encoding: [0x0f,0xa5,0x27,0x0f]
-; CHECK: ushll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x6f]
-; CHECK: ushll2.4s v11, v4, #5 ; encoding: [0x8b,0xa4,0x15,0x6f]
-; CHECK: ushll2.2d v12, v5, #4 ; encoding: [0xac,0xa4,0x24,0x6f]
-; CHECK: ushll.8h v13, v6, #3 ; encoding: [0xcd,0xa4,0x0b,0x2f]
-; CHECK: ushll.4s v14, v7, #2 ; encoding: [0xee,0xa4,0x12,0x2f]
-; CHECK: ushll.2d v15, v8, #7 ; encoding: [0x0f,0xa5,0x27,0x2f]
-
-
- pmull.8h v0, v0, v0
- pmull2.8h v0, v0, v0
- pmull.1q v2, v3, v4
- pmull2.1q v2, v3, v4
- pmull v2.1q, v3.1d, v4.1d
- pmull2 v2.1q, v3.2d, v4.2d
-
-; CHECK: pmull.8h v0, v0, v0 ; encoding: [0x00,0xe0,0x20,0x0e]
-; CHECK: pmull2.8h v0, v0, v0 ; encoding: [0x00,0xe0,0x20,0x4e]
-; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e]
-; CHECK: pmull2.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x4e]
-; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e]
-; CHECK: pmull2.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x4e]
-
-
- faddp.2d d1, v2
- faddp.2s s3, v4
-; CHECK: faddp.2d d1, v2 ; encoding: [0x41,0xd8,0x70,0x7e]
-; CHECK: faddp.2s s3, v4 ; encoding: [0x83,0xd8,0x30,0x7e]
-
- tbl.16b v2, {v4,v5,v6,v7}, v1
- tbl.8b v0, {v4,v5,v6,v7}, v1
- tbl.16b v2, {v5}, v1
- tbl.8b v0, {v5}, v1
- tbl.16b v2, {v5,v6,v7}, v1
- tbl.8b v0, {v5,v6,v7}, v1
- tbl.16b v2, {v6,v7}, v1
- tbl.8b v0, {v6,v7}, v1
-; CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1 ; encoding: [0x82,0x60,0x01,0x4e]
-; CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1 ; encoding: [0x80,0x60,0x01,0x0e]
-; CHECK: tbl.16b v2, { v5 }, v1 ; encoding: [0xa2,0x00,0x01,0x4e]
-; CHECK: tbl.8b v0, { v5 }, v1 ; encoding: [0xa0,0x00,0x01,0x0e]
-; CHECK: tbl.16b v2, { v5, v6, v7 }, v1 ; encoding: [0xa2,0x40,0x01,0x4e]
-; CHECK: tbl.8b v0, { v5, v6, v7 }, v1 ; encoding: [0xa0,0x40,0x01,0x0e]
-; CHECK: tbl.16b v2, { v6, v7 }, v1 ; encoding: [0xc2,0x20,0x01,0x4e]
-; CHECK: tbl.8b v0, { v6, v7 }, v1 ; encoding: [0xc0,0x20,0x01,0x0e]
-
- tbl v2.16b, {v4.16b,v5.16b,v6.16b,v7.16b}, v1.16b
- tbl v0.8b, {v4.16b,v5.16b,v6.16b,v7.16b}, v1.8b
- tbl v2.16b, {v5.16b}, v1.16b
- tbl v0.8b, {v5.16b}, v1.8b
- tbl v2.16b, {v5.16b,v6.16b,v7.16b}, v1.16b
- tbl v0.8b, {v5.16b,v6.16b,v7.16b}, v1.8b
- tbl v2.16b, {v6.16b,v7.16b}, v1.16b
- tbl v0.8b, {v6.16b,v7.16b}, v1.8b
-; CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1 ; encoding: [0x82,0x60,0x01,0x4e]
-; CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1 ; encoding: [0x80,0x60,0x01,0x0e]
-; CHECK: tbl.16b v2, { v5 }, v1 ; encoding: [0xa2,0x00,0x01,0x4e]
-; CHECK: tbl.8b v0, { v5 }, v1 ; encoding: [0xa0,0x00,0x01,0x0e]
-; CHECK: tbl.16b v2, { v5, v6, v7 }, v1 ; encoding: [0xa2,0x40,0x01,0x4e]
-; CHECK: tbl.8b v0, { v5, v6, v7 }, v1 ; encoding: [0xa0,0x40,0x01,0x0e]
-; CHECK: tbl.16b v2, { v6, v7 }, v1 ; encoding: [0xc2,0x20,0x01,0x4e]
-; CHECK: tbl.8b v0, { v6, v7 }, v1 ; encoding: [0xc0,0x20,0x01,0x0e]
-
- sqdmull s0, h0, h0
- sqdmull d0, s0, s0
-; CHECK: sqdmull s0, h0, h0 ; encoding: [0x00,0xd0,0x60,0x5e]
-; CHECK: sqdmull d0, s0, s0 ; encoding: [0x00,0xd0,0xa0,0x5e]
-
- frsqrte s0, s0
- frsqrte d0, d0
-; CHECK: frsqrte s0, s0 ; encoding: [0x00,0xd8,0xa1,0x7e]
-; CHECK: frsqrte d0, d0 ; encoding: [0x00,0xd8,0xe1,0x7e]
-
- mov.16b v0, v0
- mov.2s v0, v0
-; CHECK: mov.16b v0, v0 ; encoding: [0x00,0x1c,0xa0,0x4e]
-; CHECK: mov.8b v0, v0 ; encoding: [0x00,0x1c,0xa0,0x0e]
-
-
-; uadalp/sadalp verbose mode aliases.
- uadalp v14.4h, v25.8b
- uadalp v15.8h, v24.16b
- uadalp v16.2s, v23.4h
- uadalp v17.4s, v22.8h
- uadalp v18.1d, v21.2s
- uadalp v19.2d, v20.4s
-
- sadalp v1.4h, v11.8b
- sadalp v2.8h, v12.16b
- sadalp v3.2s, v13.4h
- sadalp v4.4s, v14.8h
- sadalp v5.1d, v15.2s
- sadalp v6.2d, v16.4s
-
-; CHECK: uadalp.4h v14, v25 ; encoding: [0x2e,0x6b,0x20,0x2e]
-; CHECK: uadalp.8h v15, v24 ; encoding: [0x0f,0x6b,0x20,0x6e]
-; CHECK: uadalp.2s v16, v23 ; encoding: [0xf0,0x6a,0x60,0x2e]
-; CHECK: uadalp.4s v17, v22 ; encoding: [0xd1,0x6a,0x60,0x6e]
-; CHECK: uadalp.1d v18, v21 ; encoding: [0xb2,0x6a,0xa0,0x2e]
-; CHECK: uadalp.2d v19, v20 ; encoding: [0x93,0x6a,0xa0,0x6e]
-; CHECK: sadalp.4h v1, v11 ; encoding: [0x61,0x69,0x20,0x0e]
-; CHECK: sadalp.8h v2, v12 ; encoding: [0x82,0x69,0x20,0x4e]
-; CHECK: sadalp.2s v3, v13 ; encoding: [0xa3,0x69,0x60,0x0e]
-; CHECK: sadalp.4s v4, v14 ; encoding: [0xc4,0x69,0x60,0x4e]
-; CHECK: sadalp.1d v5, v15 ; encoding: [0xe5,0x69,0xa0,0x0e]
-; CHECK: sadalp.2d v6, v16 ; encoding: [0x06,0x6a,0xa0,0x4e]
-
-; MVN is an alias for 'not'.
- mvn v1.8b, v4.8b
- mvn v19.16b, v17.16b
- mvn.8b v10, v6
- mvn.16b v11, v7
-
-; CHECK: mvn.8b v1, v4 ; encoding: [0x81,0x58,0x20,0x2e]
-; CHECK: mvn.16b v19, v17 ; encoding: [0x33,0x5a,0x20,0x6e]
-; CHECK: mvn.8b v10, v6 ; encoding: [0xca,0x58,0x20,0x2e]
-; CHECK: mvn.16b v11, v7 ; encoding: [0xeb,0x58,0x20,0x6e]
-
-; sqdmull verbose mode aliases
- sqdmull v10.4s, v12.4h, v12.4h
- sqdmull2 v10.4s, v13.8h, v13.8h
- sqdmull v10.2d, v13.2s, v13.2s
- sqdmull2 v10.2d, v13.4s, v13.4s
-; CHECK: sqdmull.4s v10, v12, v12 ; encoding: [0x8a,0xd1,0x6c,0x0e]
-; CHECK: sqdmull2.4s v10, v13, v13 ; encoding: [0xaa,0xd1,0x6d,0x4e]
-; CHECK: sqdmull.2d v10, v13, v13 ; encoding: [0xaa,0xd1,0xad,0x0e]
-; CHECK: sqdmull2.2d v10, v13, v13 ; encoding: [0xaa,0xd1,0xad,0x4e]
-
-; xtn verbose mode aliases
- xtn v14.8b, v14.8h
- xtn2 v14.16b, v14.8h
- xtn v14.4h, v14.4s
- xtn2 v14.8h, v14.4s
- xtn v14.2s, v14.2d
- xtn2 v14.4s, v14.2d
-; CHECK: xtn.8b v14, v14 ; encoding: [0xce,0x29,0x21,0x0e]
-; CHECK: xtn2.16b v14, v14 ; encoding: [0xce,0x29,0x21,0x4e]
-; CHECK: xtn.4h v14, v14 ; encoding: [0xce,0x29,0x61,0x0e]
-; CHECK: xtn2.8h v14, v14 ; encoding: [0xce,0x29,0x61,0x4e]
-; CHECK: xtn.2s v14, v14 ; encoding: [0xce,0x29,0xa1,0x0e]
-; CHECK: xtn2.4s v14, v14 ; encoding: [0xce,0x29,0xa1,0x4e]
-
-; uaddl verbose mode aliases
- uaddl v9.8h, v13.8b, v14.8b
- uaddl2 v9.8h, v13.16b, v14.16b
- uaddl v9.4s, v13.4h, v14.4h
- uaddl2 v9.4s, v13.8h, v14.8h
- uaddl v9.2d, v13.2s, v14.2s
- uaddl2 v9.2d, v13.4s, v14.4s
-; CHECK: uaddl.8h v9, v13, v14 ; encoding: [0xa9,0x01,0x2e,0x2e]
-; CHECK: uaddl2.8h v9, v13, v14 ; encoding: [0xa9,0x01,0x2e,0x6e]
-; CHECK: uaddl.4s v9, v13, v14 ; encoding: [0xa9,0x01,0x6e,0x2e]
-; CHECK: uaddl2.4s v9, v13, v14 ; encoding: [0xa9,0x01,0x6e,0x6e]
-; CHECK: uaddl.2d v9, v13, v14 ; encoding: [0xa9,0x01,0xae,0x2e]
-; CHECK: uaddl2.2d v9, v13, v14 ; encoding: [0xa9,0x01,0xae,0x6e]
-
-; bit verbose mode aliases
- bit v9.16b, v10.16b, v10.16b
- bit v9.8b, v10.8b, v10.8b
-; CHECK: bit.16b v9, v10, v10 ; encoding: [0x49,0x1d,0xaa,0x6e]
-; CHECK: bit.8b v9, v10, v10 ; encoding: [0x49,0x1d,0xaa,0x2e]
-
-; pmull verbose mode aliases
- pmull v8.8h, v8.8b, v8.8b
- pmull2 v8.8h, v8.16b, v8.16b
- pmull v8.1q, v8.1d, v8.1d
- pmull2 v8.1q, v8.2d, v8.2d
-; CHECK: pmull.8h v8, v8, v8 ; encoding: [0x08,0xe1,0x28,0x0e]
-; CHECK: pmull2.8h v8, v8, v8 ; encoding: [0x08,0xe1,0x28,0x4e]
-; CHECK: pmull.1q v8, v8, v8 ; encoding: [0x08,0xe1,0xe8,0x0e]
-; CHECK: pmull2.1q v8, v8, v8 ; encoding: [0x08,0xe1,0xe8,0x4e]
-
-; usubl verbose mode aliases
- usubl v9.8h, v13.8b, v14.8b
- usubl2 v9.8h, v13.16b, v14.16b
- usubl v9.4s, v13.4h, v14.4h
- usubl2 v9.4s, v13.8h, v14.8h
- usubl v9.2d, v13.2s, v14.2s
- usubl2 v9.2d, v13.4s, v14.4s
-; CHECK: usubl.8h v9, v13, v14 ; encoding: [0xa9,0x21,0x2e,0x2e]
-; CHECK: usubl2.8h v9, v13, v14 ; encoding: [0xa9,0x21,0x2e,0x6e]
-; CHECK: usubl.4s v9, v13, v14 ; encoding: [0xa9,0x21,0x6e,0x2e]
-; CHECK: usubl2.4s v9, v13, v14 ; encoding: [0xa9,0x21,0x6e,0x6e]
-; CHECK: usubl.2d v9, v13, v14 ; encoding: [0xa9,0x21,0xae,0x2e]
-; CHECK: usubl2.2d v9, v13, v14 ; encoding: [0xa9,0x21,0xae,0x6e]
-
-; uabdl verbose mode aliases
- uabdl v9.8h, v13.8b, v14.8b
- uabdl2 v9.8h, v13.16b, v14.16b
- uabdl v9.4s, v13.4h, v14.4h
- uabdl2 v9.4s, v13.8h, v14.8h
- uabdl v9.2d, v13.2s, v14.2s
- uabdl2 v9.2d, v13.4s, v14.4s
-; CHECK: uabdl.8h v9, v13, v14 ; encoding: [0xa9,0x71,0x2e,0x2e]
-; CHECK: uabdl2.8h v9, v13, v14 ; encoding: [0xa9,0x71,0x2e,0x6e]
-; CHECK: uabdl.4s v9, v13, v14 ; encoding: [0xa9,0x71,0x6e,0x2e]
-; CHECK: uabdl2.4s v9, v13, v14 ; encoding: [0xa9,0x71,0x6e,0x6e]
-; CHECK: uabdl.2d v9, v13, v14 ; encoding: [0xa9,0x71,0xae,0x2e]
-; CHECK: uabdl2.2d v9, v13, v14 ; encoding: [0xa9,0x71,0xae,0x6e]
-
-; umull verbose mode aliases
- umull v9.8h, v13.8b, v14.8b
- umull2 v9.8h, v13.16b, v14.16b
- umull v9.4s, v13.4h, v14.4h
- umull2 v9.4s, v13.8h, v14.8h
- umull v9.2d, v13.2s, v14.2s
- umull2 v9.2d, v13.4s, v14.4s
-; CHECK: umull.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x2e]
-; CHECK: umull2.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x6e]
-; CHECK: umull.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x2e]
-; CHECK: umull2.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x6e]
-; CHECK: umull.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x2e]
-; CHECK: umull2.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x6e]
-
-; smull verbose mode aliases
- smull v9.8h, v13.8b, v14.8b
- smull2 v9.8h, v13.16b, v14.16b
- smull v9.4s, v13.4h, v14.4h
- smull2 v9.4s, v13.8h, v14.8h
- smull v9.2d, v13.2s, v14.2s
- smull2 v9.2d, v13.4s, v14.4s
-; CHECK: smull.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x0e]
-; CHECK: smull2.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x4e]
-; CHECK: smull.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x0e]
-; CHECK: smull2.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x4e]
-; CHECK: smull.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x0e]
-; CHECK: smull2.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x4e]
Removed: llvm/trunk/test/MC/ARM64/aliases.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/aliases.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/aliases.s (original)
+++ llvm/trunk/test/MC/ARM64/aliases.s (removed)
@@ -1,753 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -output-asm-variant=1 -show-encoding < %s | FileCheck %s
-
-foo:
-;-----------------------------------------------------------------------------
-; ADD #0 to/from SP/WSP is a MOV
-;-----------------------------------------------------------------------------
- add x1, sp, #0
-; CHECK: mov x1, sp
- add sp, x2, #0
-; CHECK: mov sp, x2
- add w3, wsp, #0
-; CHECK: mov w3, wsp
- add wsp, w4, #0
-; CHECK: mov wsp, w4
- mov x5, sp
-; CHECK: mov x5, sp
- mov sp, x6
-; CHECK: mov sp, x6
- mov w7, wsp
-; CHECK: mov w7, wsp
- mov wsp, w8
-; CHECK: mov wsp, w8
-
-;-----------------------------------------------------------------------------
-; ORR Rd, Rn, Rn is a MOV
-;-----------------------------------------------------------------------------
- orr x2, xzr, x9
-; CHECK: mov x2, x9
- orr w2, wzr, w9
-; CHECK: mov w2, w9
- mov x3, x4
-; CHECK: mov x3, x4
- mov w5, w6
-; CHECK: mov w5, w6
-
-;-----------------------------------------------------------------------------
-; TST Xn, #<imm>
-;-----------------------------------------------------------------------------
- tst w1, #3
- tst x1, #3
- tst w1, w2
- tst x1, x2
- ands wzr, w1, w2, lsl #2
- ands xzr, x1, x2, lsl #3
- tst w3, w7, lsl #31
- tst x2, x20, asr #0
-
-; CHECK: tst w1, #0x3 ; encoding: [0x3f,0x04,0x00,0x72]
-; CHECK: tst x1, #0x3 ; encoding: [0x3f,0x04,0x40,0xf2]
-; CHECK: tst w1, w2 ; encoding: [0x3f,0x00,0x02,0x6a]
-; CHECK: tst x1, x2 ; encoding: [0x3f,0x00,0x02,0xea]
-; CHECK: tst w1, w2, lsl #2 ; encoding: [0x3f,0x08,0x02,0x6a]
-; CHECK: tst x1, x2, lsl #3 ; encoding: [0x3f,0x0c,0x02,0xea]
-; CHECK: tst w3, w7, lsl #31 ; encoding: [0x7f,0x7c,0x07,0x6a]
-; CHECK: tst x2, x20, asr #0 ; encoding: [0x5f,0x00,0x94,0xea]
-
-;-----------------------------------------------------------------------------
-; ADDS to WZR/XZR is a CMN
-;-----------------------------------------------------------------------------
- cmn w1, #3, lsl #0
- cmn x2, #4194304
- cmn w4, w5
- cmn x6, x7
- cmn w8, w9, asr #3
- cmn x2, x3, lsr #4
- cmn x2, w3, uxtb #1
- cmn x4, x5, uxtx #1
-
-; CHECK: cmn w1, #3 ; encoding: [0x3f,0x0c,0x00,0x31]
-; CHECK: cmn x2, #1024, lsl #12 ; encoding: [0x5f,0x00,0x50,0xb1]
-; CHECK: cmn w4, w5 ; encoding: [0x9f,0x00,0x05,0x2b]
-; CHECK: cmn x6, x7 ; encoding: [0xdf,0x00,0x07,0xab]
-; CHECK: cmn w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x2b]
-; CHECK: cmn x2, x3, lsr #4 ; encoding: [0x5f,0x10,0x43,0xab]
-; CHECK: cmn x2, w3, uxtb #1 ; encoding: [0x5f,0x04,0x23,0xab]
-; CHECK: cmn x4, x5, uxtx #1 ; encoding: [0x9f,0x64,0x25,0xab]
-
-
-;-----------------------------------------------------------------------------
-; SUBS to WZR/XZR is a CMP
-;-----------------------------------------------------------------------------
- cmp w1, #1024, lsl #12
- cmp x2, #1024
- cmp w4, w5
- cmp x6, x7
- cmp w8, w9, asr #3
- cmp x2, x3, lsr #4
- cmp x2, w3, uxth #2
- cmp x4, x5, uxtx
- cmp wzr, w1
- cmp x8, w8, uxtw
- cmp w9, w8, uxtw
- cmp wsp, w9, lsl #0
-
-; CHECK: cmp w1, #1024, lsl #12 ; encoding: [0x3f,0x00,0x50,0x71]
-; CHECK: cmp x2, #1024 ; encoding: [0x5f,0x00,0x10,0xf1]
-; CHECK: cmp w4, w5 ; encoding: [0x9f,0x00,0x05,0x6b]
-; CHECK: cmp x6, x7 ; encoding: [0xdf,0x00,0x07,0xeb]
-; CHECK: cmp w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x6b]
-; CHECK: cmp x2, x3, lsr #4 ; encoding: [0x5f,0x10,0x43,0xeb]
-; CHECK: cmp x2, w3, uxth #2 ; encoding: [0x5f,0x28,0x23,0xeb]
-; CHECK: cmp x4, x5, uxtx ; encoding: [0x9f,0x60,0x25,0xeb]
-; CHECK: cmp wzr, w1 ; encoding: [0xff,0x03,0x01,0x6b]
-; CHECK: cmp x8, w8, uxtw ; encoding: [0x1f,0x41,0x28,0xeb]
-; CHECK: cmp w9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0x6b]
-; CHECK: cmp wsp, w9 ; encoding: [0xff,0x43,0x29,0x6b]
-
-
-;-----------------------------------------------------------------------------
-; SUB/SUBS from WZR/XZR is a NEG
-;-----------------------------------------------------------------------------
-
- neg w0, w1
-; CHECK: neg w0, w1
- neg w0, w1, lsl #1
-; CHECK: neg w0, w1, lsl #1
- neg x0, x1
-; CHECK: neg x0, x1
- neg x0, x1, asr #1
-; CHECK: neg x0, x1, asr #1
- negs w0, w1
-; CHECK: negs w0, w1
- negs w0, w1, lsl #1
-; CHECK: negs w0, w1, lsl #1
- negs x0, x1
-; CHECK: negs x0, x1
- negs x0, x1, asr #1
-; CHECK: negs x0, x1, asr #1
-
-;-----------------------------------------------------------------------------
-; MOV aliases
-;-----------------------------------------------------------------------------
-
- mov x0, #281470681743360
- mov x0, #18446744073709486080
-
-; CHECK: movz x0, #0xffff, lsl #32
-; CHECK: movn x0, #0xffff
-
- mov w0, #0xffffffff
- mov w0, #0xffffff00
- mov wzr, #0xffffffff
- mov wzr, #0xffffff00
-
-; CHECK: movn w0, #0
-; CHECK: movn w0, #0xff
-; CHECK: movn wzr, #0
-; CHECK: movn wzr, #0xff
-
-;-----------------------------------------------------------------------------
-; MVN aliases
-;-----------------------------------------------------------------------------
-
- mvn w4, w9
- mvn x2, x3
- orn w4, wzr, w9
-
-; CHECK: mvn w4, w9 ; encoding: [0xe4,0x03,0x29,0x2a]
-; CHECK: mvn x2, x3 ; encoding: [0xe2,0x03,0x23,0xaa]
-; CHECK: mvn w4, w9 ; encoding: [0xe4,0x03,0x29,0x2a]
-
- mvn w4, w9, lsl #1
- mvn x2, x3, lsl #1
- orn w4, wzr, w9, lsl #1
-
-; CHECK: mvn w4, w9, lsl #1 ; encoding: [0xe4,0x07,0x29,0x2a]
-; CHECK: mvn x2, x3, lsl #1 ; encoding: [0xe2,0x07,0x23,0xaa]
-; CHECK: mvn w4, w9, lsl #1 ; encoding: [0xe4,0x07,0x29,0x2a]
-
-;-----------------------------------------------------------------------------
-; Bitfield aliases
-;-----------------------------------------------------------------------------
-
- bfi w0, w0, #1, #4
- bfi x0, x0, #1, #4
- bfi w0, w0, #0, #2
- bfi x0, x0, #0, #2
- bfxil w0, w0, #2, #3
- bfxil x0, x0, #2, #3
- sbfiz w0, w0, #1, #4
- sbfiz x0, x0, #1, #4
- sbfx w0, w0, #2, #3
- sbfx x0, x0, #2, #3
- ubfiz w0, w0, #1, #4
- ubfiz x0, x0, #1, #4
- ubfx w0, w0, #2, #3
- ubfx x0, x0, #2, #3
-
-; CHECK: bfi w0, w0, #1, #4
-; CHECK: bfi x0, x0, #1, #4
-; CHECK: bfxil w0, w0, #0, #2
-; CHECK: bfxil x0, x0, #0, #2
-; CHECK: bfxil w0, w0, #2, #3
-; CHECK: bfxil x0, x0, #2, #3
-; CHECK: sbfiz w0, w0, #1, #4
-; CHECK: sbfiz x0, x0, #1, #4
-; CHECK: sbfx w0, w0, #2, #3
-; CHECK: sbfx x0, x0, #2, #3
-; CHECK: ubfiz w0, w0, #1, #4
-; CHECK: ubfiz x0, x0, #1, #4
-; CHECK: ubfx w0, w0, #2, #3
-; CHECK: ubfx x0, x0, #2, #3
-
-;-----------------------------------------------------------------------------
-; Shift (immediate) aliases
-;-----------------------------------------------------------------------------
-
-; CHECK: asr w1, w3, #13
-; CHECK: asr x1, x3, #13
-; CHECK: lsl w0, w0, #1
-; CHECK: lsl x0, x0, #1
-; CHECK: lsr w0, w0, #4
-; CHECK: lsr x0, x0, #4
-
- sbfm w1, w3, #13, #31
- sbfm x1, x3, #13, #63
- ubfm w0, w0, #31, #30
- ubfm x0, x0, #63, #62
- ubfm w0, w0, #4, #31
- ubfm x0, x0, #4, #63
-; CHECK: ror w1, w3, #5
-; CHECK: ror x1, x3, #5
- ror w1, w3, #5
- ror x1, x3, #5
-; CHECK: lsl w1, wzr, #3
- lsl w1, wzr, #3
-
-;-----------------------------------------------------------------------------
-; Sign/Zero extend aliases
-;-----------------------------------------------------------------------------
-
- sxtb w1, w2
- sxth w1, w2
- uxtb w1, w2
- uxth w1, w2
-
-; CHECK: sxtb w1, w2
-; CHECK: sxth w1, w2
-; CHECK: uxtb w1, w2
-; CHECK: uxth w1, w2
-
- sxtb x1, w2
- sxth x1, w2
- sxtw x1, w2
- uxtb x1, w2
- uxth x1, w2
- uxtw x1, w2
-
-; CHECK: sxtb x1, w2
-; CHECK: sxth x1, w2
-; CHECK: sxtw x1, w2
-; CHECK: uxtb w1, w2
-; CHECK: uxth w1, w2
-; CHECK: ubfx x1, x2, #0, #32
-
-;-----------------------------------------------------------------------------
-; Negate with carry
-;-----------------------------------------------------------------------------
-
- ngc w1, w2
- ngc x1, x2
- ngcs w1, w2
- ngcs x1, x2
-
-; CHECK: ngc w1, w2
-; CHECK: ngc x1, x2
-; CHECK: ngcs w1, w2
-; CHECK: ngcs x1, x2
-
-;-----------------------------------------------------------------------------
-; 6.6.1 Multiply aliases
-;-----------------------------------------------------------------------------
-
- mneg w1, w2, w3
- mneg x1, x2, x3
- mul w1, w2, w3
- mul x1, x2, x3
- smnegl x1, w2, w3
- umnegl x1, w2, w3
- smull x1, w2, w3
- umull x1, w2, w3
-
-; CHECK: mneg w1, w2, w3
-; CHECK: mneg x1, x2, x3
-; CHECK: mul w1, w2, w3
-; CHECK: mul x1, x2, x3
-; CHECK: smnegl x1, w2, w3
-; CHECK: umnegl x1, w2, w3
-; CHECK: smull x1, w2, w3
-; CHECK: umull x1, w2, w3
-
-;-----------------------------------------------------------------------------
-; Conditional select aliases
-;-----------------------------------------------------------------------------
-
- cset w1, eq
- cset x1, eq
- csetm w1, ne
- csetm x1, ne
- cinc w1, w2, lt
- cinc x1, x2, lt
- cinv w1, w2, mi
- cinv x1, x2, mi
-
-; CHECK: cset w1, eq
-; CHECK: cset x1, eq
-; CHECK: csetm w1, ne
-; CHECK: csetm x1, ne
-; CHECK: cinc w1, w2, lt
-; CHECK: cinc x1, x2, lt
-; CHECK: cinv w1, w2, mi
-; CHECK: cinv x1, x2, mi
-
-;-----------------------------------------------------------------------------
-; SYS aliases
-;-----------------------------------------------------------------------------
-
- sys #0, c7, c1, #0
-; CHECK: ic ialluis
- sys #0, c7, c5, #0
-; CHECK: ic iallu
- sys #3, c7, c5, #1
-; CHECK: ic ivau
-
- sys #3, c7, c4, #1
-; CHECK: dc zva
- sys #0, c7, c6, #1
-; CHECK: dc ivac
- sys #0, c7, c6, #2
-; CHECK: dc isw
- sys #3, c7, c10, #1
-; CHECK: dc cvac
- sys #0, c7, c10, #2
-; CHECK: dc csw
- sys #3, c7, c11, #1
-; CHECK: dc cvau
- sys #3, c7, c14, #1
-; CHECK: dc civac
- sys #0, c7, c14, #2
-; CHECK: dc cisw
-
- sys #0, c7, c8, #0
-; CHECK: at s1e1r
- sys #4, c7, c8, #0
-; CHECK: at s1e2r
- sys #6, c7, c8, #0
-; CHECK: at s1e3r
- sys #0, c7, c8, #1
-; CHECK: at s1e1w
- sys #4, c7, c8, #1
-; CHECK: at s1e2w
- sys #6, c7, c8, #1
-; CHECK: at s1e3w
- sys #0, c7, c8, #2
-; CHECK: at s1e0r
- sys #0, c7, c8, #3
-; CHECK: at s1e0w
- sys #4, c7, c8, #4
-; CHECK: at s12e1r
- sys #4, c7, c8, #5
-; CHECK: at s12e1w
- sys #4, c7, c8, #6
-; CHECK: at s12e0r
- sys #4, c7, c8, #7
-; CHECK: at s12e0w
-
- sys #0, c8, c3, #0
-; CHECK: tlbi vmalle1is
- sys #4, c8, c3, #0
-; CHECK: tlbi alle2is
- sys #6, c8, c3, #0
-; CHECK: tlbi alle3is
- sys #0, c8, c3, #1
-; CHECK: tlbi vae1is
- sys #4, c8, c3, #1
-; CHECK: tlbi vae2is
- sys #6, c8, c3, #1
-; CHECK: tlbi vae3is
- sys #0, c8, c3, #2
-; CHECK: tlbi aside1is
- sys #0, c8, c3, #3
-; CHECK: tlbi vaae1is
- sys #4, c8, c3, #4
-; CHECK: tlbi alle1is
- sys #0, c8, c3, #5
-; CHECK: tlbi vale1is
- sys #0, c8, c3, #7
-; CHECK: tlbi vaale1is
- sys #0, c8, c7, #0
-; CHECK: tlbi vmalle1
- sys #4, c8, c7, #0
-; CHECK: tlbi alle2
- sys #4, c8, c3, #5
-; CHECK: tlbi vale2is
- sys #6, c8, c3, #5
-; CHECK: tlbi vale3is
- sys #6, c8, c7, #0
-; CHECK: tlbi alle3
- sys #0, c8, c7, #1
-; CHECK: tlbi vae1
- sys #4, c8, c7, #1
-; CHECK: tlbi vae2
- sys #6, c8, c7, #1
-; CHECK: tlbi vae3
- sys #0, c8, c7, #2
-; CHECK: tlbi aside1
- sys #0, c8, c7, #3
-; CHECK: tlbi vaae1
- sys #4, c8, c7, #4
-; CHECK: tlbi alle1
- sys #0, c8, c7, #5
-; CHECK: tlbi vale1
- sys #4, c8, c7, #5
-; CHECK: tlbi vale2
- sys #6, c8, c7, #5
-; CHECK: tlbi vale3
- sys #0, c8, c7, #7
-; CHECK: tlbi vaale1
- sys #4, c8, c4, #1
-; CHECK: tlbi ipas2e1
- sys #4, c8, c4, #5
-; CHECK: tlbi ipas2le1
- sys #4, c8, c0, #1
-; CHECK: tlbi ipas2e1is
- sys #4, c8, c0, #5
-; CHECK: tlbi ipas2le1is
- sys #4, c8, c7, #6
-; CHECK: tlbi vmalls12e1
- sys #4, c8, c3, #6
-; CHECK: tlbi vmalls12e1is
-
- ic ialluis
-; CHECK: ic ialluis ; encoding: [0x1f,0x71,0x08,0xd5]
- ic iallu
-; CHECK: ic iallu ; encoding: [0x1f,0x75,0x08,0xd5]
- ic ivau, x0
-; CHECK: ic ivau, x0 ; encoding: [0x20,0x75,0x0b,0xd5]
-
- dc zva, x0
-; CHECK: dc zva, x0 ; encoding: [0x20,0x74,0x0b,0xd5]
- dc ivac, x0
-; CHECK: dc ivac, x0 ; encoding: [0x20,0x76,0x08,0xd5]
- dc isw, x0
-; CHECK: dc isw, x0 ; encoding: [0x40,0x76,0x08,0xd5]
- dc cvac, x0
-; CHECK: dc cvac, x0 ; encoding: [0x20,0x7a,0x0b,0xd5]
- dc csw, x0
-; CHECK: dc csw, x0 ; encoding: [0x40,0x7a,0x08,0xd5]
- dc cvau, x0
-; CHECK: dc cvau, x0 ; encoding: [0x20,0x7b,0x0b,0xd5]
- dc civac, x0
-; CHECK: dc civac, x0 ; encoding: [0x20,0x7e,0x0b,0xd5]
- dc cisw, x0
-; CHECK: dc cisw, x0 ; encoding: [0x40,0x7e,0x08,0xd5]
-
- at s1e1r, x0
-; CHECK: at s1e1r, x0 ; encoding: [0x00,0x78,0x08,0xd5]
- at s1e2r, x0
-; CHECK: at s1e2r, x0 ; encoding: [0x00,0x78,0x0c,0xd5]
- at s1e3r, x0
-; CHECK: at s1e3r, x0 ; encoding: [0x00,0x78,0x0e,0xd5]
- at s1e1w, x0
-; CHECK: at s1e1w, x0 ; encoding: [0x20,0x78,0x08,0xd5]
- at s1e2w, x0
-; CHECK: at s1e2w, x0 ; encoding: [0x20,0x78,0x0c,0xd5]
- at s1e3w, x0
-; CHECK: at s1e3w, x0 ; encoding: [0x20,0x78,0x0e,0xd5]
- at s1e0r, x0
-; CHECK: at s1e0r, x0 ; encoding: [0x40,0x78,0x08,0xd5]
- at s1e0w, x0
-; CHECK: at s1e0w, x0 ; encoding: [0x60,0x78,0x08,0xd5]
- at s12e1r, x0
-; CHECK: at s12e1r, x0 ; encoding: [0x80,0x78,0x0c,0xd5]
- at s12e1w, x0
-; CHECK: at s12e1w, x0 ; encoding: [0xa0,0x78,0x0c,0xd5]
- at s12e0r, x0
-; CHECK: at s12e0r, x0 ; encoding: [0xc0,0x78,0x0c,0xd5]
- at s12e0w, x0
-; CHECK: at s12e0w, x0 ; encoding: [0xe0,0x78,0x0c,0xd5]
-
- tlbi vmalle1is
-; CHECK: tlbi vmalle1is ; encoding: [0x1f,0x83,0x08,0xd5]
- tlbi alle2is
-; CHECK: tlbi alle2is ; encoding: [0x1f,0x83,0x0c,0xd5]
- tlbi alle3is
-; CHECK: tlbi alle3is ; encoding: [0x1f,0x83,0x0e,0xd5]
- tlbi vae1is, x0
-; CHECK: tlbi vae1is, x0 ; encoding: [0x20,0x83,0x08,0xd5]
- tlbi vae2is, x0
-; CHECK: tlbi vae2is, x0 ; encoding: [0x20,0x83,0x0c,0xd5]
- tlbi vae3is, x0
-; CHECK: tlbi vae3is, x0 ; encoding: [0x20,0x83,0x0e,0xd5]
- tlbi aside1is, x0
-; CHECK: tlbi aside1is, x0 ; encoding: [0x40,0x83,0x08,0xd5]
- tlbi vaae1is, x0
-; CHECK: tlbi vaae1is, x0 ; encoding: [0x60,0x83,0x08,0xd5]
- tlbi alle1is
-; CHECK: tlbi alle1is ; encoding: [0x9f,0x83,0x0c,0xd5]
- tlbi vale1is, x0
-; CHECK: tlbi vale1is, x0 ; encoding: [0xa0,0x83,0x08,0xd5]
- tlbi vaale1is, x0
-; CHECK: tlbi vaale1is, x0 ; encoding: [0xe0,0x83,0x08,0xd5]
- tlbi vmalle1
-; CHECK: tlbi vmalle1 ; encoding: [0x1f,0x87,0x08,0xd5]
- tlbi alle2
-; CHECK: tlbi alle2 ; encoding: [0x1f,0x87,0x0c,0xd5]
- tlbi vale2is, x0
-; CHECK: tlbi vale2is, x0 ; encoding: [0xa0,0x83,0x0c,0xd5]
- tlbi vale3is, x0
-; CHECK: tlbi vale3is, x0 ; encoding: [0xa0,0x83,0x0e,0xd5]
- tlbi alle3
-; CHECK: tlbi alle3 ; encoding: [0x1f,0x87,0x0e,0xd5]
- tlbi vae1, x0
-; CHECK: tlbi vae1, x0 ; encoding: [0x20,0x87,0x08,0xd5]
- tlbi vae2, x0
-; CHECK: tlbi vae2, x0 ; encoding: [0x20,0x87,0x0c,0xd5]
- tlbi vae3, x0
-; CHECK: tlbi vae3, x0 ; encoding: [0x20,0x87,0x0e,0xd5]
- tlbi aside1, x0
-; CHECK: tlbi aside1, x0 ; encoding: [0x40,0x87,0x08,0xd5]
- tlbi vaae1, x0
-; CHECK: tlbi vaae1, x0 ; encoding: [0x60,0x87,0x08,0xd5]
- tlbi alle1
-; CHECK: tlbi alle1 ; encoding: [0x9f,0x87,0x0c,0xd5
- tlbi vale1, x0
-; CHECK: tlbi vale1, x0 ; encoding: [0xa0,0x87,0x08,0xd5]
- tlbi vale2, x0
-; CHECK: tlbi vale2, x0 ; encoding: [0xa0,0x87,0x0c,0xd5]
- tlbi vale3, x0
-; CHECK: tlbi vale3, x0 ; encoding: [0xa0,0x87,0x0e,0xd5]
- tlbi vaale1, x0
-; CHECK: tlbi vaale1, x0 ; encoding: [0xe0,0x87,0x08,0xd5]
- tlbi ipas2e1, x0
-; CHECK: tlbi ipas2e1, x0 ; encoding: [0x20,0x84,0x0c,0xd5]
- tlbi ipas2le1, x0
-; CHECK: tlbi ipas2le1, x0 ; encoding: [0xa0,0x84,0x0c,0xd5]
- tlbi ipas2e1is, x0
-; CHECK: tlbi ipas2e1is, x0 ; encoding: [0x20,0x80,0x0c,0xd5]
- tlbi ipas2le1is, x0
-; CHECK: tlbi ipas2le1is, x0 ; encoding: [0xa0,0x80,0x0c,0xd5]
- tlbi vmalls12e1
-; CHECK: tlbi vmalls12e1 ; encoding: [0xdf,0x87,0x0c,0xd5]
- tlbi vmalls12e1is
-; CHECK: tlbi vmalls12e1is ; encoding: [0xdf,0x83,0x0c,0xd5]
-
-;-----------------------------------------------------------------------------
-; 5.8.5 Vector Arithmetic aliases
-;-----------------------------------------------------------------------------
-
- cmls.8b v0, v2, v1
- cmls.16b v0, v2, v1
- cmls.4h v0, v2, v1
- cmls.8h v0, v2, v1
- cmls.2s v0, v2, v1
- cmls.4s v0, v2, v1
- cmls.2d v0, v2, v1
-; CHECK: cmhs.8b v0, v1, v2
-; CHECK: cmhs.16b v0, v1, v2
-; CHECK: cmhs.4h v0, v1, v2
-; CHECK: cmhs.8h v0, v1, v2
-; CHECK: cmhs.2s v0, v1, v2
-; CHECK: cmhs.4s v0, v1, v2
-; CHECK: cmhs.2d v0, v1, v2
-
- cmlo.8b v0, v2, v1
- cmlo.16b v0, v2, v1
- cmlo.4h v0, v2, v1
- cmlo.8h v0, v2, v1
- cmlo.2s v0, v2, v1
- cmlo.4s v0, v2, v1
- cmlo.2d v0, v2, v1
-; CHECK: cmhi.8b v0, v1, v2
-; CHECK: cmhi.16b v0, v1, v2
-; CHECK: cmhi.4h v0, v1, v2
-; CHECK: cmhi.8h v0, v1, v2
-; CHECK: cmhi.2s v0, v1, v2
-; CHECK: cmhi.4s v0, v1, v2
-; CHECK: cmhi.2d v0, v1, v2
-
- cmle.8b v0, v2, v1
- cmle.16b v0, v2, v1
- cmle.4h v0, v2, v1
- cmle.8h v0, v2, v1
- cmle.2s v0, v2, v1
- cmle.4s v0, v2, v1
- cmle.2d v0, v2, v1
-; CHECK: cmge.8b v0, v1, v2
-; CHECK: cmge.16b v0, v1, v2
-; CHECK: cmge.4h v0, v1, v2
-; CHECK: cmge.8h v0, v1, v2
-; CHECK: cmge.2s v0, v1, v2
-; CHECK: cmge.4s v0, v1, v2
-; CHECK: cmge.2d v0, v1, v2
-
- cmlt.8b v0, v2, v1
- cmlt.16b v0, v2, v1
- cmlt.4h v0, v2, v1
- cmlt.8h v0, v2, v1
- cmlt.2s v0, v2, v1
- cmlt.4s v0, v2, v1
- cmlt.2d v0, v2, v1
-; CHECK: cmgt.8b v0, v1, v2
-; CHECK: cmgt.16b v0, v1, v2
-; CHECK: cmgt.4h v0, v1, v2
-; CHECK: cmgt.8h v0, v1, v2
-; CHECK: cmgt.2s v0, v1, v2
-; CHECK: cmgt.4s v0, v1, v2
-; CHECK: cmgt.2d v0, v1, v2
-
- fcmle.2s v0, v2, v1
- fcmle.4s v0, v2, v1
- fcmle.2d v0, v2, v1
-; CHECK: fcmge.2s v0, v1, v2
-; CHECK: fcmge.4s v0, v1, v2
-; CHECK: fcmge.2d v0, v1, v2
-
- fcmlt.2s v0, v2, v1
- fcmlt.4s v0, v2, v1
- fcmlt.2d v0, v2, v1
-; CHECK: fcmgt.2s v0, v1, v2
-; CHECK: fcmgt.4s v0, v1, v2
-; CHECK: fcmgt.2d v0, v1, v2
-
- facle.2s v0, v2, v1
- facle.4s v0, v2, v1
- facle.2d v0, v2, v1
-; CHECK: facge.2s v0, v1, v2
-; CHECK: facge.4s v0, v1, v2
-; CHECK: facge.2d v0, v1, v2
-
- faclt.2s v0, v2, v1
- faclt.4s v0, v2, v1
- faclt.2d v0, v2, v1
-; CHECK: facgt.2s v0, v1, v2
-; CHECK: facgt.4s v0, v1, v2
-; CHECK: facgt.2d v0, v1, v2
-
-;-----------------------------------------------------------------------------
-; 5.8.6 Scalar Arithmetic aliases
-;-----------------------------------------------------------------------------
-
- cmls d0, d2, d1
-; CHECK: cmhs d0, d1, d2
-
- cmle d0, d2, d1
-; CHECK: cmge d0, d1, d2
-
- cmlo d0, d2, d1
-; CHECK: cmhi d0, d1, d2
-
- cmlt d0, d2, d1
-; CHECK: cmgt d0, d1, d2
-
- fcmle s0, s2, s1
- fcmle d0, d2, d1
-; CHECK: fcmge s0, s1, s2
-; CHECK: fcmge d0, d1, d2
-
- fcmlt s0, s2, s1
- fcmlt d0, d2, d1
-; CHECK: fcmgt s0, s1, s2
-; CHECK: fcmgt d0, d1, d2
-
- facle s0, s2, s1
- facle d0, d2, d1
-; CHECK: facge s0, s1, s2
-; CHECK: facge d0, d1, d2
-
- faclt s0, s2, s1
- faclt d0, d2, d1
-; CHECK: facgt s0, s1, s2
-; CHECK: facgt d0, d1, d2
-
-;-----------------------------------------------------------------------------
-; 5.8.14 Vector Shift (immediate)
-;-----------------------------------------------------------------------------
- sxtl v1.8h, v2.8b
-; CHECK: sshll.8h v1, v2, #0
- sxtl.8h v1, v2
-; CHECK: sshll.8h v1, v2, #0
-
- sxtl v1.4s, v2.4h
-; CHECK: sshll.4s v1, v2, #0
- sxtl.4s v1, v2
-; CHECK: sshll.4s v1, v2, #0
-
- sxtl v1.2d, v2.2s
-; CHECK: sshll.2d v1, v2, #0
- sxtl.2d v1, v2
-; CHECK: sshll.2d v1, v2, #0
-
- sxtl2 v1.8h, v2.16b
-; CHECK: sshll2.8h v1, v2, #0
- sxtl2.8h v1, v2
-; CHECK: sshll2.8h v1, v2, #0
-
- sxtl2 v1.4s, v2.8h
-; CHECK: sshll2.4s v1, v2, #0
- sxtl2.4s v1, v2
-; CHECK: sshll2.4s v1, v2, #0
-
- sxtl2 v1.2d, v2.4s
-; CHECK: sshll2.2d v1, v2, #0
- sxtl2.2d v1, v2
-; CHECK: sshll2.2d v1, v2, #0
-
- uxtl v1.8h, v2.8b
-; CHECK: ushll.8h v1, v2, #0
- uxtl.8h v1, v2
-; CHECK: ushll.8h v1, v2, #0
-
- uxtl v1.4s, v2.4h
-; CHECK: ushll.4s v1, v2, #0
- uxtl.4s v1, v2
-; CHECK: ushll.4s v1, v2, #0
-
- uxtl v1.2d, v2.2s
-; CHECK: ushll.2d v1, v2, #0
- uxtl.2d v1, v2
-; CHECK: ushll.2d v1, v2, #0
-
- uxtl2 v1.8h, v2.16b
-; CHECK: ushll2.8h v1, v2, #0
- uxtl2.8h v1, v2
-; CHECK: ushll2.8h v1, v2, #0
-
- uxtl2 v1.4s, v2.8h
-; CHECK: ushll2.4s v1, v2, #0
- uxtl2.4s v1, v2
-; CHECK: ushll2.4s v1, v2, #0
-
- uxtl2 v1.2d, v2.4s
-; CHECK: ushll2.2d v1, v2, #0
- uxtl2.2d v1, v2
-; CHECK: ushll2.2d v1, v2, #0
-
-
-;-----------------------------------------------------------------------------
-; MOVI verbose syntax with shift operand omitted.
-;-----------------------------------------------------------------------------
- movi v4.16b, #0x00
- movi v4.16B, #0x01
- movi v4.8b, #0x02
- movi v4.8B, #0x03
- movi v1.2d, #0x000000000000ff
- movi v2.2D, #0x000000000000ff
-
-; CHECK: movi.16b v4, #0 ; encoding: [0x04,0xe4,0x00,0x4f]
-; CHECK: movi.16b v4, #0x1 ; encoding: [0x24,0xe4,0x00,0x4f]
-; CHECK: movi.8b v4, #0x2 ; encoding: [0x44,0xe4,0x00,0x0f]
-; CHECK: movi.8b v4, #0x3 ; encoding: [0x64,0xe4,0x00,0x0f]
-; CHECK: movi.2d v1, #0x000000000000ff ; encoding: [0x21,0xe4,0x00,0x6f]
-; CHECK: movi.2d v2, #0x000000000000ff ; encoding: [0x22,0xe4,0x00,0x6f]
Removed: llvm/trunk/test/MC/ARM64/arithmetic-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/arithmetic-encoding.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/arithmetic-encoding.s (original)
+++ llvm/trunk/test/MC/ARM64/arithmetic-encoding.s (removed)
@@ -1,615 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -show-encoding < %s | FileCheck %s
-
-foo:
-;==---------------------------------------------------------------------------==
-; Add/Subtract with carry/borrow
-;==---------------------------------------------------------------------------==
-
- adc w1, w2, w3
- adc x1, x2, x3
- adcs w5, w4, w3
- adcs x5, x4, x3
-
-; CHECK: adc w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x1a]
-; CHECK: adc x1, x2, x3 ; encoding: [0x41,0x00,0x03,0x9a]
-; CHECK: adcs w5, w4, w3 ; encoding: [0x85,0x00,0x03,0x3a]
-; CHECK: adcs x5, x4, x3 ; encoding: [0x85,0x00,0x03,0xba]
-
- sbc w1, w2, w3
- sbc x1, x2, x3
- sbcs w1, w2, w3
- sbcs x1, x2, x3
-
-; CHECK: sbc w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x5a]
-; CHECK: sbc x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xda]
-; CHECK: sbcs w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x7a]
-; CHECK: sbcs x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xfa]
-
-;==---------------------------------------------------------------------------==
-; Add/Subtract with (optionally shifted) immediate
-;==---------------------------------------------------------------------------==
-
- add w3, w4, #1024
- add w3, w4, #1024, lsl #0
- add x3, x4, #1024
- add x3, x4, #1024, lsl #0
-
-; CHECK: add w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x11]
-; CHECK: add w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x11]
-; CHECK: add x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0x91]
-; CHECK: add x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0x91]
-
- add w3, w4, #1024, lsl #12
- add w3, w4, #4194304
- add w3, w4, #0, lsl #12
- add x3, x4, #1024, lsl #12
- add x3, x4, #4194304
- add x3, x4, #0, lsl #12
- add sp, sp, #32
-
-; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11]
-; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11]
-; CHECK: add w3, w4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x11]
-; CHECK: add x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x91]
-; CHECK: add x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x91]
-; CHECK: add x3, x4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x91]
-; CHECK: add sp, sp, #32 ; encoding: [0xff,0x83,0x00,0x91]
-
- adds w3, w4, #1024
- adds w3, w4, #1024, lsl #0
- adds w3, w4, #1024, lsl #12
- adds x3, x4, #1024
- adds x3, x4, #1024, lsl #0
- adds x3, x4, #1024, lsl #12
-
-; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31]
-; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31]
-; CHECK: adds w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x31]
-; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1]
-; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1]
-; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1]
-
- sub w3, w4, #1024
- sub w3, w4, #1024, lsl #0
- sub w3, w4, #1024, lsl #12
- sub x3, x4, #1024
- sub x3, x4, #1024, lsl #0
- sub x3, x4, #1024, lsl #12
- sub sp, sp, #32
-
-; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51]
-; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51]
-; CHECK: sub w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x51]
-; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1]
-; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1]
-; CHECK: sub x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xd1]
-; CHECK: sub sp, sp, #32 ; encoding: [0xff,0x83,0x00,0xd1]
-
- subs w3, w4, #1024
- subs w3, w4, #1024, lsl #0
- subs w3, w4, #1024, lsl #12
- subs x3, x4, #1024
- subs x3, x4, #1024, lsl #0
- subs x3, x4, #1024, lsl #12
-
-; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71]
-; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71]
-; CHECK: subs w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x71]
-; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1]
-; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1]
-; CHECK: subs x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xf1]
-
-;==---------------------------------------------------------------------------==
-; Add/Subtract register with (optional) shift
-;==---------------------------------------------------------------------------==
-
- add w12, w13, w14
- add x12, x13, x14
- add w12, w13, w14, lsl #12
- add x12, x13, x14, lsl #12
- add x12, x13, x14, lsr #42
- add x12, x13, x14, asr #39
-
-; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b]
-; CHECK: add x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0x8b]
-; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b]
-; CHECK: add x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x8b]
-; CHECK: add x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x8b]
-; CHECK: add x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x8b]
-
- sub w12, w13, w14
- sub x12, x13, x14
- sub w12, w13, w14, lsl #12
- sub x12, x13, x14, lsl #12
- sub x12, x13, x14, lsr #42
- sub x12, x13, x14, asr #39
-
-; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b]
-; CHECK: sub x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xcb]
-; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b]
-; CHECK: sub x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xcb]
-; CHECK: sub x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xcb]
-; CHECK: sub x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xcb]
-
- adds w12, w13, w14
- adds x12, x13, x14
- adds w12, w13, w14, lsl #12
- adds x12, x13, x14, lsl #12
- adds x12, x13, x14, lsr #42
- adds x12, x13, x14, asr #39
-
-; CHECK: adds w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x2b]
-; CHECK: adds x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xab]
-; CHECK: adds w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x2b]
-; CHECK: adds x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xab]
-; CHECK: adds x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xab]
-; CHECK: adds x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xab]
-
- subs w12, w13, w14
- subs x12, x13, x14
- subs w12, w13, w14, lsl #12
- subs x12, x13, x14, lsl #12
- subs x12, x13, x14, lsr #42
- subs x12, x13, x14, asr #39
-
-; CHECK: subs w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x6b]
-; CHECK: subs x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xeb]
-; CHECK: subs w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x6b]
-; CHECK: subs x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xeb]
-; CHECK: subs x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xeb]
-; CHECK: subs x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xeb]
-
-; Check use of upper case register names rdar://14354073
- add X2, X2, X2
-; CHECK: add x2, x2, x2 ; encoding: [0x42,0x00,0x02,0x8b]
-
-;==---------------------------------------------------------------------------==
-; Add/Subtract with (optional) extend
-;==---------------------------------------------------------------------------==
-
- add w1, w2, w3, uxtb
- add w1, w2, w3, uxth
- add w1, w2, w3, uxtw
- add w1, w2, w3, uxtx
- add w1, w2, w3, sxtb
- add w1, w2, w3, sxth
- add w1, w2, w3, sxtw
- add w1, w2, w3, sxtx
-
-; CHECK: add w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x0b]
-; CHECK: add w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x0b]
-; CHECK: add w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x0b]
-; CHECK: add w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x0b]
-; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b]
-; CHECK: add w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x0b]
-; CHECK: add w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x0b]
-; CHECK: add w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x0b]
-
- add x1, x2, w3, uxtb
- add x1, x2, w3, uxth
- add x1, x2, w3, uxtw
- add x1, x2, w3, sxtb
- add x1, x2, w3, sxth
- add x1, x2, w3, sxtw
-
-; CHECK: add x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x8b]
-; CHECK: add x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0x8b]
-; CHECK: add x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x8b]
-; CHECK: add x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x8b]
-; CHECK: add x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x8b]
-; CHECK: add x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x8b]
-
- add w1, wsp, w3
- add w1, wsp, w3, uxtw #0
- add w2, wsp, w3, lsl #1
- add sp, x2, x3
- add sp, x2, x3, uxtx #0
-
-; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b]
-; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b]
-; CHECK: add w2, wsp, w3, lsl #1 ; encoding: [0xe2,0x47,0x23,0x0b]
-; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b]
-; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b]
-
- sub w1, w2, w3, uxtb
- sub w1, w2, w3, uxth
- sub w1, w2, w3, uxtw
- sub w1, w2, w3, uxtx
- sub w1, w2, w3, sxtb
- sub w1, w2, w3, sxth
- sub w1, w2, w3, sxtw
- sub w1, w2, w3, sxtx
-
-; CHECK: sub w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x4b]
-; CHECK: sub w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x4b]
-; CHECK: sub w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x4b]
-; CHECK: sub w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x4b]
-; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b]
-; CHECK: sub w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x4b]
-; CHECK: sub w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x4b]
-; CHECK: sub w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x4b]
-
- sub x1, x2, w3, uxtb
- sub x1, x2, w3, uxth
- sub x1, x2, w3, uxtw
- sub x1, x2, w3, sxtb
- sub x1, x2, w3, sxth
- sub x1, x2, w3, sxtw
-
-; CHECK: sub x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xcb]
-; CHECK: sub x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xcb]
-; CHECK: sub x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xcb]
-; CHECK: sub x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xcb]
-; CHECK: sub x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xcb]
-; CHECK: sub x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xcb]
-
- sub w1, wsp, w3
- sub w1, wsp, w3, uxtw #0
- sub sp, x2, x3
- sub sp, x2, x3, uxtx #0
- sub sp, x3, x7, lsl #4
-
-; CHECK: sub w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x4b]
-; CHECK: sub w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x4b]
-; CHECK: sub sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0xcb]
-; CHECK: sub sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0xcb]
-; CHECK: sp, x3, x7, lsl #4 ; encoding: [0x7f,0x70,0x27,0xcb]
-
- adds w1, w2, w3, uxtb
- adds w1, w2, w3, uxth
- adds w1, w2, w3, uxtw
- adds w1, w2, w3, uxtx
- adds w1, w2, w3, sxtb
- adds w1, w2, w3, sxth
- adds w1, w2, w3, sxtw
- adds w1, w2, w3, sxtx
-
-; CHECK: adds w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x2b]
-; CHECK: adds w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x2b]
-; CHECK: adds w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x2b]
-; CHECK: adds w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x2b]
-; CHECK: adds w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x2b]
-; CHECK: adds w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x2b]
-; CHECK: adds w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x2b]
-; CHECK: adds w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x2b]
-
- adds x1, x2, w3, uxtb
- adds x1, x2, w3, uxth
- adds x1, x2, w3, uxtw
- adds x1, x2, w3, uxtx
- adds x1, x2, w3, sxtb
- adds x1, x2, w3, sxth
- adds x1, x2, w3, sxtw
- adds x1, x2, w3, sxtx
-
-; CHECK: adds x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xab]
-; CHECK: adds x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xab]
-; CHECK: adds x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xab]
-; CHECK: adds x1, x2, w3, uxtx ; encoding: [0x41,0x60,0x23,0xab]
-; CHECK: adds x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xab]
-; CHECK: adds x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xab]
-; CHECK: adds x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xab]
-; CHECK: adds x1, x2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0xab]
-
- adds w1, wsp, w3
- adds w1, wsp, w3, uxtw #0
- adds wzr, wsp, w3, lsl #4
-
-; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b]
-; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b]
-; CHECK: cmn wsp, w3, lsl #4 ; encoding: [0xff,0x53,0x23,0x2b]
-
- subs w1, w2, w3, uxtb
- subs w1, w2, w3, uxth
- subs w1, w2, w3, uxtw
- subs w1, w2, w3, uxtx
- subs w1, w2, w3, sxtb
- subs w1, w2, w3, sxth
- subs w1, w2, w3, sxtw
- subs w1, w2, w3, sxtx
-
-; CHECK: subs w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x6b]
-; CHECK: subs w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x6b]
-; CHECK: subs w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x6b]
-; CHECK: subs w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x6b]
-; CHECK: subs w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x6b]
-; CHECK: subs w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x6b]
-; CHECK: subs w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x6b]
-; CHECK: subs w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x6b]
-
- subs x1, x2, w3, uxtb
- subs x1, x2, w3, uxth
- subs x1, x2, w3, uxtw
- subs x1, x2, w3, uxtx
- subs x1, x2, w3, sxtb
- subs x1, x2, w3, sxth
- subs x1, x2, w3, sxtw
- subs x1, x2, w3, sxtx
-
-; CHECK: subs x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xeb]
-; CHECK: subs x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xeb]
-; CHECK: subs x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xeb]
-; CHECK: subs x1, x2, w3, uxtx ; encoding: [0x41,0x60,0x23,0xeb]
-; CHECK: subs x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xeb]
-; CHECK: subs x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xeb]
-; CHECK: subs x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xeb]
-; CHECK: subs x1, x2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0xeb]
-
- subs w1, wsp, w3
- subs w1, wsp, w3, uxtw #0
-
-; CHECK: subs w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x6b]
-; CHECK: subs w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x6b]
-
- cmp wsp, w9, lsl #0
- subs x3, sp, x9, lsl #2
- cmp wsp, w8, uxtw
- subs wzr, wsp, w8, uxtw
- cmp sp, w8, uxtw
- subs xzr, sp, w8, uxtw
-
-; CHECK: cmp wsp, w9 ; encoding: [0xff,0x43,0x29,0x6b]
-; CHECK: subs x3, sp, x9, lsl #2 ; encoding: [0xe3,0x6b,0x29,0xeb]
-; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b]
-; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b]
-; CHECK: cmp sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xeb]
-; CHECK: cmp sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xeb]
-
- sub wsp, w9, w8, uxtw
- sub w1, wsp, w8, uxtw
- sub wsp, wsp, w8, uxtw
- sub sp, x9, w8, uxtw
- sub x1, sp, w8, uxtw
- sub sp, sp, w8, uxtw
- subs w1, wsp, w8, uxtw
- subs x1, sp, w8, uxtw
-
-; CHECK: sub wsp, w9, w8 ; encoding: [0x3f,0x41,0x28,0x4b]
-; CHECK: sub w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x4b]
-; CHECK: sub wsp, wsp, w8 ; encoding: [0xff,0x43,0x28,0x4b]
-; CHECK: sub sp, x9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0xcb]
-; CHECK: sub x1, sp, w8, uxtw ; encoding: [0xe1,0x43,0x28,0xcb]
-; CHECK: sub sp, sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xcb]
-; CHECK: subs w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x6b]
-; CHECK: subs x1, sp, w8, uxtw ; encoding: [0xe1,0x43,0x28,0xeb]
-
-;==---------------------------------------------------------------------------==
-; Signed/Unsigned divide
-;==---------------------------------------------------------------------------==
-
- sdiv w1, w2, w3
- sdiv x1, x2, x3
- udiv w1, w2, w3
- udiv x1, x2, x3
-
-; CHECK: sdiv w1, w2, w3 ; encoding: [0x41,0x0c,0xc3,0x1a]
-; CHECK: sdiv x1, x2, x3 ; encoding: [0x41,0x0c,0xc3,0x9a]
-; CHECK: udiv w1, w2, w3 ; encoding: [0x41,0x08,0xc3,0x1a]
-; CHECK: udiv x1, x2, x3 ; encoding: [0x41,0x08,0xc3,0x9a]
-
-;==---------------------------------------------------------------------------==
-; Variable shifts
-;==---------------------------------------------------------------------------==
-
- asrv w1, w2, w3
- asrv x1, x2, x3
- asr w1, w2, w3
- asr x1, x2, x3
- lslv w1, w2, w3
- lslv x1, x2, x3
- lsl w1, w2, w3
- lsl x1, x2, x3
- lsrv w1, w2, w3
- lsrv x1, x2, x3
- lsr w1, w2, w3
- lsr x1, x2, x3
- rorv w1, w2, w3
- rorv x1, x2, x3
- ror w1, w2, w3
- ror x1, x2, x3
-
-; CHECK: encoding: [0x41,0x28,0xc3,0x1a]
-; CHECK: encoding: [0x41,0x28,0xc3,0x9a]
-; CHECK: encoding: [0x41,0x28,0xc3,0x1a]
-; CHECK: encoding: [0x41,0x28,0xc3,0x9a]
-; CHECK: encoding: [0x41,0x20,0xc3,0x1a]
-; CHECK: encoding: [0x41,0x20,0xc3,0x9a]
-; CHECK: encoding: [0x41,0x20,0xc3,0x1a]
-; CHECK: encoding: [0x41,0x20,0xc3,0x9a]
-; CHECK: encoding: [0x41,0x24,0xc3,0x1a]
-; CHECK: encoding: [0x41,0x24,0xc3,0x9a]
-; CHECK: encoding: [0x41,0x24,0xc3,0x1a]
-; CHECK: encoding: [0x41,0x24,0xc3,0x9a]
-; CHECK: encoding: [0x41,0x2c,0xc3,0x1a]
-; CHECK: encoding: [0x41,0x2c,0xc3,0x9a]
-; CHECK: encoding: [0x41,0x2c,0xc3,0x1a]
-; CHECK: encoding: [0x41,0x2c,0xc3,0x9a]
-
-;==---------------------------------------------------------------------------==
-; One operand instructions
-;==---------------------------------------------------------------------------==
-
- cls w1, w2
- cls x1, x2
- clz w1, w2
- clz x1, x2
- rbit w1, w2
- rbit x1, x2
- rev w1, w2
- rev x1, x2
- rev16 w1, w2
- rev16 x1, x2
- rev32 x1, x2
-
-; CHECK: encoding: [0x41,0x14,0xc0,0x5a]
-; CHECK: encoding: [0x41,0x14,0xc0,0xda]
-; CHECK: encoding: [0x41,0x10,0xc0,0x5a]
-; CHECK: encoding: [0x41,0x10,0xc0,0xda]
-; CHECK: encoding: [0x41,0x00,0xc0,0x5a]
-; CHECK: encoding: [0x41,0x00,0xc0,0xda]
-; CHECK: encoding: [0x41,0x08,0xc0,0x5a]
-; CHECK: encoding: [0x41,0x0c,0xc0,0xda]
-; CHECK: encoding: [0x41,0x04,0xc0,0x5a]
-; CHECK: encoding: [0x41,0x04,0xc0,0xda]
-; CHECK: encoding: [0x41,0x08,0xc0,0xda]
-
-;==---------------------------------------------------------------------------==
-; 6.6.1 Multiply-add instructions
-;==---------------------------------------------------------------------------==
-
- madd w1, w2, w3, w4
- madd x1, x2, x3, x4
- msub w1, w2, w3, w4
- msub x1, x2, x3, x4
- smaddl x1, w2, w3, x4
- smsubl x1, w2, w3, x4
- umaddl x1, w2, w3, x4
- umsubl x1, w2, w3, x4
-
-; CHECK: madd w1, w2, w3, w4 ; encoding: [0x41,0x10,0x03,0x1b]
-; CHECK: madd x1, x2, x3, x4 ; encoding: [0x41,0x10,0x03,0x9b]
-; CHECK: msub w1, w2, w3, w4 ; encoding: [0x41,0x90,0x03,0x1b]
-; CHECK: msub x1, x2, x3, x4 ; encoding: [0x41,0x90,0x03,0x9b]
-; CHECK: smaddl x1, w2, w3, x4 ; encoding: [0x41,0x10,0x23,0x9b]
-; CHECK: smsubl x1, w2, w3, x4 ; encoding: [0x41,0x90,0x23,0x9b]
-; CHECK: umaddl x1, w2, w3, x4 ; encoding: [0x41,0x10,0xa3,0x9b]
-; CHECK: umsubl x1, w2, w3, x4 ; encoding: [0x41,0x90,0xa3,0x9b]
-
-;==---------------------------------------------------------------------------==
-; Multiply-high instructions
-;==---------------------------------------------------------------------------==
-
- smulh x1, x2, x3
- umulh x1, x2, x3
-
-; CHECK: smulh x1, x2, x3 ; encoding: [0x41,0x7c,0x43,0x9b]
-; CHECK: umulh x1, x2, x3 ; encoding: [0x41,0x7c,0xc3,0x9b]
-
-;==---------------------------------------------------------------------------==
-; Move immediate instructions
-;==---------------------------------------------------------------------------==
-
- movz w0, #1
- movz x0, #1
- movz w0, #1, lsl #16
- movz x0, #1, lsl #16
-
-; CHECK: movz w0, #0x1 ; encoding: [0x20,0x00,0x80,0x52]
-; CHECK: movz x0, #0x1 ; encoding: [0x20,0x00,0x80,0xd2]
-; CHECK: movz w0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x52]
-; CHECK: movz x0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xd2]
-
- movn w0, #2
- movn x0, #2
- movn w0, #2, lsl #16
- movn x0, #2, lsl #16
-
-; CHECK: movn w0, #0x2 ; encoding: [0x40,0x00,0x80,0x12]
-; CHECK: movn x0, #0x2 ; encoding: [0x40,0x00,0x80,0x92]
-; CHECK: movn w0, #0x2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x12]
-; CHECK: movn x0, #0x2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x92]
-
- movk w0, #1
- movk x0, #1
- movk w0, #1, lsl #16
- movk x0, #1, lsl #16
-
-; CHECK: movk w0, #0x1 ; encoding: [0x20,0x00,0x80,0x72]
-; CHECK: movk x0, #0x1 ; encoding: [0x20,0x00,0x80,0xf2]
-; CHECK: movk w0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x72]
-; CHECK: movk x0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xf2]
-
-;==---------------------------------------------------------------------------==
-; Conditionally set flags instructions
-;==---------------------------------------------------------------------------==
-
- ccmn w1, #2, #3, eq
- ccmn x1, #2, #3, eq
- ccmp w1, #2, #3, eq
- ccmp x1, #2, #3, eq
-
-; CHECK: encoding: [0x23,0x08,0x42,0x3a]
-; CHECK: encoding: [0x23,0x08,0x42,0xba]
-; CHECK: encoding: [0x23,0x08,0x42,0x7a]
-; CHECK: encoding: [0x23,0x08,0x42,0xfa]
-
- ccmn w1, w2, #3, eq
- ccmn x1, x2, #3, eq
- ccmp w1, w2, #3, eq
- ccmp x1, x2, #3, eq
-
-; CHECK: encoding: [0x23,0x00,0x42,0x3a]
-; CHECK: encoding: [0x23,0x00,0x42,0xba]
-; CHECK: encoding: [0x23,0x00,0x42,0x7a]
-; CHECK: encoding: [0x23,0x00,0x42,0xfa]
-
-;==---------------------------------------------------------------------------==
-; Conditional select instructions
-;==---------------------------------------------------------------------------==
-
- csel w1, w2, w3, eq
- csel x1, x2, x3, eq
- csinc w1, w2, w3, eq
- csinc x1, x2, x3, eq
- csinv w1, w2, w3, eq
- csinv x1, x2, x3, eq
- csneg w1, w2, w3, eq
- csneg x1, x2, x3, eq
-
-; CHECK: encoding: [0x41,0x00,0x83,0x1a]
-; CHECK: encoding: [0x41,0x00,0x83,0x9a]
-; CHECK: encoding: [0x41,0x04,0x83,0x1a]
-; CHECK: encoding: [0x41,0x04,0x83,0x9a]
-; CHECK: encoding: [0x41,0x00,0x83,0x5a]
-; CHECK: encoding: [0x41,0x00,0x83,0xda]
-; CHECK: encoding: [0x41,0x04,0x83,0x5a]
-; CHECK: encoding: [0x41,0x04,0x83,0xda]
-
-; Make sure we handle upper case, too. In particular, condition codes.
- CSEL W16, W7, W27, EQ
- CSEL W15, W6, W26, NE
- CSEL W14, W5, W25, CS
- CSEL W13, W4, W24, HS
- csel w12, w3, w23, CC
- csel w11, w2, w22, LO
- csel w10, w1, w21, MI
- csel x9, x9, x1, PL
- csel x8, x8, x2, VS
- CSEL X7, X7, X3, VC
- CSEL X6, X7, X4, HI
- CSEL X5, X6, X5, LS
- CSEL X4, X5, X6, GE
- csel x3, x4, x7, LT
- csel x2, x3, x8, GT
- csel x1, x2, x9, LE
- csel x10, x1, x20, AL
-
-; CHECK: csel w16, w7, w27, eq ; encoding: [0xf0,0x00,0x9b,0x1a]
-; CHECK: csel w15, w6, w26, ne ; encoding: [0xcf,0x10,0x9a,0x1a]
-; CHECK: csel w14, w5, w25, hs ; encoding: [0xae,0x20,0x99,0x1a]
-; CHECK: csel w13, w4, w24, hs ; encoding: [0x8d,0x20,0x98,0x1a]
-; CHECK: csel w12, w3, w23, lo ; encoding: [0x6c,0x30,0x97,0x1a]
-; CHECK: csel w11, w2, w22, lo ; encoding: [0x4b,0x30,0x96,0x1a]
-; CHECK: csel w10, w1, w21, mi ; encoding: [0x2a,0x40,0x95,0x1a]
-; CHECK: csel x9, x9, x1, pl ; encoding: [0x29,0x51,0x81,0x9a]
-; CHECK: csel x8, x8, x2, vs ; encoding: [0x08,0x61,0x82,0x9a]
-; CHECK: csel x7, x7, x3, vc ; encoding: [0xe7,0x70,0x83,0x9a]
-; CHECK: csel x6, x7, x4, hi ; encoding: [0xe6,0x80,0x84,0x9a]
-; CHECK: csel x5, x6, x5, ls ; encoding: [0xc5,0x90,0x85,0x9a]
-; CHECK: csel x4, x5, x6, ge ; encoding: [0xa4,0xa0,0x86,0x9a]
-; CHECK: csel x3, x4, x7, lt ; encoding: [0x83,0xb0,0x87,0x9a]
-; CHECK: csel x2, x3, x8, gt ; encoding: [0x62,0xc0,0x88,0x9a]
-; CHECK: csel x1, x2, x9, le ; encoding: [0x41,0xd0,0x89,0x9a]
-; CHECK: csel x10, x1, x20, al ; encoding: [0x2a,0xe0,0x94,0x9a]
-
-
-;==---------------------------------------------------------------------------==
-; Scalar saturating arithmetic
-;==---------------------------------------------------------------------------==
- uqxtn b4, h2
- uqxtn h2, s3
- uqxtn s9, d2
-
-; CHECK: uqxtn b4, h2 ; encoding: [0x44,0x48,0x21,0x7e]
-; CHECK: uqxtn h2, s3 ; encoding: [0x62,0x48,0x61,0x7e]
-; CHECK: uqxtn s9, d2 ; encoding: [0x49,0x48,0xa1,0x7e]
Removed: llvm/trunk/test/MC/ARM64/arm64-fixup.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/arm64-fixup.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/arm64-fixup.s (original)
+++ llvm/trunk/test/MC/ARM64/arm64-fixup.s (removed)
@@ -1,10 +0,0 @@
-; RUN: llvm-mc < %s -triple arm64-apple-darwin --show-encoding | FileCheck %s
-
-foo:
- adr x3, Lbar
-; CHECK: adr x3, Lbar ; encoding: [0x03'A',A,A,0x10'A']
-; CHECK: fixup A - offset: 0, value: Lbar, kind: fixup_arm64_pcrel_adr_imm21
-Lbar:
- adrp x3, _printf at page
-; CHECK: adrp x3, _printf at PAGE ; encoding: [0x03'A',A,A,0x90'A']
-; CHECK: fixup A - offset: 0, value: _printf at PAGE, kind: fixup_arm64_pcrel_adrp_imm21
Removed: llvm/trunk/test/MC/ARM64/basic-a64-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/basic-a64-instructions.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/basic-a64-instructions.s (original)
+++ llvm/trunk/test/MC/ARM64/basic-a64-instructions.s (removed)
@@ -1,18 +0,0 @@
-// RUN: llvm-mc -triple arm64 -mattr=+crc -show-encoding < %s | FileCheck %s
-
- crc32b w5, w7, w20
- crc32h w28, wzr, w30
- crc32w w0, w1, w2
- crc32x w7, w9, x20
- crc32cb w9, w5, w4
- crc32ch w13, w17, w25
- crc32cw wzr, w3, w5
- crc32cx w18, w16, xzr
-// CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a]
-// CHECK: crc32h w28, wzr, w30 // encoding: [0xfc,0x47,0xde,0x1a]
-// CHECK: crc32w w0, w1, w2 // encoding: [0x20,0x48,0xc2,0x1a]
-// CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a]
-// CHECK: crc32cb w9, w5, w4 // encoding: [0xa9,0x50,0xc4,0x1a]
-// CHECK: crc32ch w13, w17, w25 // encoding: [0x2d,0x56,0xd9,0x1a]
-// CHECK: crc32cw wzr, w3, w5 // encoding: [0x7f,0x58,0xc5,0x1a]
-// CHECK: crc32cx w18, w16, xzr // encoding: [0x12,0x5e,0xdf,0x9a]
Removed: llvm/trunk/test/MC/ARM64/be-datalayout.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/be-datalayout.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/be-datalayout.s (original)
+++ llvm/trunk/test/MC/ARM64/be-datalayout.s (removed)
@@ -1,4 +0,0 @@
-// RUN: llvm-mc -filetype=obj -triple arm64_be %s | llvm-readobj -section-data -sections | FileCheck %s
-
-// CHECK: 0000: 00123456 789ABCDE
-foo: .xword 0x123456789abcde
Removed: llvm/trunk/test/MC/ARM64/bitfield-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/bitfield-encoding.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/bitfield-encoding.s (original)
+++ llvm/trunk/test/MC/ARM64/bitfield-encoding.s (removed)
@@ -1,38 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
-
-foo:
-;==---------------------------------------------------------------------------==
-; 5.4.4 Bitfield Operations
-;==---------------------------------------------------------------------------==
-
- bfm w1, w2, #1, #15
- bfm x1, x2, #1, #15
- sbfm w1, w2, #1, #15
- sbfm x1, x2, #1, #15
- ubfm w1, w2, #1, #15
- ubfm x1, x2, #1, #15
- sbfiz wzr, w0, #31, #1
- sbfiz xzr, x0, #31, #1
- ubfiz wzr, w0, #31, #1
- ubfiz xzr, x0, #31, #1
-
-; CHECK: bfxil w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x33]
-; CHECK: bfxil x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xb3]
-; CHECK: sbfx w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x13]
-; CHECK: sbfx x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0x93]
-; CHECK: ubfx w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x53]
-; CHECK: ubfx x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xd3]
-; CHECK: sbfiz wzr, w0, #31, #1 ; encoding: [0x1f,0x00,0x01,0x13]
-; CHECK: sbfiz xzr, x0, #31, #1 ; encoding: [0x1f,0x00,0x61,0x93]
-; CHECK: lsl wzr, w0, #31 ; encoding: [0x1f,0x00,0x01,0x53]
-; CHECK: ubfiz xzr, x0, #31, #1 ; encoding: [0x1f,0x00,0x61,0xd3]
-
-;==---------------------------------------------------------------------------==
-; 5.4.5 Extract (immediate)
-;==---------------------------------------------------------------------------==
-
- extr w1, w2, w3, #15
- extr x2, x3, x4, #1
-
-; CHECK: extr w1, w2, w3, #15 ; encoding: [0x41,0x3c,0x83,0x13]
-; CHECK: extr x2, x3, x4, #1 ; encoding: [0x62,0x04,0xc4,0x93]
Removed: llvm/trunk/test/MC/ARM64/branch-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/branch-encoding.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/branch-encoding.s (original)
+++ llvm/trunk/test/MC/ARM64/branch-encoding.s (removed)
@@ -1,159 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
-
-foo:
-
-;-----------------------------------------------------------------------------
-; Unconditional branch (register) instructions.
-;-----------------------------------------------------------------------------
-
- ret
-; CHECK: encoding: [0xc0,0x03,0x5f,0xd6]
- ret x1
-; CHECK: encoding: [0x20,0x00,0x5f,0xd6]
- drps
-; CHECK: encoding: [0xe0,0x03,0xbf,0xd6]
- eret
-; CHECK: encoding: [0xe0,0x03,0x9f,0xd6]
- br x5
-; CHECK: encoding: [0xa0,0x00,0x1f,0xd6]
- blr x9
-; CHECK: encoding: [0x20,0x01,0x3f,0xd6]
- bl L1
-; CHECK: bl L1 ; encoding: [A,A,A,0b100101AA]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_call26
-
-;-----------------------------------------------------------------------------
-; Contitional branch instructions.
-;-----------------------------------------------------------------------------
-
- b L1
-; CHECK: b L1 ; encoding: [A,A,A,0b000101AA]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch26
- b.eq L1
-; CHECK: b.eq L1 ; encoding: [0bAAA00000,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.ne L1
-; CHECK: b.ne L1 ; encoding: [0bAAA00001,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.cs L1
-; CHECK: b.hs L1 ; encoding: [0bAAA00010,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.cc L1
-; CHECK: b.lo L1 ; encoding: [0bAAA00011,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.mi L1
-; CHECK: b.mi L1 ; encoding: [0bAAA00100,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.pl L1
-; CHECK: b.pl L1 ; encoding: [0bAAA00101,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.vs L1
-; CHECK: b.vs L1 ; encoding: [0bAAA00110,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.vc L1
-; CHECK: b.vc L1 ; encoding: [0bAAA00111,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.hi L1
-; CHECK: b.hi L1 ; encoding: [0bAAA01000,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.ls L1
-; CHECK: b.ls L1 ; encoding: [0bAAA01001,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.ge L1
-; CHECK: b.ge L1 ; encoding: [0bAAA01010,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.lt L1
-; CHECK: b.lt L1 ; encoding: [0bAAA01011,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.gt L1
-; CHECK: b.gt L1 ; encoding: [0bAAA01100,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.le L1
-; CHECK: b.le L1 ; encoding: [0bAAA01101,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
- b.al L1
-; CHECK: b.al L1 ; encoding: [0bAAA01110,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
-L1:
- b #28
-; CHECK: b #28
- b.lt #28
-; CHECK: b.lt #28
- b.cc #1048572
-; CHECK: b.lo #1048572 ; encoding: [0xe3,0xff,0x7f,0x54]
- b #134217724
-; CHECK: b #134217724 ; encoding: [0xff,0xff,0xff,0x15]
- b #-134217728
-; CHECK: b #-134217728 ; encoding: [0x00,0x00,0x00,0x16]
-
-;-----------------------------------------------------------------------------
-; Compare-and-branch instructions.
-;-----------------------------------------------------------------------------
-
- cbz w1, foo
-; CHECK: encoding: [0bAAA00001,A,A,0x34]
- cbz x1, foo
-; CHECK: encoding: [0bAAA00001,A,A,0xb4]
- cbnz w2, foo
-; CHECK: encoding: [0bAAA00010,A,A,0x35]
- cbnz x2, foo
-; CHECK: encoding: [0bAAA00010,A,A,0xb5]
- cbz w1, #28
-; CHECK: cbz w1, #28
- cbz w20, #1048572
-; CHECK: cbz w20, #1048572 ; encoding: [0xf4,0xff,0x7f,0x34]
- cbnz x2, #-1048576
-; CHECK: cbnz x2, #-1048576 ; encoding: [0x02,0x00,0x80,0xb5]
-
-
-;-----------------------------------------------------------------------------
-; Bit-test-and-branch instructions.
-;-----------------------------------------------------------------------------
-
- tbz x1, #3, foo
-; CHECK: encoding: [0bAAA00001,A,0b00011AAA,0x36]
- tbnz x1, #63, foo
-; CHECK: encoding: [0bAAA00001,A,0b11111AAA,0xb7]
-
- tbz w1, #3, foo
-; CHECK: encoding: [0bAAA00001,A,0b00011AAA,0x36]
- tbnz w1, #31, foo
-; CHECK: encoding: [0bAAA00001,A,0b11111AAA,0x37]
-
- tbz w1, #3, #28
-; CHECK: tbz w1, #3, #28
- tbz w3, #5, #32764
-; CHECK: tbz w3, #5, #32764 ; encoding: [0xe3,0xff,0x2b,0x36]
- tbnz x3, #8, #-32768
-; CHECK: tbnz w3, #8, #-32768 ; encoding: [0x03,0x00,0x44,0x37]
-
-;-----------------------------------------------------------------------------
-; Exception generation instructions.
-;-----------------------------------------------------------------------------
-
- brk #1
-; CHECK: encoding: [0x20,0x00,0x20,0xd4]
- dcps1 #2
-; CHECK: encoding: [0x41,0x00,0xa0,0xd4]
- dcps2 #3
-; CHECK: encoding: [0x62,0x00,0xa0,0xd4]
- dcps3 #4
-; CHECK: encoding: [0x83,0x00,0xa0,0xd4]
- hlt #5
-; CHECK: encoding: [0xa0,0x00,0x40,0xd4]
- hvc #6
-; CHECK: encoding: [0xc2,0x00,0x00,0xd4]
- smc #7
-; CHECK: encoding: [0xe3,0x00,0x00,0xd4]
- svc #8
-; CHECK: encoding: [0x01,0x01,0x00,0xd4]
-
-; The immediate defaults to zero for DCPSn
- dcps1
- dcps2
- dcps3
-
-; CHECK: dcps1 ; encoding: [0x01,0x00,0xa0,0xd4]
-; CHECK: dcps2 ; encoding: [0x02,0x00,0xa0,0xd4]
-; CHECK: dcps3 ; encoding: [0x03,0x00,0xa0,0xd4]
-
Removed: llvm/trunk/test/MC/ARM64/condbr-without-dots.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/condbr-without-dots.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/condbr-without-dots.s (original)
+++ llvm/trunk/test/MC/ARM64/condbr-without-dots.s (removed)
@@ -1,37 +0,0 @@
-// RUN: llvm-mc -triple arm64-apple-ios -o - %s | FileCheck %s
-
- beq lbl
- bne lbl
- bcs lbl
- bhs lbl
- blo lbl
- bcc lbl
- bmi lbl
- bpl lbl
- bvs lbl
- bvc lbl
- bhi lbl
- bls lbl
- bge lbl
- blt lbl
- bgt lbl
- ble lbl
- bal lbl
-
-// CHECK: b.eq lbl
-// CHECK: b.ne lbl
-// CHECK: b.hs lbl
-// CHECK: b.hs lbl
-// CHECK: b.lo lbl
-// CHECK: b.lo lbl
-// CHECK: b.mi lbl
-// CHECK: b.pl lbl
-// CHECK: b.vs lbl
-// CHECK: b.vc lbl
-// CHECK: b.hi lbl
-// CHECK: b.ls lbl
-// CHECK: b.ge lbl
-// CHECK: b.lt lbl
-// CHECK: b.gt lbl
-// CHECK: b.le lbl
-// CHECK: b.al lbl
Removed: llvm/trunk/test/MC/ARM64/crypto.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/crypto.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/crypto.s (original)
+++ llvm/trunk/test/MC/ARM64/crypto.s (removed)
@@ -1,66 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -show-encoding -output-asm-variant=1 < %s | FileCheck %s
-
-foo:
- aese.16b v0, v1
- aesd.16b v0, v1
- aesmc.16b v0, v1
- aesimc.16b v0, v1
-
- sha1c.4s q0, s1, v2
- sha1p.4s q0, s1, v2
- sha1m.4s q0, s1, v2
- sha1su0.4s v0, v1, v2
- sha256h.4s q0, q1, v2
- sha256h2.4s q0, q1, v2
- sha256su1.4s v0, v1, v2
- sha1h s0, s1
- sha1su1.4s v0, v1
- sha256su0.4s v0, v1
-
-; CHECK: aese.16b v0, v1 ; encoding: [0x20,0x48,0x28,0x4e]
-; CHECK: aesd.16b v0, v1 ; encoding: [0x20,0x58,0x28,0x4e]
-; CHECK: aesmc.16b v0, v1 ; encoding: [0x20,0x68,0x28,0x4e]
-; CHECK: aesimc.16b v0, v1 ; encoding: [0x20,0x78,0x28,0x4e]
-
-; CHECK: sha1c.4s q0, s1, v2 ; encoding: [0x20,0x00,0x02,0x5e]
-; CHECK: sha1p.4s q0, s1, v2 ; encoding: [0x20,0x10,0x02,0x5e]
-; CHECK: sha1m.4s q0, s1, v2 ; encoding: [0x20,0x20,0x02,0x5e]
-; CHECK: sha1su0.4s v0, v1, v2 ; encoding: [0x20,0x30,0x02,0x5e]
-; CHECK: sha256h.4s q0, q1, v2 ; encoding: [0x20,0x40,0x02,0x5e]
-; CHECK: sha256h2.4s q0, q1, v2 ; encoding: [0x20,0x50,0x02,0x5e]
-; CHECK: sha256su1.4s v0, v1, v2 ; encoding: [0x20,0x60,0x02,0x5e]
-; CHECK: sha1h s0, s1 ; encoding: [0x20,0x08,0x28,0x5e]
-; CHECK: sha1su1.4s v0, v1 ; encoding: [0x20,0x18,0x28,0x5e]
-; CHECK: sha256su0.4s v0, v1 ; encoding: [0x20,0x28,0x28,0x5e]
-
- aese v2.16b, v3.16b
- aesd v5.16b, v7.16b
- aesmc v11.16b, v13.16b
- aesimc v17.16b, v19.16b
-
-; CHECK: aese.16b v2, v3 ; encoding: [0x62,0x48,0x28,0x4e]
-; CHECK: aesd.16b v5, v7 ; encoding: [0xe5,0x58,0x28,0x4e]
-; CHECK: aesmc.16b v11, v13 ; encoding: [0xab,0x69,0x28,0x4e]
-; CHECK: aesimc.16b v17, v19 ; encoding: [0x71,0x7a,0x28,0x4e]
-
- sha1c q23, s29, v3.4s
- sha1p q14, s15, v9.4s
- sha1m q2, s6, v5.4s
- sha1su0 v3.4s, v5.4s, v9.4s
- sha256h q2, q7, v18.4s
- sha256h2 q28, q18, v28.4s
- sha256su1 v4.4s, v5.4s, v9.4s
- sha1h s30, s0
- sha1su1 v10.4s, v21.4s
- sha256su0 v2.4s, v31.4s
-
-; CHECK: sha1c.4s q23, s29, v3 ; encoding: [0xb7,0x03,0x03,0x5e]
-; CHECK: sha1p.4s q14, s15, v9 ; encoding: [0xee,0x11,0x09,0x5e]
-; CHECK: sha1m.4s q2, s6, v5 ; encoding: [0xc2,0x20,0x05,0x5e]
-; CHECK: sha1su0.4s v3, v5, v9 ; encoding: [0xa3,0x30,0x09,0x5e]
-; CHECK: sha256h.4s q2, q7, v18 ; encoding: [0xe2,0x40,0x12,0x5e]
-; CHECK: sha256h2.4s q28, q18, v28 ; encoding: [0x5c,0x52,0x1c,0x5e]
-; CHECK: sha256su1.4s v4, v5, v9 ; encoding: [0xa4,0x60,0x09,0x5e]
-; CHECK: sha1h s30, s0 ; encoding: [0x1e,0x08,0x28,0x5e]
-; CHECK: sha1su1.4s v10, v21 ; encoding: [0xaa,0x1a,0x28,0x5e]
-; CHECK: sha256su0.4s v2, v31 ; encoding: [0xe2,0x2b,0x28,0x5e]
Removed: llvm/trunk/test/MC/ARM64/diagno-predicate.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/diagno-predicate.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/diagno-predicate.s (original)
+++ llvm/trunk/test/MC/ARM64/diagno-predicate.s (removed)
@@ -1,24 +0,0 @@
-// RUN: not llvm-mc -triple arm64-linux-gnu -mattr=-fp-armv8,-crc < %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
-
-
- fcvt d0, s0
-// CHECK-ERROR: error: instruction requires: fp-armv8
-// CHECK-ERROR-NEXT: fcvt d0, s0
-// CHECK-ERROR-NEXT: ^
-
- fmla v9.2s, v9.2s, v0.2s
-// CHECK-ERROR: error: instruction requires: neon
-// CHECK-ERROR-NEXT: fmla v9.2s, v9.2s, v0.2s
-// CHECK-ERROR-NEXT: ^
-
- pmull v0.1q, v1.1d, v2.1d
-// CHECK-ERROR: error: instruction requires: crypto
-// CHECK-ERROR-NEXT: pmull v0.1q, v1.1d, v2.1d
-// CHECK-ERROR-NEXT: ^
-
- crc32b w5, w7, w20
-// CHECK-ERROR: error: instruction requires: crc
-// CHECK-ERROR-NEXT: crc32b w5, w7, w20
-// CHECK-ERROR-NEXT: ^
-
Removed: llvm/trunk/test/MC/ARM64/diags.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/diags.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/diags.s (original)
+++ llvm/trunk/test/MC/ARM64/diags.s (removed)
@@ -1,392 +0,0 @@
-; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-foo:
-
-; The first should encode as an expression. The second should error expecting
-; a register.
- ldr x3, (foo + 4)
- ldr x3, [foo + 4]
-; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58]
-; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_arm64_ldr_pcrel_imm19
-; CHECK-ERRORS: error: invalid operand for instruction
-
-; The last argument should be flagged as an error. rdar://9576009
- ld4.8b {v0, v1, v2, v3}, [x0], #33
-; CHECK-ERRORS: error: invalid operand for instruction
-; CHECK-ERRORS: ld4.8b {v0, v1, v2, v3}, [x0], #33
-
-
- ldr x0, [x0, #804]
- ldr w0, [x0, #802]
- ldr x0, [x0, #804]!
- ldr w0, [w0, #301]!
- ldr x0, [x0], #804
- ldr w0, [w0], #301
-
- ldp w3, w4, [x5, #11]!
- ldp x3, x4, [x5, #12]!
- ldp q3, q4, [x5, #12]!
- ldp w3, w4, [x5], #11
- ldp x3, x4, [x5], #12
- ldp q3, q4, [x5], #12
-
- ldur x0, [x1, #-257]
-
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
-; CHECK-ERRORS: ldr x0, [x0, #804]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
-; CHECK-ERRORS: ldr w0, [x0, #802]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
-; CHECK-ERRORS: ldr x0, [x0, #804]!
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: invalid operand for instruction
-; CHECK-ERRORS: ldr w0, [w0, #301]!
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
-; CHECK-ERRORS: ldr x0, [x0], #804
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: invalid operand for instruction
-; CHECK-ERRORS: ldr w0, [w0], #301
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
-; CHECK-ERRORS: ldp w3, w4, [x5, #11]!
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
-; CHECK-ERRORS: ldp x3, x4, [x5, #12]!
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
-; CHECK-ERRORS: ldp q3, q4, [x5, #12]!
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
-; CHECK-ERRORS: ldp w3, w4, [x5], #11
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
-; CHECK-ERRORS: ldp x3, x4, [x5], #12
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
-; CHECK-ERRORS: ldp q3, q4, [x5], #12
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
-; CHECK-ERRORS: ldur x0, [x1, #-257]
-; CHECK-ERRORS: ^
-
-
-ldrb w1, [x3, w3, sxtw #4]
-ldrh w1, [x3, w3, sxtw #4]
-ldr w1, [x3, w3, sxtw #4]
-ldr x1, [x3, w3, sxtw #4]
-ldr b1, [x3, w3, sxtw #4]
-ldr h1, [x3, w3, sxtw #4]
-ldr s1, [x3, w3, sxtw #4]
-ldr d1, [x3, w3, sxtw #4]
-ldr q1, [x3, w3, sxtw #1]
-
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
-; CHECK-ERRORS:ldrb w1, [x3, w3, sxtw #4]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
-; CHECK-ERRORS:ldrh w1, [x3, w3, sxtw #4]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
-; CHECK-ERRORS:ldr w1, [x3, w3, sxtw #4]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
-; CHECK-ERRORS:ldr x1, [x3, w3, sxtw #4]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
-; CHECK-ERRORS:ldr b1, [x3, w3, sxtw #4]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
-; CHECK-ERRORS:ldr h1, [x3, w3, sxtw #4]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
-; CHECK-ERRORS:ldr s1, [x3, w3, sxtw #4]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
-; CHECK-ERRORS:ldr d1, [x3, w3, sxtw #4]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4
-; CHECK-ERRORS:ldr q1, [x3, w3, sxtw #1]
-; CHECK-ERRORS: ^
-
-; Check that register offset addressing modes only accept 32-bit offset
-; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
-; register.
- str d1, [x3, w3, sxtx #3]
- ldr s1, [x3, d3, sxtx #2]
-
-; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
-; CHECK-ERRORS: str d1, [x3, w3, sxtx #3]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
-; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2]
-; CHECK-ERRORS: ^
-
-; Shift immediates range checking.
- sqrshrn b4, h9, #10
- rshrn v9.8b, v11.8h, #17
- sqrshrn v7.4h, v8.4s, #39
- uqshrn2 v4.4s, v5.2d, #67
-
-; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
-; CHECK-ERRORS: sqrshrn b4, h9, #10
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
-; CHECK-ERRORS: rshrn v9.8b, v11.8h, #17
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: immediate must be an integer in range [1, 16].
-; CHECK-ERRORS: sqrshrn v7.4h, v8.4s, #39
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].
-; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67
-; CHECK-ERRORS: ^
-
-
- st1.s4 {v14, v15}, [x2], #32
-; CHECK-ERRORS: error: invalid type suffix for instruction
-; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32
-; CHECK-ERRORS: ^
-
-
-
-; Load pair instructions where Rt==Rt2 and writeback load/store instructions
-; where Rt==Rn or Rt2==Rn are unpredicatable.
- ldp x1, x2, [x2], #16
- ldp x2, x2, [x2], #16
- ldp w1, w2, [x2], #16
- ldp w2, w2, [x2], #16
- ldp x1, x1, [x2]
-
- ldr x2, [x2], #8
- ldr x2, [x2, #8]!
- ldr w2, [x2], #8
- ldr w2, [x2, #8]!
-
- str x2, [x2], #8
- str x2, [x2, #8]!
- str w2, [x2], #8
- str w2, [x2, #8]!
-
-; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
-; CHECK-ERRORS: ldp x1, x2, [x2], #16
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
-; CHECK-ERRORS: ldp x2, x2, [x2], #16
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
-; CHECK-ERRORS: ldp w1, w2, [x2], #16
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
-; CHECK-ERRORS: ldp w2, w2, [x2], #16
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
-; CHECK-ERRORS: ldp x1, x1, [x2]
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
-; CHECK-ERRORS: ldr x2, [x2], #8
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
-; CHECK-ERRORS: ldr x2, [x2, #8]!
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
-; CHECK-ERRORS: ldr w2, [x2], #8
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
-; CHECK-ERRORS: ldr w2, [x2, #8]!
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
-; CHECK-ERRORS: str x2, [x2], #8
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
-; CHECK-ERRORS: str x2, [x2, #8]!
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
-; CHECK-ERRORS: str w2, [x2], #8
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
-; CHECK-ERRORS: str w2, [x2, #8]!
-; CHECK-ERRORS: ^
-
-; The validity checking for shifted-immediate operands. rdar://13174476
-; Where the immediate is out of range.
- add w1, w2, w3, lsr #75
-
-; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
-; CHECK-ERRORS: add w1, w2, w3, lsr #75
-; CHECK-ERRORS: ^
-
-; logical instructions on 32-bit regs with shift > 31 is not legal
-orr w0, w0, w0, lsl #32
-; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
-; CHECK-ERRORS: orr w0, w0, w0, lsl #32
-; CHECK-ERRORS: ^
-eor w0, w0, w0, lsl #32
-; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
-; CHECK-ERRORS: eor w0, w0, w0, lsl #32
-; CHECK-ERRORS: ^
-and w0, w0, w0, lsl #32
-; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
-; CHECK-ERRORS: and w0, w0, w0, lsl #32
-; CHECK-ERRORS: ^
-ands w0, w0, w0, lsl #32
-; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
-; CHECK-ERRORS: ands w0, w0, w0, lsl #32
-; CHECK-ERRORS: ^
-
-; Relocated expressions should not be accepted for 32-bit adds or sub (imm)
-add w3, w5, sym at PAGEOFF
-; CHECK-ERRORS: error: invalid immediate expression
-; CHECK-ERRORS: add w3, w5, sym at PAGEOFF
-; CHECK-ERRORS: ^
-
-adds w3, w5, sym at PAGEOFF
-adds x9, x12, sym at PAGEOFF
-; CHECK-ERRORS: error: invalid immediate expression
-; CHECK-ERRORS: adds w3, w5, sym at PAGEOFF
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: invalid immediate expression
-; CHECK-ERRORS: adds x9, x12, sym at PAGEOFF
-; CHECK-ERRORS: ^
-
-sub x3, x5, sym at PAGEOFF
-sub w20, w30, sym at PAGEOFF
-; CHECK-ERRORS: error: invalid immediate expression
-; CHECK-ERRORS: sub x3, x5, sym at PAGEOFF
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: invalid immediate expression
-; CHECK-ERRORS: sub w20, w30, sym at PAGEOFF
-; CHECK-ERRORS: ^
-
-subs w9, w10, sym at PAGEOFF
-subs x20, x30, sym at PAGEOFF
-; CHECK-ERRORS: error: invalid immediate expression
-; CHECK-ERRORS: subs w9, w10, sym at PAGEOFF
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: invalid immediate expression
-; CHECK-ERRORS: subs x20, x30, sym at PAGEOFF
-; CHECK-ERRORS: ^
-
-tbl v0.8b, { v1 }, v0.8b
-tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
-tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
-tbx v2.8b, { v0 }, v6.8b
-; CHECK-ERRORS: error: invalid operand for instruction
-; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: invalid operand for instruction
-; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: invalid operand for instruction
-; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
-; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: invalid operand for instruction
-; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b
-; CHECK-ERRORS: ^
-
-b.c #0x4
-; CHECK-ERRORS: error: invalid condition code
-; CHECK-ERRORS: b.c #0x4
-; CHECK-ERRORS: ^
-
-ic ialluis, x0
-; CHECK-ERRORS: error: specified ic op does not use a register
-ic iallu, x0
-; CHECK-ERRORS: error: specified ic op does not use a register
-ic ivau
-; CHECK-ERRORS: error: specified ic op requires a register
-
-dc zva
-; CHECK-ERRORS: error: specified dc op requires a register
-dc ivac
-; CHECK-ERRORS: error: specified dc op requires a register
-dc isw
-; CHECK-ERRORS: error: specified dc op requires a register
-dc cvac
-; CHECK-ERRORS: error: specified dc op requires a register
-dc csw
-; CHECK-ERRORS: error: specified dc op requires a register
-dc cvau
-; CHECK-ERRORS: error: specified dc op requires a register
-dc civac
-; CHECK-ERRORS: error: specified dc op requires a register
-dc cisw
-; CHECK-ERRORS: error: specified dc op requires a register
-
-at s1e1r
-; CHECK-ERRORS: error: specified at op requires a register
-at s1e2r
-; CHECK-ERRORS: error: specified at op requires a register
-at s1e3r
-; CHECK-ERRORS: error: specified at op requires a register
-at s1e1w
-; CHECK-ERRORS: error: specified at op requires a register
-at s1e2w
-; CHECK-ERRORS: error: specified at op requires a register
-at s1e3w
-; CHECK-ERRORS: error: specified at op requires a register
-at s1e0r
-; CHECK-ERRORS: error: specified at op requires a register
-at s1e0w
-; CHECK-ERRORS: error: specified at op requires a register
-at s12e1r
-; CHECK-ERRORS: error: specified at op requires a register
-at s12e1w
-; CHECK-ERRORS: error: specified at op requires a register
-at s12e0r
-; CHECK-ERRORS: error: specified at op requires a register
-at s12e0w
-; CHECK-ERRORS: error: specified at op requires a register
-
-tlbi vmalle1is, x0
-; CHECK-ERRORS: error: specified tlbi op does not use a register
-tlbi vmalle1, x0
-; CHECK-ERRORS: error: specified tlbi op does not use a register
-tlbi alle1is, x0
-; CHECK-ERRORS: error: specified tlbi op does not use a register
-tlbi alle2is, x0
-; CHECK-ERRORS: error: specified tlbi op does not use a register
-tlbi alle3is, x0
-; CHECK-ERRORS: error: specified tlbi op does not use a register
-tlbi alle1, x0
-; CHECK-ERRORS: error: specified tlbi op does not use a register
-tlbi alle2, x0
-; CHECK-ERRORS: error: specified tlbi op does not use a register
-tlbi alle3, x0
-; CHECK-ERRORS: error: specified tlbi op does not use a register
-tlbi vae1is
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vae2is
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vae3is
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi aside1is
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vaae1is
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vale1is
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vaale1is
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vale2is
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vale3is
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vae1
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vae2
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vae3
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi aside1
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vaae1
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vale1
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vale2
-; CHECK-ERRORS: error: specified tlbi op requires a register
-tlbi vale3
-; CHECK-ERRORS: error: specified tlbi op requires a register
Removed: llvm/trunk/test/MC/ARM64/directive_loh.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/directive_loh.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/directive_loh.s (original)
+++ llvm/trunk/test/MC/ARM64/directive_loh.s (removed)
@@ -1,93 +0,0 @@
-# RUN: not llvm-mc -triple arm64-apple-darwin < %s 2> %t | FileCheck %s
-# RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-.globl _fct1
-_fct1:
- L1:
- L2:
- L3:
- L4:
- ret lr;
-
-# Known LOHs with:
-# - Regular syntax.
-# - Alternative syntax.
-
-# CHECK: .loh AdrpAdrp L1, L2
-# CHECK: .loh AdrpAdrp L1, L2
-.loh AdrpAdrp L1, L2
-.loh 1 L1, L2
-
-# CHECK: .loh AdrpLdr L1, L2
-# CHECK: .loh AdrpLdr L1, L2
-.loh AdrpLdr L1, L2
-.loh 2 L1, L2
-
-# CHECK: .loh AdrpAddLdr L1, L2, L3
-# CHECK: .loh AdrpAddLdr L1, L2, L3
-.loh AdrpAddLdr L1, L2, L3
-.loh 3 L1, L2, L3
-
-# CHECK: .loh AdrpLdrGotLdr L1, L2, L3
-# CHECK: .loh AdrpLdrGotLdr L1, L2, L3
-.loh AdrpLdrGotLdr L1, L2, L3
-.loh 4 L1, L2, L3
-
-# CHECK: .loh AdrpAddStr L1, L2, L3
-# CHECK: .loh AdrpAddStr L1, L2, L3
-.loh AdrpAddStr L1, L2, L3
-.loh 5 L1, L2, L3
-
-# CHECK: .loh AdrpLdrGotStr L1, L2, L3
-# CHECK: .loh AdrpLdrGotStr L1, L2, L3
-.loh AdrpLdrGotStr L1, L2, L3
-.loh 6 L1, L2, L3
-
-# CHECK: .loh AdrpAdd L1, L2
-# CHECK: .loh AdrpAdd L1, L2
-.loh AdrpAdd L1, L2
-.loh 7 L1, L2
-
-# CHECK: .loh AdrpLdrGot L1, L2
-# CHECK: .loh AdrpLdrGot L1, L2
-.loh AdrpLdrGot L1, L2
-.loh 8 L1, L2
-
-# End Known LOHs.
-
-### Errors Check ####
-
-# Unknown textual identifier.
-# CHECK-ERRORS: error: invalid identifier in directive
-# CHECK-ERRORS-NEXT: .loh Unknown
-# CHECK-ERRORS-NEXT: ^
-.loh Unknown
-# Unknown numeric identifier.
-# CHECK-ERRORS: error: invalid numeric identifier in directive
-# CHECK-ERRORS-NEXT: .loh 153, L1
-# CHECK-ERRORS-NEXT: ^
-.loh 153, L1
-
-# Too much arguments.
-# CHECK-ERRORS: error: unexpected token in '.loh' directive
-# CHECK-ERRORS-NEXT: .loh AdrpAdrp L1, L2, L3
-# CHECK-ERRORS-NEXT: ^
-.loh AdrpAdrp L1, L2, L3
-
-# Too much arguments with alternative syntax.
-# CHECK-ERRORS: error: unexpected token in '.loh' directive
-# CHECK-ERRORS-NEXT: .loh 1 L1, L2, L3
-# CHECK-ERRORS-NEXT: ^
-.loh 1 L1, L2, L3
-
-# Too few argumets.
-# CHECK-ERRORS: error: unexpected token in '.loh' directive
-# CHECK-ERRORS-NEXT: .loh AdrpAdrp L1
-# CHECK-ERRORS-NEXT: ^
-.loh AdrpAdrp L1
-
-# Too few argumets with alternative syntax.
-# CHECK-ERRORS: error: unexpected token in '.loh' directive
-# CHECK-ERRORS-NEXT: .loh 1 L1
-# CHECK-ERRORS-NEXT: ^
-.loh 1 L1
Removed: llvm/trunk/test/MC/ARM64/elf-reloc-condbr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/elf-reloc-condbr.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/elf-reloc-condbr.s (original)
+++ llvm/trunk/test/MC/ARM64/elf-reloc-condbr.s (removed)
@@ -1,10 +0,0 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \
-// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
-
- b.eq somewhere
-
-// OBJ: Relocations [
-// OBJ-NEXT: Section (2) .rela.text {
-// OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0
-// OBJ-NEXT: }
-// OBJ-NEXT: ]
Removed: llvm/trunk/test/MC/ARM64/elf-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/elf-relocs.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/elf-relocs.s (original)
+++ llvm/trunk/test/MC/ARM64/elf-relocs.s (removed)
@@ -1,249 +0,0 @@
-// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
-// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump -triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ
-
- add x0, x2, #:lo12:sym
-// CHECK: add x0, x2, :lo12:sym
-// CHECK-OBJ: 0 R_AARCH64_ADD_ABS_LO12_NC sym
-
- add x5, x7, #:dtprel_lo12:sym
-// CHECK: add x5, x7, :dtprel_lo12:sym
-// CHECK-OBJ: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
-
- add x9, x12, #:dtprel_lo12_nc:sym
-// CHECK: add x9, x12, :dtprel_lo12_nc:sym
-// CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
-
- add x20, x30, #:tprel_lo12:sym
-// CHECK: add x20, x30, :tprel_lo12:sym
-// CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
-
- add x9, x12, #:tprel_lo12_nc:sym
-// CHECK: add x9, x12, :tprel_lo12_nc:sym
-// CHECK-OBJ: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
-
- add x5, x0, #:tlsdesc_lo12:sym
-// CHECK: add x5, x0, :tlsdesc_lo12:sym
-// CHECK-OBJ: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
-
- add x0, x2, #:lo12:sym+8
-// CHECK: add x0, x2, :lo12:sym
-// CHECK-OBJ: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
-
- add x5, x7, #:dtprel_lo12:sym+1
-// CHECK: add x5, x7, :dtprel_lo12:sym+1
-// CHECK-OBJ: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
-
- add x9, x12, #:dtprel_lo12_nc:sym+2
-// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
-// CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
-
- add x20, x30, #:tprel_lo12:sym+12
-// CHECK: add x20, x30, :tprel_lo12:sym+12
-// CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
-
- add x9, x12, #:tprel_lo12_nc:sym+54
-// CHECK: add x9, x12, :tprel_lo12_nc:sym+54
-// CHECK-OBJ: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
-
- add x5, x0, #:tlsdesc_lo12:sym+70
-// CHECK: add x5, x0, :tlsdesc_lo12:sym+70
-// CHECK-OBJ: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
-
- .hword sym + 4 - .
-// CHECK-OBJ: 30 R_AARCH64_PREL16 sym+4
- .word sym - . + 8
-// CHECK-OBJ: 32 R_AARCH64_PREL32 sym+8
- .xword sym-.
-// CHECK-OBJ: 36 R_AARCH64_PREL64 sym{{$}}
-
- .hword sym
-// CHECK-OBJ: 3e R_AARCH64_ABS16 sym
- .word sym+1
-// CHECK-OBJ: 40 R_AARCH64_ABS32 sym+1
- .xword sym+16
-// CHECK-OBJ: 44 R_AARCH64_ABS64 sym+16
-
- adrp x0, sym
-// CHECK: adrp x0, sym
-// CHECK-OBJ: 4c R_AARCH64_ADR_PREL_PG_HI21 sym
-
- adrp x15, :got:sym
-// CHECK: adrp x15, :got:sym
-// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym
-
- adrp x29, :gottprel:sym
-// CHECK: adrp x29, :gottprel:sym
-// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
-
- adrp x2, :tlsdesc:sym
-// CHECK: adrp x2, :tlsdesc:sym
-// CHECK-OBJ: 58 R_AARCH64_TLSDESC_ADR_PAGE sym
-
- // LLVM is not competent enough to do this relocation because the
- // page boundary could occur anywhere after linking. A relocation
- // is needed.
- adrp x3, trickQuestion
- .global trickQuestion
-trickQuestion:
-// CHECK: adrp x3, trickQuestion
-// CHECK-OBJ: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
-
- ldrb w2, [x3, :lo12:sym]
- ldrsb w5, [x7, #:lo12:sym]
- ldrsb x11, [x13, :lo12:sym]
- ldr b17, [x19, #:lo12:sym]
-// CHECK: ldrb w2, [x3, :lo12:sym]
-// CHECK: ldrsb w5, [x7, :lo12:sym]
-// CHECK: ldrsb x11, [x13, :lo12:sym]
-// CHECK: ldr b17, [x19, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
-
- ldrb w23, [x29, #:dtprel_lo12_nc:sym]
- ldrsb w23, [x19, #:dtprel_lo12:sym]
- ldrsb x17, [x13, :dtprel_lo12_nc:sym]
- ldr b11, [x7, #:dtprel_lo12:sym]
-// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
-// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
-// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
-// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
-
- ldrb w1, [x2, :tprel_lo12:sym]
- ldrsb w3, [x4, #:tprel_lo12_nc:sym]
- ldrsb x5, [x6, :tprel_lo12:sym]
- ldr b7, [x8, #:tprel_lo12_nc:sym]
-// CHECK: ldrb w1, [x2, :tprel_lo12:sym]
-// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
-// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
-// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
-
- ldrh w2, [x3, #:lo12:sym]
- ldrsh w5, [x7, :lo12:sym]
- ldrsh x11, [x13, #:lo12:sym]
- ldr h17, [x19, :lo12:sym]
-// CHECK: ldrh w2, [x3, :lo12:sym]
-// CHECK: ldrsh w5, [x7, :lo12:sym]
-// CHECK: ldrsh x11, [x13, :lo12:sym]
-// CHECK: ldr h17, [x19, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
-
- ldrh w23, [x29, #:dtprel_lo12_nc:sym]
- ldrsh w23, [x19, :dtprel_lo12:sym]
- ldrsh x17, [x13, :dtprel_lo12_nc:sym]
- ldr h11, [x7, #:dtprel_lo12:sym]
-// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
-// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
-// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
-// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
-
- ldrh w1, [x2, :tprel_lo12:sym]
- ldrsh w3, [x4, #:tprel_lo12_nc:sym]
- ldrsh x5, [x6, :tprel_lo12:sym]
- ldr h7, [x8, #:tprel_lo12_nc:sym]
-// CHECK: ldrh w1, [x2, :tprel_lo12:sym]
-// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
-// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
-// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
-
- ldr w1, [x2, #:lo12:sym]
- ldrsw x3, [x4, #:lo12:sym]
- ldr s4, [x5, :lo12:sym]
-// CHECK: ldr w1, [x2, :lo12:sym]
-// CHECK: ldrsw x3, [x4, :lo12:sym]
-// CHECK: ldr s4, [x5, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
-
- ldr w1, [x2, :dtprel_lo12:sym]
- ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
- ldr s4, [x5, #:dtprel_lo12_nc:sym]
-// CHECK: ldr w1, [x2, :dtprel_lo12:sym]
-// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
-// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
-
-
- ldr w1, [x2, #:tprel_lo12:sym]
- ldrsw x3, [x4, :tprel_lo12_nc:sym]
- ldr s4, [x5, :tprel_lo12_nc:sym]
-// CHECK: ldr w1, [x2, :tprel_lo12:sym]
-// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
-// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
-
- ldr x28, [x27, :lo12:sym]
- ldr d26, [x25, #:lo12:sym]
-// CHECK: ldr x28, [x27, :lo12:sym]
-// CHECK: ldr d26, [x25, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
-
- ldr x24, [x23, #:got_lo12:sym]
- ldr d22, [x21, :got_lo12:sym]
-// CHECK: ldr x24, [x23, :got_lo12:sym]
-// CHECK: ldr d22, [x21, :got_lo12:sym]
-// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
-
- ldr x24, [x23, :dtprel_lo12_nc:sym]
- ldr d22, [x21, #:dtprel_lo12:sym]
-// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
-// CHECK: ldr d22, [x21, :dtprel_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
-
- ldr x24, [x23, #:tprel_lo12:sym]
- ldr d22, [x21, :tprel_lo12_nc:sym]
-// CHECK: ldr x24, [x23, :tprel_lo12:sym]
-// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym
-
- ldr x24, [x23, :gottprel_lo12:sym]
- ldr d22, [x21, #:gottprel_lo12:sym]
-// CHECK: ldr x24, [x23, :gottprel_lo12:sym]
-// CHECK: ldr d22, [x21, :gottprel_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
-
- ldr x24, [x23, #:tlsdesc_lo12:sym]
- ldr d22, [x21, :tlsdesc_lo12:sym]
-// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
-// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
-
- ldr q20, [x19, #:lo12:sym]
-// CHECK: ldr q20, [x19, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST128_ABS_LO12_NC sym
-
-// Since relocated instructions print without a '#', that syntax should
-// certainly be accepted when assembling.
- add x3, x5, :lo12:imm
-// CHECK: add x3, x5, :lo12:imm
Removed: llvm/trunk/test/MC/ARM64/fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/fp-encoding.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/fp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM64/fp-encoding.s (removed)
@@ -1,443 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -show-encoding -output-asm-variant=1 < %s | FileCheck %s
-
-foo:
-;-----------------------------------------------------------------------------
-; Floating-point arithmetic
-;-----------------------------------------------------------------------------
-
- fabs s1, s2
- fabs d1, d2
-
-; CHECK: fabs s1, s2 ; encoding: [0x41,0xc0,0x20,0x1e]
-; CHECK: fabs d1, d2 ; encoding: [0x41,0xc0,0x60,0x1e]
-
- fadd s1, s2, s3
- fadd d1, d2, d3
-
-; CHECK: fadd s1, s2, s3 ; encoding: [0x41,0x28,0x23,0x1e]
-; CHECK: fadd d1, d2, d3 ; encoding: [0x41,0x28,0x63,0x1e]
-
- fdiv s1, s2, s3
- fdiv d1, d2, d3
-
-; CHECK: fdiv s1, s2, s3 ; encoding: [0x41,0x18,0x23,0x1e]
-; CHECK: fdiv d1, d2, d3 ; encoding: [0x41,0x18,0x63,0x1e]
-
- fmadd s1, s2, s3, s4
- fmadd d1, d2, d3, d4
-
-; CHECK: fmadd s1, s2, s3, s4 ; encoding: [0x41,0x10,0x03,0x1f]
-; CHECK: fmadd d1, d2, d3, d4 ; encoding: [0x41,0x10,0x43,0x1f]
-
- fmax s1, s2, s3
- fmax d1, d2, d3
- fmaxnm s1, s2, s3
- fmaxnm d1, d2, d3
-
-; CHECK: fmax s1, s2, s3 ; encoding: [0x41,0x48,0x23,0x1e]
-; CHECK: fmax d1, d2, d3 ; encoding: [0x41,0x48,0x63,0x1e]
-; CHECK: fmaxnm s1, s2, s3 ; encoding: [0x41,0x68,0x23,0x1e]
-; CHECK: fmaxnm d1, d2, d3 ; encoding: [0x41,0x68,0x63,0x1e]
-
- fmin s1, s2, s3
- fmin d1, d2, d3
- fminnm s1, s2, s3
- fminnm d1, d2, d3
-
-; CHECK: fmin s1, s2, s3 ; encoding: [0x41,0x58,0x23,0x1e]
-; CHECK: fmin d1, d2, d3 ; encoding: [0x41,0x58,0x63,0x1e]
-; CHECK: fminnm s1, s2, s3 ; encoding: [0x41,0x78,0x23,0x1e]
-; CHECK: fminnm d1, d2, d3 ; encoding: [0x41,0x78,0x63,0x1e]
-
- fmsub s1, s2, s3, s4
- fmsub d1, d2, d3, d4
-
-; CHECK: fmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x03,0x1f]
-; CHECK: fmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x43,0x1f]
-
- fmul s1, s2, s3
- fmul d1, d2, d3
-
-; CHECK: fmul s1, s2, s3 ; encoding: [0x41,0x08,0x23,0x1e]
-; CHECK: fmul d1, d2, d3 ; encoding: [0x41,0x08,0x63,0x1e]
-
- fneg s1, s2
- fneg d1, d2
-
-; CHECK: fneg s1, s2 ; encoding: [0x41,0x40,0x21,0x1e]
-; CHECK: fneg d1, d2 ; encoding: [0x41,0x40,0x61,0x1e]
-
- fnmadd s1, s2, s3, s4
- fnmadd d1, d2, d3, d4
-
-; CHECK: fnmadd s1, s2, s3, s4 ; encoding: [0x41,0x10,0x23,0x1f]
-; CHECK: fnmadd d1, d2, d3, d4 ; encoding: [0x41,0x10,0x63,0x1f]
-
- fnmsub s1, s2, s3, s4
- fnmsub d1, d2, d3, d4
-
-; CHECK: fnmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x23,0x1f]
-; CHECK: fnmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x63,0x1f]
-
- fnmul s1, s2, s3
- fnmul d1, d2, d3
-
-; CHECK: fnmul s1, s2, s3 ; encoding: [0x41,0x88,0x23,0x1e]
-; CHECK: fnmul d1, d2, d3 ; encoding: [0x41,0x88,0x63,0x1e]
-
- fsqrt s1, s2
- fsqrt d1, d2
-
-; CHECK: fsqrt s1, s2 ; encoding: [0x41,0xc0,0x21,0x1e]
-; CHECK: fsqrt d1, d2 ; encoding: [0x41,0xc0,0x61,0x1e]
-
- fsub s1, s2, s3
- fsub d1, d2, d3
-
-; CHECK: fsub s1, s2, s3 ; encoding: [0x41,0x38,0x23,0x1e]
-; CHECK: fsub d1, d2, d3 ; encoding: [0x41,0x38,0x63,0x1e]
-
-;-----------------------------------------------------------------------------
-; Floating-point comparison
-;-----------------------------------------------------------------------------
-
- fccmp s1, s2, #0, eq
- fccmp d1, d2, #0, eq
- fccmpe s1, s2, #0, eq
- fccmpe d1, d2, #0, eq
-
-; CHECK: fccmp s1, s2, #0, eq ; encoding: [0x20,0x04,0x22,0x1e]
-; CHECK: fccmp d1, d2, #0, eq ; encoding: [0x20,0x04,0x62,0x1e]
-; CHECK: fccmpe s1, s2, #0, eq ; encoding: [0x30,0x04,0x22,0x1e]
-; CHECK: fccmpe d1, d2, #0, eq ; encoding: [0x30,0x04,0x62,0x1e]
-
- fcmp s1, s2
- fcmp d1, d2
- fcmp s1, #0.0
- fcmp d1, #0.0
- fcmpe s1, s2
- fcmpe d1, d2
- fcmpe s1, #0.0
- fcmpe d1, #0.0
-
-; CHECK: fcmp s1, s2 ; encoding: [0x20,0x20,0x22,0x1e]
-; CHECK: fcmp d1, d2 ; encoding: [0x20,0x20,0x62,0x1e]
-; CHECK: fcmp s1, #0.0 ; encoding: [0x28,0x20,0x20,0x1e]
-; CHECK: fcmp d1, #0.0 ; encoding: [0x28,0x20,0x60,0x1e]
-; CHECK: fcmpe s1, s2 ; encoding: [0x30,0x20,0x22,0x1e]
-; CHECK: fcmpe d1, d2 ; encoding: [0x30,0x20,0x62,0x1e]
-; CHECK: fcmpe s1, #0.0 ; encoding: [0x38,0x20,0x20,0x1e]
-; CHECK: fcmpe d1, #0.0 ; encoding: [0x38,0x20,0x60,0x1e]
-
-;-----------------------------------------------------------------------------
-; Floating-point conditional select
-;-----------------------------------------------------------------------------
-
- fcsel s1, s2, s3, eq
- fcsel d1, d2, d3, eq
-
-; CHECK: fcsel s1, s2, s3, eq ; encoding: [0x41,0x0c,0x23,0x1e]
-; CHECK: fcsel d1, d2, d3, eq ; encoding: [0x41,0x0c,0x63,0x1e]
-
-;-----------------------------------------------------------------------------
-; Floating-point convert
-;-----------------------------------------------------------------------------
-
- fcvt h1, d2
- fcvt s1, d2
- fcvt d1, h2
- fcvt s1, h2
- fcvt d1, s2
- fcvt h1, s2
-
-; CHECK: fcvt h1, d2 ; encoding: [0x41,0xc0,0x63,0x1e]
-; CHECK: fcvt s1, d2 ; encoding: [0x41,0x40,0x62,0x1e]
-; CHECK: fcvt d1, h2 ; encoding: [0x41,0xc0,0xe2,0x1e]
-; CHECK: fcvt s1, h2 ; encoding: [0x41,0x40,0xe2,0x1e]
-; CHECK: fcvt d1, s2 ; encoding: [0x41,0xc0,0x22,0x1e]
-; CHECK: fcvt h1, s2 ; encoding: [0x41,0xc0,0x23,0x1e]
-
- fcvtas w1, d2
- fcvtas x1, d2
- fcvtas w1, s2
- fcvtas x1, s2
-
-; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e]
-; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e]
-; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e]
-; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e]
-
- fcvtau w1, s2
- fcvtau w1, d2
- fcvtau x1, s2
- fcvtau x1, d2
-
-; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e]
-; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e]
-; CHECK: fcvtau x1, s2 ; encoding: [0x41,0x00,0x25,0x9e]
-; CHECK: fcvtau x1, d2 ; encoding: [0x41,0x00,0x65,0x9e]
-
- fcvtms w1, s2
- fcvtms w1, d2
- fcvtms x1, s2
- fcvtms x1, d2
-
-; CHECK: fcvtms w1, s2 ; encoding: [0x41,0x00,0x30,0x1e]
-; CHECK: fcvtms w1, d2 ; encoding: [0x41,0x00,0x70,0x1e]
-; CHECK: fcvtms x1, s2 ; encoding: [0x41,0x00,0x30,0x9e]
-; CHECK: fcvtms x1, d2 ; encoding: [0x41,0x00,0x70,0x9e]
-
- fcvtmu w1, s2
- fcvtmu w1, d2
- fcvtmu x1, s2
- fcvtmu x1, d2
-
-; CHECK: fcvtmu w1, s2 ; encoding: [0x41,0x00,0x31,0x1e]
-; CHECK: fcvtmu w1, d2 ; encoding: [0x41,0x00,0x71,0x1e]
-; CHECK: fcvtmu x1, s2 ; encoding: [0x41,0x00,0x31,0x9e]
-; CHECK: fcvtmu x1, d2 ; encoding: [0x41,0x00,0x71,0x9e]
-
- fcvtns w1, s2
- fcvtns w1, d2
- fcvtns x1, s2
- fcvtns x1, d2
-
-; CHECK: fcvtns w1, s2 ; encoding: [0x41,0x00,0x20,0x1e]
-; CHECK: fcvtns w1, d2 ; encoding: [0x41,0x00,0x60,0x1e]
-; CHECK: fcvtns x1, s2 ; encoding: [0x41,0x00,0x20,0x9e]
-; CHECK: fcvtns x1, d2 ; encoding: [0x41,0x00,0x60,0x9e]
-
- fcvtnu w1, s2
- fcvtnu w1, d2
- fcvtnu x1, s2
- fcvtnu x1, d2
-
-; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e]
-; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e]
-; CHECK: fcvtnu x1, s2 ; encoding: [0x41,0x00,0x21,0x9e]
-; CHECK: fcvtnu x1, d2 ; encoding: [0x41,0x00,0x61,0x9e]
-
- fcvtps w1, s2
- fcvtps w1, d2
- fcvtps x1, s2
- fcvtps x1, d2
-
-; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e]
-; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e]
-; CHECK: fcvtps x1, s2 ; encoding: [0x41,0x00,0x28,0x9e]
-; CHECK: fcvtps x1, d2 ; encoding: [0x41,0x00,0x68,0x9e]
-
- fcvtpu w1, s2
- fcvtpu w1, d2
- fcvtpu x1, s2
- fcvtpu x1, d2
-
-; CHECK: fcvtpu w1, s2 ; encoding: [0x41,0x00,0x29,0x1e]
-; CHECK: fcvtpu w1, d2 ; encoding: [0x41,0x00,0x69,0x1e]
-; CHECK: fcvtpu x1, s2 ; encoding: [0x41,0x00,0x29,0x9e]
-; CHECK: fcvtpu x1, d2 ; encoding: [0x41,0x00,0x69,0x9e]
-
- fcvtzs w1, s2
- fcvtzs w1, s2, #1
- fcvtzs w1, d2
- fcvtzs w1, d2, #1
- fcvtzs x1, s2
- fcvtzs x1, s2, #1
- fcvtzs x1, d2
- fcvtzs x1, d2, #1
-
-; CHECK: fcvtzs w1, s2 ; encoding: [0x41,0x00,0x38,0x1e]
-; CHECK: fcvtzs w1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x1e]
-; CHECK: fcvtzs w1, d2 ; encoding: [0x41,0x00,0x78,0x1e]
-; CHECK: fcvtzs w1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x1e]
-; CHECK: fcvtzs x1, s2 ; encoding: [0x41,0x00,0x38,0x9e]
-; CHECK: fcvtzs x1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x9e]
-; CHECK: fcvtzs x1, d2 ; encoding: [0x41,0x00,0x78,0x9e]
-; CHECK: fcvtzs x1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x9e]
-
- fcvtzu w1, s2
- fcvtzu w1, s2, #1
- fcvtzu w1, d2
- fcvtzu w1, d2, #1
- fcvtzu x1, s2
- fcvtzu x1, s2, #1
- fcvtzu x1, d2
- fcvtzu x1, d2, #1
-
-; CHECK: fcvtzu w1, s2 ; encoding: [0x41,0x00,0x39,0x1e]
-; CHECK: fcvtzu w1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x1e]
-; CHECK: fcvtzu w1, d2 ; encoding: [0x41,0x00,0x79,0x1e]
-; CHECK: fcvtzu w1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x1e]
-; CHECK: fcvtzu x1, s2 ; encoding: [0x41,0x00,0x39,0x9e]
-; CHECK: fcvtzu x1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x9e]
-; CHECK: fcvtzu x1, d2 ; encoding: [0x41,0x00,0x79,0x9e]
-; CHECK: fcvtzu x1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x9e]
-
- scvtf s1, w2
- scvtf s1, w2, #1
- scvtf d1, w2
- scvtf d1, w2, #1
- scvtf s1, x2
- scvtf s1, x2, #1
- scvtf d1, x2
- scvtf d1, x2, #1
-
-; CHECK: scvtf s1, w2 ; encoding: [0x41,0x00,0x22,0x1e]
-; CHECK: scvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x02,0x1e]
-; CHECK: scvtf d1, w2 ; encoding: [0x41,0x00,0x62,0x1e]
-; CHECK: scvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x42,0x1e]
-; CHECK: scvtf s1, x2 ; encoding: [0x41,0x00,0x22,0x9e]
-; CHECK: scvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x02,0x9e]
-; CHECK: scvtf d1, x2 ; encoding: [0x41,0x00,0x62,0x9e]
-; CHECK: scvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x42,0x9e]
-
- ucvtf s1, w2
- ucvtf s1, w2, #1
- ucvtf d1, w2
- ucvtf d1, w2, #1
- ucvtf s1, x2
- ucvtf s1, x2, #1
- ucvtf d1, x2
- ucvtf d1, x2, #1
-
-; CHECK: ucvtf s1, w2 ; encoding: [0x41,0x00,0x23,0x1e]
-; CHECK: ucvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x03,0x1e]
-; CHECK: ucvtf d1, w2 ; encoding: [0x41,0x00,0x63,0x1e]
-; CHECK: ucvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x43,0x1e]
-; CHECK: ucvtf s1, x2 ; encoding: [0x41,0x00,0x23,0x9e]
-; CHECK: ucvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x03,0x9e]
-; CHECK: ucvtf d1, x2 ; encoding: [0x41,0x00,0x63,0x9e]
-; CHECK: ucvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x43,0x9e]
-
-;-----------------------------------------------------------------------------
-; Floating-point move
-;-----------------------------------------------------------------------------
-
- fmov s1, w2
- fmov w1, s2
- fmov d1, x2
- fmov x1, d2
-
-; CHECK: fmov s1, w2 ; encoding: [0x41,0x00,0x27,0x1e]
-; CHECK: fmov w1, s2 ; encoding: [0x41,0x00,0x26,0x1e]
-; CHECK: fmov d1, x2 ; encoding: [0x41,0x00,0x67,0x9e]
-; CHECK: fmov x1, d2 ; encoding: [0x41,0x00,0x66,0x9e]
-
- fmov s1, #0.125
- fmov s1, #0x40
- fmov d1, #0.125
- fmov d1, #0x40
- fmov d1, #-4.843750e-01
- fmov d1, #4.843750e-01
- fmov d3, #3
- fmov s2, #0.0
- fmov d2, #0.0
-
-; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e]
-; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e]
-; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e]
-; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e]
-; CHECK: fmov d1, #-0.48437500 ; encoding: [0x01,0xf0,0x7b,0x1e]
-; CHECK: fmov d1, #0.48437500 ; encoding: [0x01,0xf0,0x6b,0x1e]
-; CHECK: fmov d3, #3.00000000 ; encoding: [0x03,0x10,0x61,0x1e]
-; CHECK: fmov s2, wzr ; encoding: [0xe2,0x03,0x27,0x1e]
-; CHECK: fmov d2, xzr ; encoding: [0xe2,0x03,0x67,0x9e]
-
- fmov s1, s2
- fmov d1, d2
-
-; CHECK: fmov s1, s2 ; encoding: [0x41,0x40,0x20,0x1e]
-; CHECK: fmov d1, d2 ; encoding: [0x41,0x40,0x60,0x1e]
-
-
- fmov x2, v5.d[1]
- fmov.d x9, v7[1]
- fmov v1.d[1], x1
- fmov.d v8[1], x6
-
-; CHECK: fmov.d x2, v5[1] ; encoding: [0xa2,0x00,0xae,0x9e]
-; CHECK: fmov.d x9, v7[1] ; encoding: [0xe9,0x00,0xae,0x9e]
-; CHECK: fmov.d v1[1], x1 ; encoding: [0x21,0x00,0xaf,0x9e]
-; CHECK: fmov.d v8[1], x6 ; encoding: [0xc8,0x00,0xaf,0x9e]
-
-
-;-----------------------------------------------------------------------------
-; Floating-point round to integral
-;-----------------------------------------------------------------------------
-
- frinta s1, s2
- frinta d1, d2
-
-; CHECK: frinta s1, s2 ; encoding: [0x41,0x40,0x26,0x1e]
-; CHECK: frinta d1, d2 ; encoding: [0x41,0x40,0x66,0x1e]
-
- frinti s1, s2
- frinti d1, d2
-
-; CHECK: frinti s1, s2 ; encoding: [0x41,0xc0,0x27,0x1e]
-; CHECK: frinti d1, d2 ; encoding: [0x41,0xc0,0x67,0x1e]
-
- frintm s1, s2
- frintm d1, d2
-
-; CHECK: frintm s1, s2 ; encoding: [0x41,0x40,0x25,0x1e]
-; CHECK: frintm d1, d2 ; encoding: [0x41,0x40,0x65,0x1e]
-
- frintn s1, s2
- frintn d1, d2
-
-; CHECK: frintn s1, s2 ; encoding: [0x41,0x40,0x24,0x1e]
-; CHECK: frintn d1, d2 ; encoding: [0x41,0x40,0x64,0x1e]
-
- frintp s1, s2
- frintp d1, d2
-
-; CHECK: frintp s1, s2 ; encoding: [0x41,0xc0,0x24,0x1e]
-; CHECK: frintp d1, d2 ; encoding: [0x41,0xc0,0x64,0x1e]
-
- frintx s1, s2
- frintx d1, d2
-
-; CHECK: frintx s1, s2 ; encoding: [0x41,0x40,0x27,0x1e]
-; CHECK: frintx d1, d2 ; encoding: [0x41,0x40,0x67,0x1e]
-
- frintz s1, s2
- frintz d1, d2
-
-; CHECK: frintz s1, s2 ; encoding: [0x41,0xc0,0x25,0x1e]
-; CHECK: frintz d1, d2 ; encoding: [0x41,0xc0,0x65,0x1e]
-
- cmhs d0, d0, d0
- cmtst d0, d0, d0
-
-; CHECK: cmhs d0, d0, d0 ; encoding: [0x00,0x3c,0xe0,0x7e]
-; CHECK: cmtst d0, d0, d0 ; encoding: [0x00,0x8c,0xe0,0x5e]
-
-
-
-;-----------------------------------------------------------------------------
-; Floating-point extract and narrow
-;-----------------------------------------------------------------------------
- sqxtn b4, h2
- sqxtn h2, s3
- sqxtn s9, d2
-
-; CHECK: sqxtn b4, h2 ; encoding: [0x44,0x48,0x21,0x5e]
-; CHECK: sqxtn h2, s3 ; encoding: [0x62,0x48,0x61,0x5e]
-; CHECK: sqxtn s9, d2 ; encoding: [0x49,0x48,0xa1,0x5e]
-
- sqxtun b4, h2
- sqxtun h2, s3
- sqxtun s9, d2
-
-; CHECK: sqxtun b4, h2 ; encoding: [0x44,0x28,0x21,0x7e]
-; CHECK: sqxtun h2, s3 ; encoding: [0x62,0x28,0x61,0x7e]
-; CHECK: sqxtun s9, d2 ; encoding: [0x49,0x28,0xa1,0x7e]
-
- uqxtn b4, h2
- uqxtn h2, s3
- uqxtn s9, d2
-
-; CHECK: uqxtn b4, h2 ; encoding: [0x44,0x48,0x21,0x7e]
-; CHECK: uqxtn h2, s3 ; encoding: [0x62,0x48,0x61,0x7e]
-; CHECK: uqxtn s9, d2 ; encoding: [0x49,0x48,0xa1,0x7e]
Removed: llvm/trunk/test/MC/ARM64/large-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/large-relocs.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/large-relocs.s (original)
+++ llvm/trunk/test/MC/ARM64/large-relocs.s (removed)
@@ -1,38 +0,0 @@
-// RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -o - %s | FileCheck %s
-// RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -filetype=obj -o - %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-OBJ %s
-
- movz x2, #:abs_g0:sym
- movk w3, #:abs_g0_nc:sym
-// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_arm64_movw
-// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_arm64_movw
-
-// CHECK-OBJ: 0 R_AARCH64_MOVW_UABS_G0 sym
-// CHECK-OBJ: 4 R_AARCH64_MOVW_UABS_G0_NC sym
-
- movz x4, #:abs_g1:sym
- movk w5, #:abs_g1_nc:sym
-// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_arm64_movw
-// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_arm64_movw
-
-// CHECK-OBJ: 8 R_AARCH64_MOVW_UABS_G1 sym
-// CHECK-OBJ: c R_AARCH64_MOVW_UABS_G1_NC sym
-
- movz x6, #:abs_g2:sym
- movk x7, #:abs_g2_nc:sym
-// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_arm64_movw
-// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_arm64_movw
-
-// CHECK-OBJ: 10 R_AARCH64_MOVW_UABS_G2 sym
-// CHECK-OBJ: 14 R_AARCH64_MOVW_UABS_G2_NC sym
-
- movz x8, #:abs_g3:sym
-// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw
-
-// CHECK-OBJ: 18 R_AARCH64_MOVW_UABS_G3 sym
Removed: llvm/trunk/test/MC/ARM64/leaf-compact-unwind.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/leaf-compact-unwind.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/leaf-compact-unwind.s (original)
+++ llvm/trunk/test/MC/ARM64/leaf-compact-unwind.s (removed)
@@ -1,208 +0,0 @@
-// RUN: llvm-mc -triple=arm64-apple-ios -filetype=obj < %s | \
-// RUN: llvm-readobj -sections -section-relocations -section-data | \
-// RUN: FileCheck %s
-//
-// rdar://13070556
-
-// FIXME: we should add compact unwind support to llvm-objdump -unwind-info
-
-// CHECK: Section {
-// CHECK: Index: 1
-// CHECK-NEXT: Name: __compact_unwind
-// CHECK-NEXT: Segment: __LD
-// CHECK-NEXT: Address:
-// CHECK-NEXT: Size:
-// CHECK-NEXT: Offset:
-// CHECK-NEXT: Alignment:
-// CHECK-NEXT: RelocationOffset:
-// CHECK-NEXT: RelocationCount:
-// CHECK-NEXT: Type:
-// CHECK-NEXT: Attributes [
-// CHECK-NEXT: Debug
-// CHECK-NEXT: ]
-// CHECK-NEXT: Reserved1:
-// CHECK-NEXT: Reserved2:
-// CHECK-NEXT: Relocations [
-// CHECK-NEXT: 0x60 0 3 0 ARM64_RELOC_UNSIGNED 0 -
-// CHECK-NEXT: 0x40 0 3 0 ARM64_RELOC_UNSIGNED 0 -
-// CHECK-NEXT: 0x20 0 3 0 ARM64_RELOC_UNSIGNED 0 -
-// CHECK-NEXT: 0x0 0 3 0 ARM64_RELOC_UNSIGNED 0 -
-// CHECK-NEXT: ]
-// CHECK-NEXT: SectionData (
-// CHECK-NEXT: 0000: 00000000 00000000 08000000 00000002
-// CHECK-NEXT: 0010: 00000000 00000000 00000000 00000000
-// CHECK-NEXT: 0020: 08000000 00000000 40000000 00900002
-// CHECK-NEXT: 0030: 00000000 00000000 00000000 00000000
-// CHECK-NEXT: 0040: 48000000 00000000 D4000000 0F400002
-// CHECK-NEXT: 0050: 00000000 00000000 00000000 00000000
-// CHECK-NEXT: 0060: 1C010000 00000000 54000000 10100202
-// CHECK-NEXT: 0070: 00000000 00000000 00000000 00000000
-// CHECK-NEXT: )
-// CHECK-NEXT: }
-
- .section __TEXT,__text,regular,pure_instructions
- .globl _foo1
- .align 2
-_foo1: ; @foo1
- .cfi_startproc
-; BB#0: ; %entry
- add w0, w0, #42 ; =#42
- ret
- .cfi_endproc
-
- .globl _foo2
- .align 2
-_foo2: ; @foo2
- .cfi_startproc
-; BB#0: ; %entry
- sub sp, sp, #144 ; =#144
-Ltmp2:
- .cfi_def_cfa_offset 144
- mov x9, xzr
- mov x8, sp
-LBB1_1: ; %for.body
- ; =>This Inner Loop Header: Depth=1
- str w9, [x8, x9, lsl #2]
- add x9, x9, #1 ; =#1
- cmp w9, #36 ; =#36
- b.ne LBB1_1
-; BB#2:
- mov x9, xzr
- mov w0, wzr
-LBB1_3: ; %for.body4
- ; =>This Inner Loop Header: Depth=1
- ldr w10, [x8, x9]
- add x9, x9, #4 ; =#4
- cmp w9, #144 ; =#144
- add w0, w10, w0
- b.ne LBB1_3
-; BB#4: ; %for.end9
- add sp, sp, #144 ; =#144
- ret
- .cfi_endproc
-
- .globl _foo3
- .align 2
-_foo3: ; @foo3
- .cfi_startproc
-; BB#0: ; %entry
- stp x26, x25, [sp, #-64]!
- stp x24, x23, [sp, #16]
- stp x22, x21, [sp, #32]
- stp x20, x19, [sp, #48]
-Ltmp3:
- .cfi_def_cfa_offset 64
-Ltmp4:
- .cfi_offset w19, -16
-Ltmp5:
- .cfi_offset w20, -24
-Ltmp6:
- .cfi_offset w21, -32
-Ltmp7:
- .cfi_offset w22, -40
-Ltmp8:
- .cfi_offset w23, -48
-Ltmp9:
- .cfi_offset w24, -56
-Ltmp10:
- .cfi_offset w25, -64
-Ltmp11:
- .cfi_offset w26, -72
-Lloh0:
- adrp x8, _bar at GOTPAGE
-Lloh1:
- ldr x8, [x8, _bar at GOTPAGEOFF]
- ldr w9, [x8]
- ldr w10, [x8]
- ldr w11, [x8]
- ldr w12, [x8]
- ldr w13, [x8]
- ldr w14, [x8]
- ldr w15, [x8]
- ldr w16, [x8]
- ldr w17, [x8]
- ldr w0, [x8]
- ldr w19, [x8]
- ldr w20, [x8]
- ldr w21, [x8]
- ldr w22, [x8]
- ldr w23, [x8]
- ldr w24, [x8]
- ldr w25, [x8]
- ldr w8, [x8]
- add w9, w10, w9
- add w9, w9, w11
- add w9, w9, w12
- add w9, w9, w13
- add w9, w9, w14
- add w9, w9, w15
- add w9, w9, w16
- add w9, w9, w17
- add w9, w9, w0
- add w9, w9, w19
- add w9, w9, w20
- add w9, w9, w21
- add w9, w9, w22
- add w9, w9, w23
- add w9, w9, w24
- add w9, w9, w25
- sub w8, w8, w9
- sub w8, w8, w7, lsl #1
- sub w8, w8, w6, lsl #1
- sub w8, w8, w5, lsl #1
- sub w8, w8, w4, lsl #1
- sub w8, w8, w3, lsl #1
- sub w8, w8, w2, lsl #1
- sub w0, w8, w1, lsl #1
- ldp x20, x19, [sp, #48]
- ldp x22, x21, [sp, #32]
- ldp x24, x23, [sp, #16]
- ldp x26, x25, [sp], #64
- ret
- .loh AdrpLdrGot Lloh0, Lloh1
- .cfi_endproc
-
- .globl _foo4
- .align 2
-_foo4: ; @foo4
- .cfi_startproc
-; BB#0: ; %entry
- stp x28, x27, [sp, #-16]!
- sub sp, sp, #512 ; =#512
-Ltmp12:
- .cfi_def_cfa_offset 528
-Ltmp13:
- .cfi_offset w27, -16
-Ltmp14:
- .cfi_offset w28, -24
- ; kill: W0<def> W0<kill> X0<def>
- mov x9, xzr
- ubfx x10, x0, #0, #32
- mov x8, sp
-LBB3_1: ; %for.body
- ; =>This Inner Loop Header: Depth=1
- add w11, w10, w9
- str w11, [x8, x9, lsl #2]
- add x9, x9, #1 ; =#1
- cmp w9, #128 ; =#128
- b.ne LBB3_1
-; BB#2: ; %for.cond2.preheader
- mov x9, xzr
- mov w0, wzr
- add x8, x8, w5, sxtw #2
-LBB3_3: ; %for.body4
- ; =>This Inner Loop Header: Depth=1
- ldr w10, [x8, x9]
- add x9, x9, #4 ; =#4
- cmp w9, #512 ; =#512
- add w0, w10, w0
- b.ne LBB3_3
-; BB#4: ; %for.end11
- add sp, sp, #512 ; =#512
- ldp x28, x27, [sp], #16
- ret
- .cfi_endproc
-
- .comm _bar,4,2 ; @bar
-
-.subsections_via_symbols
Removed: llvm/trunk/test/MC/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/MC/ARM64/lit.local.cfg (removed)
@@ -1,6 +0,0 @@
-config.suffixes = ['.ll', '.s']
-
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
-
Removed: llvm/trunk/test/MC/ARM64/logical-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/logical-encoding.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/logical-encoding.s (original)
+++ llvm/trunk/test/MC/ARM64/logical-encoding.s (removed)
@@ -1,224 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
-
-foo:
-;==---------------------------------------------------------------------------==
-; 5.4.2 Logical (immediate)
-;==---------------------------------------------------------------------------==
-
- and w0, w0, #1
- and x0, x0, #1
- and w1, w2, #15
- and x1, x2, #15
- and sp, x5, #~15
- ands w0, w0, #1
- ands x0, x0, #1
- ands w1, w2, #15
- ands x1, x2, #15
-
-; CHECK: and w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x12]
-; CHECK: and x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0x92]
-; CHECK: and w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x12]
-; CHECK: and x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0x92]
-; CHECK: and sp, x5, #0xfffffffffffffff0 ; encoding: [0xbf,0xec,0x7c,0x92]
-; CHECK: ands w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x72]
-; CHECK: ands x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0xf2]
-; CHECK: ands w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x72]
-; CHECK: ands x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0xf2]
-
- eor w1, w2, #0x4000
- eor x1, x2, #0x8000
-
-; CHECK: eor w1, w2, #0x4000 ; encoding: [0x41,0x00,0x12,0x52]
-; CHECK: eor x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xd2]
-
- orr w1, w2, #0x4000
- orr x1, x2, #0x8000
-
-; CHECK: orr w1, w2, #0x4000 ; encoding: [0x41,0x00,0x12,0x32]
-; CHECK: orr x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xb2]
-
- orr w8, wzr, #0x1
- orr x8, xzr, #0x1
-
-; CHECK: orr w8, wzr, #0x1 ; encoding: [0xe8,0x03,0x00,0x32]
-; CHECK: orr x8, xzr, #0x1 ; encoding: [0xe8,0x03,0x40,0xb2]
-
-;==---------------------------------------------------------------------------==
-; 5.5.3 Logical (shifted register)
-;==---------------------------------------------------------------------------==
-
- and w1, w2, w3
- and x1, x2, x3
- and w1, w2, w3, lsl #2
- and x1, x2, x3, lsl #2
- and w1, w2, w3, lsr #2
- and x1, x2, x3, lsr #2
- and w1, w2, w3, asr #2
- and x1, x2, x3, asr #2
- and w1, w2, w3, ror #2
- and x1, x2, x3, ror #2
-
-; CHECK: and w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x0a]
-; CHECK: and x1, x2, x3 ; encoding: [0x41,0x00,0x03,0x8a]
-; CHECK: and w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x0a]
-; CHECK: and x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0x8a]
-; CHECK: and w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x0a]
-; CHECK: and x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0x8a]
-; CHECK: and w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x0a]
-; CHECK: and x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0x8a]
-; CHECK: and w1, w2, w3, ror #2 ; encoding: [0x41,0x08,0xc3,0x0a]
-; CHECK: and x1, x2, x3, ror #2 ; encoding: [0x41,0x08,0xc3,0x8a]
-
- ands w1, w2, w3
- ands x1, x2, x3
- ands w1, w2, w3, lsl #2
- ands x1, x2, x3, lsl #2
- ands w1, w2, w3, lsr #2
- ands x1, x2, x3, lsr #2
- ands w1, w2, w3, asr #2
- ands x1, x2, x3, asr #2
- ands w1, w2, w3, ror #2
- ands x1, x2, x3, ror #2
-
-; CHECK: ands w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x6a]
-; CHECK: ands x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xea]
-; CHECK: ands w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x6a]
-; CHECK: ands x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0xea]
-; CHECK: ands w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x6a]
-; CHECK: ands x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0xea]
-; CHECK: ands w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x6a]
-; CHECK: ands x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0xea]
-; CHECK: ands w1, w2, w3, ror #2 ; encoding: [0x41,0x08,0xc3,0x6a]
-; CHECK: ands x1, x2, x3, ror #2 ; encoding: [0x41,0x08,0xc3,0xea]
-
- bic w1, w2, w3
- bic x1, x2, x3
- bic w1, w2, w3, lsl #3
- bic x1, x2, x3, lsl #3
- bic w1, w2, w3, lsr #3
- bic x1, x2, x3, lsr #3
- bic w1, w2, w3, asr #3
- bic x1, x2, x3, asr #3
- bic w1, w2, w3, ror #3
- bic x1, x2, x3, ror #3
-
-; CHECK: bic w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x0a]
-; CHECK: bic x1, x2, x3 ; encoding: [0x41,0x00,0x23,0x8a]
-; CHECK: bic w1, w2, w3, lsl #3 ; encoding: [0x41,0x0c,0x23,0x0a]
-; CHECK: bic x1, x2, x3, lsl #3 ; encoding: [0x41,0x0c,0x23,0x8a]
-; CHECK: bic w1, w2, w3, lsr #3 ; encoding: [0x41,0x0c,0x63,0x0a]
-; CHECK: bic x1, x2, x3, lsr #3 ; encoding: [0x41,0x0c,0x63,0x8a]
-; CHECK: bic w1, w2, w3, asr #3 ; encoding: [0x41,0x0c,0xa3,0x0a]
-; CHECK: bic x1, x2, x3, asr #3 ; encoding: [0x41,0x0c,0xa3,0x8a]
-; CHECK: bic w1, w2, w3, ror #3 ; encoding: [0x41,0x0c,0xe3,0x0a]
-; CHECK: bic x1, x2, x3, ror #3 ; encoding: [0x41,0x0c,0xe3,0x8a]
-
- bics w1, w2, w3
- bics x1, x2, x3
- bics w1, w2, w3, lsl #3
- bics x1, x2, x3, lsl #3
- bics w1, w2, w3, lsr #3
- bics x1, x2, x3, lsr #3
- bics w1, w2, w3, asr #3
- bics x1, x2, x3, asr #3
- bics w1, w2, w3, ror #3
- bics x1, x2, x3, ror #3
-
-; CHECK: bics w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x6a]
-; CHECK: bics x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xea]
-; CHECK: bics w1, w2, w3, lsl #3 ; encoding: [0x41,0x0c,0x23,0x6a]
-; CHECK: bics x1, x2, x3, lsl #3 ; encoding: [0x41,0x0c,0x23,0xea]
-; CHECK: bics w1, w2, w3, lsr #3 ; encoding: [0x41,0x0c,0x63,0x6a]
-; CHECK: bics x1, x2, x3, lsr #3 ; encoding: [0x41,0x0c,0x63,0xea]
-; CHECK: bics w1, w2, w3, asr #3 ; encoding: [0x41,0x0c,0xa3,0x6a]
-; CHECK: bics x1, x2, x3, asr #3 ; encoding: [0x41,0x0c,0xa3,0xea]
-; CHECK: bics w1, w2, w3, ror #3 ; encoding: [0x41,0x0c,0xe3,0x6a]
-; CHECK: bics x1, x2, x3, ror #3 ; encoding: [0x41,0x0c,0xe3,0xea]
-
- eon w1, w2, w3
- eon x1, x2, x3
- eon w1, w2, w3, lsl #4
- eon x1, x2, x3, lsl #4
- eon w1, w2, w3, lsr #4
- eon x1, x2, x3, lsr #4
- eon w1, w2, w3, asr #4
- eon x1, x2, x3, asr #4
- eon w1, w2, w3, ror #4
- eon x1, x2, x3, ror #4
-
-; CHECK: eon w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x4a]
-; CHECK: eon x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xca]
-; CHECK: eon w1, w2, w3, lsl #4 ; encoding: [0x41,0x10,0x23,0x4a]
-; CHECK: eon x1, x2, x3, lsl #4 ; encoding: [0x41,0x10,0x23,0xca]
-; CHECK: eon w1, w2, w3, lsr #4 ; encoding: [0x41,0x10,0x63,0x4a]
-; CHECK: eon x1, x2, x3, lsr #4 ; encoding: [0x41,0x10,0x63,0xca]
-; CHECK: eon w1, w2, w3, asr #4 ; encoding: [0x41,0x10,0xa3,0x4a]
-; CHECK: eon x1, x2, x3, asr #4 ; encoding: [0x41,0x10,0xa3,0xca]
-; CHECK: eon w1, w2, w3, ror #4 ; encoding: [0x41,0x10,0xe3,0x4a]
-; CHECK: eon x1, x2, x3, ror #4 ; encoding: [0x41,0x10,0xe3,0xca]
-
- eor w1, w2, w3
- eor x1, x2, x3
- eor w1, w2, w3, lsl #5
- eor x1, x2, x3, lsl #5
- eor w1, w2, w3, lsr #5
- eor x1, x2, x3, lsr #5
- eor w1, w2, w3, asr #5
- eor x1, x2, x3, asr #5
- eor w1, w2, w3, ror #5
- eor x1, x2, x3, ror #5
-
-; CHECK: eor w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x4a]
-; CHECK: eor x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xca]
-; CHECK: eor w1, w2, w3, lsl #5 ; encoding: [0x41,0x14,0x03,0x4a]
-; CHECK: eor x1, x2, x3, lsl #5 ; encoding: [0x41,0x14,0x03,0xca]
-; CHECK: eor w1, w2, w3, lsr #5 ; encoding: [0x41,0x14,0x43,0x4a]
-; CHECK: eor x1, x2, x3, lsr #5 ; encoding: [0x41,0x14,0x43,0xca]
-; CHECK: eor w1, w2, w3, asr #5 ; encoding: [0x41,0x14,0x83,0x4a]
-; CHECK: eor x1, x2, x3, asr #5 ; encoding: [0x41,0x14,0x83,0xca]
-; CHECK: eor w1, w2, w3, ror #5 ; encoding: [0x41,0x14,0xc3,0x4a]
-; CHECK: eor x1, x2, x3, ror #5 ; encoding: [0x41,0x14,0xc3,0xca]
-
- orr w1, w2, w3
- orr x1, x2, x3
- orr w1, w2, w3, lsl #6
- orr x1, x2, x3, lsl #6
- orr w1, w2, w3, lsr #6
- orr x1, x2, x3, lsr #6
- orr w1, w2, w3, asr #6
- orr x1, x2, x3, asr #6
- orr w1, w2, w3, ror #6
- orr x1, x2, x3, ror #6
-
-; CHECK: orr w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x2a]
-; CHECK: orr x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xaa]
-; CHECK: orr w1, w2, w3, lsl #6 ; encoding: [0x41,0x18,0x03,0x2a]
-; CHECK: orr x1, x2, x3, lsl #6 ; encoding: [0x41,0x18,0x03,0xaa]
-; CHECK: orr w1, w2, w3, lsr #6 ; encoding: [0x41,0x18,0x43,0x2a]
-; CHECK: orr x1, x2, x3, lsr #6 ; encoding: [0x41,0x18,0x43,0xaa]
-; CHECK: orr w1, w2, w3, asr #6 ; encoding: [0x41,0x18,0x83,0x2a]
-; CHECK: orr x1, x2, x3, asr #6 ; encoding: [0x41,0x18,0x83,0xaa]
-; CHECK: orr w1, w2, w3, ror #6 ; encoding: [0x41,0x18,0xc3,0x2a]
-; CHECK: orr x1, x2, x3, ror #6 ; encoding: [0x41,0x18,0xc3,0xaa]
-
- orn w1, w2, w3
- orn x1, x2, x3
- orn w1, w2, w3, lsl #7
- orn x1, x2, x3, lsl #7
- orn w1, w2, w3, lsr #7
- orn x1, x2, x3, lsr #7
- orn w1, w2, w3, asr #7
- orn x1, x2, x3, asr #7
- orn w1, w2, w3, ror #7
- orn x1, x2, x3, ror #7
-
-; CHECK: orn w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x2a]
-; CHECK: orn x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xaa]
-; CHECK: orn w1, w2, w3, lsl #7 ; encoding: [0x41,0x1c,0x23,0x2a]
-; CHECK: orn x1, x2, x3, lsl #7 ; encoding: [0x41,0x1c,0x23,0xaa]
-; CHECK: orn w1, w2, w3, lsr #7 ; encoding: [0x41,0x1c,0x63,0x2a]
-; CHECK: orn x1, x2, x3, lsr #7 ; encoding: [0x41,0x1c,0x63,0xaa]
-; CHECK: orn w1, w2, w3, asr #7 ; encoding: [0x41,0x1c,0xa3,0x2a]
-; CHECK: orn x1, x2, x3, asr #7 ; encoding: [0x41,0x1c,0xa3,0xaa]
-; CHECK: orn w1, w2, w3, ror #7 ; encoding: [0x41,0x1c,0xe3,0x2a]
-; CHECK: orn x1, x2, x3, ror #7 ; encoding: [0x41,0x1c,0xe3,0xaa]
Removed: llvm/trunk/test/MC/ARM64/mapping-across-sections.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/mapping-across-sections.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/mapping-across-sections.s (original)
+++ llvm/trunk/test/MC/ARM64/mapping-across-sections.s (removed)
@@ -1,28 +0,0 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
-
- .text
- add w0, w0, w0
-
-// .wibble should *not* inherit .text's mapping symbol. It's a completely different section.
- .section .wibble
- add w0, w0, w0
-
-// A setion should be able to start with a $d
- .section .starts_data
- .word 42
-
-// Changing back to .text should not emit a redundant $x
- .text
- add w0, w0, w0
-
-// With all those constraints, we want:
-// + .text to have $x at 0 and no others
-// + .wibble to have $x at 0
-// + .starts_data to have $d at 0
-
-
-// CHECK: 00000000 .starts_data 00000000 $d
-// CHECK-NEXT: 00000000 .text 00000000 $x
-// CHECK-NEXT: 00000000 .wibble 00000000 $x
-// CHECK-NOT: ${{[adtx]}}
-
Removed: llvm/trunk/test/MC/ARM64/mapping-within-section.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/mapping-within-section.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/mapping-within-section.s (original)
+++ llvm/trunk/test/MC/ARM64/mapping-within-section.s (removed)
@@ -1,23 +0,0 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
-
- .text
-// $x at 0x0000
- add w0, w0, w0
-// $d at 0x0004
- .ascii "012"
- .byte 1
- .hword 2
- .word 4
- .xword 8
- .single 4.0
- .double 8.0
- .space 10
- .zero 3
- .fill 10, 2, 42
- .org 100, 12
-// $x at 0x0018
- add x0, x0, x0
-
-// CHECK: 00000004 .text 00000000 $d
-// CHECK-NEXT: 00000000 .text 00000000 $x
-// CHECK-NEXT: 00000064 .text 00000000 $x
Removed: llvm/trunk/test/MC/ARM64/memory.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/memory.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/memory.s (original)
+++ llvm/trunk/test/MC/ARM64/memory.s (removed)
@@ -1,634 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
-
-foo:
-;-----------------------------------------------------------------------------
-; Indexed loads
-;-----------------------------------------------------------------------------
-
- ldr w5, [x4, #20]
- ldr x4, [x3]
- ldr x2, [sp, #32]
- ldr b5, [sp, #1]
- ldr h6, [sp, #2]
- ldr s7, [sp, #4]
- ldr d8, [sp, #8]
- ldr q9, [sp, #16]
- ldrb w4, [x3]
- ldrb w5, [x4, #20]
- ldrb w2, [x3, _foo at pageoff]
- ldrb w3, [x2, "+[Test method].var"@PAGEOFF]
- ldrsb w9, [x3]
- ldrsb x2, [sp, #128]
- ldrh w2, [sp, #32]
- ldrsh w3, [sp, #32]
- ldrsh x5, [x9, #24]
- ldrsw x9, [sp, #512]
-
- prfm #5, [sp, #32]
- prfm #31, [sp, #32]
- prfm pldl1keep, [x2]
- prfm pldl1strm, [x2]
- prfm pldl2keep, [x2]
- prfm pldl2strm, [x2]
- prfm pldl3keep, [x2]
- prfm pldl3strm, [x2]
- prfm pstl1keep, [x2]
- prfm pstl1strm, [x2]
- prfm pstl2keep, [x2]
- prfm pstl2strm, [x2]
- prfm pstl3keep, [x2]
- prfm pstl3strm, [x2]
- prfm pstl3strm, [x4, x5, lsl #3]
-
-; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9]
-; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9]
-; CHECK: ldr x2, [sp, #32] ; encoding: [0xe2,0x13,0x40,0xf9]
-; CHECK: ldr b5, [sp, #1] ; encoding: [0xe5,0x07,0x40,0x3d]
-; CHECK: ldr h6, [sp, #2] ; encoding: [0xe6,0x07,0x40,0x7d]
-; CHECK: ldr s7, [sp, #4] ; encoding: [0xe7,0x07,0x40,0xbd]
-; CHECK: ldr d8, [sp, #8] ; encoding: [0xe8,0x07,0x40,0xfd]
-; CHECK: ldr q9, [sp, #16] ; encoding: [0xe9,0x07,0xc0,0x3d]
-; CHECK: ldrb w4, [x3] ; encoding: [0x64,0x00,0x40,0x39]
-; CHECK: ldrb w5, [x4, #20] ; encoding: [0x85,0x50,0x40,0x39]
-; CHECK: ldrb w2, [x3, _foo at PAGEOFF] ; encoding: [0x62,0bAAAAAA00,0b01AAAAAA,0x39]
-; CHECK: ldrb w3, [x2, "+[Test method].var"@PAGEOFF] ; encoding: [0x43,0bAAAAAA00,0b01AAAAAA,0x39]
-; CHECK: ldrsb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x39]
-; CHECK: ldrsb x2, [sp, #128] ; encoding: [0xe2,0x03,0x82,0x39]
-; CHECK: ldrh w2, [sp, #32] ; encoding: [0xe2,0x43,0x40,0x79]
-; CHECK: ldrsh w3, [sp, #32] ; encoding: [0xe3,0x43,0xc0,0x79]
-; CHECK: ldrsh x5, [x9, #24] ; encoding: [0x25,0x31,0x80,0x79]
-; CHECK: ldrsw x9, [sp, #512] ; encoding: [0xe9,0x03,0x82,0xb9]
-; CHECK: prfm pldl3strm, [sp, #32] ; encoding: [0xe5,0x13,0x80,0xf9]
-; CHECK: prfm #31, [sp, #32] ; encoding: [0xff,0x13,0x80,0xf9]
-; CHECK: prfm pldl1keep, [x2] ; encoding: [0x40,0x00,0x80,0xf9]
-; CHECK: prfm pldl1strm, [x2] ; encoding: [0x41,0x00,0x80,0xf9]
-; CHECK: prfm pldl2keep, [x2] ; encoding: [0x42,0x00,0x80,0xf9]
-; CHECK: prfm pldl2strm, [x2] ; encoding: [0x43,0x00,0x80,0xf9]
-; CHECK: prfm pldl3keep, [x2] ; encoding: [0x44,0x00,0x80,0xf9]
-; CHECK: prfm pldl3strm, [x2] ; encoding: [0x45,0x00,0x80,0xf9]
-; CHECK: prfm pstl1keep, [x2] ; encoding: [0x50,0x00,0x80,0xf9]
-; CHECK: prfm pstl1strm, [x2] ; encoding: [0x51,0x00,0x80,0xf9]
-; CHECK: prfm pstl2keep, [x2] ; encoding: [0x52,0x00,0x80,0xf9]
-; CHECK: prfm pstl2strm, [x2] ; encoding: [0x53,0x00,0x80,0xf9]
-; CHECK: prfm pstl3keep, [x2] ; encoding: [0x54,0x00,0x80,0xf9]
-; CHECK: prfm pstl3strm, [x2] ; encoding: [0x55,0x00,0x80,0xf9]
-; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8]
-
-;-----------------------------------------------------------------------------
-; Indexed stores
-;-----------------------------------------------------------------------------
-
- str x4, [x3]
- str x2, [sp, #32]
- str w5, [x4, #20]
- str b5, [sp, #1]
- str h6, [sp, #2]
- str s7, [sp, #4]
- str d8, [sp, #8]
- str q9, [sp, #16]
- strb w4, [x3]
- strb w5, [x4, #20]
- strh w2, [sp, #32]
-
-; CHECK: str x4, [x3] ; encoding: [0x64,0x00,0x00,0xf9]
-; CHECK: str x2, [sp, #32] ; encoding: [0xe2,0x13,0x00,0xf9]
-; CHECK: str w5, [x4, #20] ; encoding: [0x85,0x14,0x00,0xb9]
-; CHECK: str b5, [sp, #1] ; encoding: [0xe5,0x07,0x00,0x3d]
-; CHECK: str h6, [sp, #2] ; encoding: [0xe6,0x07,0x00,0x7d]
-; CHECK: str s7, [sp, #4] ; encoding: [0xe7,0x07,0x00,0xbd]
-; CHECK: str d8, [sp, #8] ; encoding: [0xe8,0x07,0x00,0xfd]
-; CHECK: str q9, [sp, #16] ; encoding: [0xe9,0x07,0x80,0x3d]
-; CHECK: strb w4, [x3] ; encoding: [0x64,0x00,0x00,0x39]
-; CHECK: strb w5, [x4, #20] ; encoding: [0x85,0x50,0x00,0x39]
-; CHECK: strh w2, [sp, #32] ; encoding: [0xe2,0x43,0x00,0x79]
-
-;-----------------------------------------------------------------------------
-; Unscaled immediate loads and stores
-;-----------------------------------------------------------------------------
-
- ldur w2, [x3]
- ldur w2, [sp, #24]
- ldur x2, [x3]
- ldur x2, [sp, #24]
- ldur b5, [sp, #1]
- ldur h6, [sp, #2]
- ldur s7, [sp, #4]
- ldur d8, [sp, #8]
- ldur q9, [sp, #16]
- ldursb w9, [x3]
- ldursb x2, [sp, #128]
- ldursh w3, [sp, #32]
- ldursh x5, [x9, #24]
- ldursw x9, [sp, #-128]
-
-; CHECK: ldur w2, [x3] ; encoding: [0x62,0x00,0x40,0xb8]
-; CHECK: ldur w2, [sp, #24] ; encoding: [0xe2,0x83,0x41,0xb8]
-; CHECK: ldur x2, [x3] ; encoding: [0x62,0x00,0x40,0xf8]
-; CHECK: ldur x2, [sp, #24] ; encoding: [0xe2,0x83,0x41,0xf8]
-; CHECK: ldur b5, [sp, #1] ; encoding: [0xe5,0x13,0x40,0x3c]
-; CHECK: ldur h6, [sp, #2] ; encoding: [0xe6,0x23,0x40,0x7c]
-; CHECK: ldur s7, [sp, #4] ; encoding: [0xe7,0x43,0x40,0xbc]
-; CHECK: ldur d8, [sp, #8] ; encoding: [0xe8,0x83,0x40,0xfc]
-; CHECK: ldur q9, [sp, #16] ; encoding: [0xe9,0x03,0xc1,0x3c]
-; CHECK: ldursb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x38]
-; CHECK: ldursb x2, [sp, #128] ; encoding: [0xe2,0x03,0x88,0x38]
-; CHECK: ldursh w3, [sp, #32] ; encoding: [0xe3,0x03,0xc2,0x78]
-; CHECK: ldursh x5, [x9, #24] ; encoding: [0x25,0x81,0x81,0x78]
-; CHECK: ldursw x9, [sp, #-128] ; encoding: [0xe9,0x03,0x98,0xb8]
-
- stur w4, [x3]
- stur w2, [sp, #32]
- stur x4, [x3]
- stur x2, [sp, #32]
- stur w5, [x4, #20]
- stur b5, [sp, #1]
- stur h6, [sp, #2]
- stur s7, [sp, #4]
- stur d8, [sp, #8]
- stur q9, [sp, #16]
- sturb w4, [x3]
- sturb w5, [x4, #20]
- sturh w2, [sp, #32]
- prfum #5, [sp, #32]
-
-; CHECK: stur w4, [x3] ; encoding: [0x64,0x00,0x00,0xb8]
-; CHECK: stur w2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0xb8]
-; CHECK: stur x4, [x3] ; encoding: [0x64,0x00,0x00,0xf8]
-; CHECK: stur x2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0xf8]
-; CHECK: stur w5, [x4, #20] ; encoding: [0x85,0x40,0x01,0xb8]
-; CHECK: stur b5, [sp, #1] ; encoding: [0xe5,0x13,0x00,0x3c]
-; CHECK: stur h6, [sp, #2] ; encoding: [0xe6,0x23,0x00,0x7c]
-; CHECK: stur s7, [sp, #4] ; encoding: [0xe7,0x43,0x00,0xbc]
-; CHECK: stur d8, [sp, #8] ; encoding: [0xe8,0x83,0x00,0xfc]
-; CHECK: stur q9, [sp, #16] ; encoding: [0xe9,0x03,0x81,0x3c]
-; CHECK: sturb w4, [x3] ; encoding: [0x64,0x00,0x00,0x38]
-; CHECK: sturb w5, [x4, #20] ; encoding: [0x85,0x40,0x01,0x38]
-; CHECK: sturh w2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0x78]
-; CHECK: prfum pldl3strm, [sp, #32] ; encoding: [0xe5,0x03,0x82,0xf8]
-
-;-----------------------------------------------------------------------------
-; Unprivileged loads and stores
-;-----------------------------------------------------------------------------
-
- ldtr w3, [x4, #16]
- ldtr x3, [x4, #16]
- ldtrb w3, [x4, #16]
- ldtrsb w9, [x3]
- ldtrsb x2, [sp, #128]
- ldtrh w3, [x4, #16]
- ldtrsh w3, [sp, #32]
- ldtrsh x5, [x9, #24]
- ldtrsw x9, [sp, #-128]
-
-; CHECK: ldtr w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0xb8]
-; CHECK: ldtr x3, [x4, #16] ; encoding: [0x83,0x08,0x41,0xf8]
-; CHECK: ldtrb w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0x38]
-; CHECK: ldtrsb w9, [x3] ; encoding: [0x69,0x08,0xc0,0x38]
-; CHECK: ldtrsb x2, [sp, #128] ; encoding: [0xe2,0x0b,0x88,0x38]
-; CHECK: ldtrh w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0x78]
-; CHECK: ldtrsh w3, [sp, #32] ; encoding: [0xe3,0x0b,0xc2,0x78]
-; CHECK: ldtrsh x5, [x9, #24] ; encoding: [0x25,0x89,0x81,0x78]
-; CHECK: ldtrsw x9, [sp, #-128] ; encoding: [0xe9,0x0b,0x98,0xb8]
-
- sttr w5, [x4, #20]
- sttr x4, [x3]
- sttr x2, [sp, #32]
- sttrb w4, [x3]
- sttrb w5, [x4, #20]
- sttrh w2, [sp, #32]
-
-; CHECK: sttr w5, [x4, #20] ; encoding: [0x85,0x48,0x01,0xb8]
-; CHECK: sttr x4, [x3] ; encoding: [0x64,0x08,0x00,0xf8]
-; CHECK: sttr x2, [sp, #32] ; encoding: [0xe2,0x0b,0x02,0xf8]
-; CHECK: sttrb w4, [x3] ; encoding: [0x64,0x08,0x00,0x38]
-; CHECK: sttrb w5, [x4, #20] ; encoding: [0x85,0x48,0x01,0x38]
-; CHECK: sttrh w2, [sp, #32] ; encoding: [0xe2,0x0b,0x02,0x78]
-
-;-----------------------------------------------------------------------------
-; Pre-indexed loads and stores
-;-----------------------------------------------------------------------------
-
- ldr x29, [x7, #8]!
- ldr x30, [x7, #8]!
- ldr b5, [x0, #1]!
- ldr h6, [x0, #2]!
- ldr s7, [x0, #4]!
- ldr d8, [x0, #8]!
- ldr q9, [x0, #16]!
-
- str x30, [x7, #-8]!
- str x29, [x7, #-8]!
- str b5, [x0, #-1]!
- str h6, [x0, #-2]!
- str s7, [x0, #-4]!
- str d8, [x0, #-8]!
- str q9, [x0, #-16]!
-
-; CHECK: ldr x29, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
-; CHECK: ldr x30, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8]
-; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c]
-; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c]
-; CHECK: ldr s7, [x0, #4]! ; encoding: [0x07,0x4c,0x40,0xbc]
-; CHECK: ldr d8, [x0, #8]! ; encoding: [0x08,0x8c,0x40,0xfc]
-; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c]
-
-; CHECK: str x30, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8]
-; CHECK: str x29, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
-; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c]
-; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c]
-; CHECK: str s7, [x0, #-4]! ; encoding: [0x07,0xcc,0x1f,0xbc]
-; CHECK: str d8, [x0, #-8]! ; encoding: [0x08,0x8c,0x1f,0xfc]
-; CHECK: str q9, [x0, #-16]! ; encoding: [0x09,0x0c,0x9f,0x3c]
-
-;-----------------------------------------------------------------------------
-; post-indexed loads and stores
-;-----------------------------------------------------------------------------
- str x30, [x7], #-8
- str x29, [x7], #-8
- str b5, [x0], #-1
- str h6, [x0], #-2
- str s7, [x0], #-4
- str d8, [x0], #-8
- str q9, [x0], #-16
-
- ldr x29, [x7], #8
- ldr x30, [x7], #8
- ldr b5, [x0], #1
- ldr h6, [x0], #2
- ldr s7, [x0], #4
- ldr d8, [x0], #8
- ldr q9, [x0], #16
-
-; CHECK: str x30, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8]
-; CHECK: str x29, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
-; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c]
-; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c]
-; CHECK: str s7, [x0], #-4 ; encoding: [0x07,0xc4,0x1f,0xbc]
-; CHECK: str d8, [x0], #-8 ; encoding: [0x08,0x84,0x1f,0xfc]
-; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c]
-
-; CHECK: ldr x29, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
-; CHECK: ldr x30, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8]
-; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c]
-; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c]
-; CHECK: ldr s7, [x0], #4 ; encoding: [0x07,0x44,0x40,0xbc]
-; CHECK: ldr d8, [x0], #8 ; encoding: [0x08,0x84,0x40,0xfc]
-; CHECK: ldr q9, [x0], #16 ; encoding: [0x09,0x04,0xc1,0x3c]
-
-;-----------------------------------------------------------------------------
-; Load/Store pair (indexed, offset)
-;-----------------------------------------------------------------------------
-
- ldp w3, w2, [x15, #16]
- ldp x4, x9, [sp, #-16]
- ldpsw x2, x3, [x14, #16]
- ldpsw x2, x3, [sp, #-16]
- ldp s10, s1, [x2, #64]
- ldp d10, d1, [x2]
- ldp q2, q3, [x0, #32]
-
-; CHECK: ldp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x29]
-; CHECK: ldp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x7f,0xa9]
-; CHECK: ldpsw x2, x3, [x14, #16] ; encoding: [0xc2,0x0d,0x42,0x69]
-; CHECK: ldpsw x2, x3, [sp, #-16] ; encoding: [0xe2,0x0f,0x7e,0x69]
-; CHECK: ldp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x48,0x2d]
-; CHECK: ldp d10, d1, [x2] ; encoding: [0x4a,0x04,0x40,0x6d]
-; CHECK: ldp q2, q3, [x0, #32] ; encoding: [0x02,0x0c,0x41,0xad]
-
- stp w3, w2, [x15, #16]
- stp x4, x9, [sp, #-16]
- stp s10, s1, [x2, #64]
- stp d10, d1, [x2]
- stp q2, q3, [x0, #32]
-
-; CHECK: stp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x02,0x29]
-; CHECK: stp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x3f,0xa9]
-; CHECK: stp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x08,0x2d]
-; CHECK: stp d10, d1, [x2] ; encoding: [0x4a,0x04,0x00,0x6d]
-; CHECK: stp q2, q3, [x0, #32] ; encoding: [0x02,0x0c,0x01,0xad]
-
-;-----------------------------------------------------------------------------
-; Load/Store pair (pre-indexed)
-;-----------------------------------------------------------------------------
-
- ldp w3, w2, [x15, #16]!
- ldp x4, x9, [sp, #-16]!
- ldpsw x2, x3, [x14, #16]!
- ldpsw x2, x3, [sp, #-16]!
- ldp s10, s1, [x2, #64]!
- ldp d10, d1, [x2, #16]!
-
-; CHECK: ldp w3, w2, [x15, #16]! ; encoding: [0xe3,0x09,0xc2,0x29]
-; CHECK: ldp x4, x9, [sp, #-16]! ; encoding: [0xe4,0x27,0xff,0xa9]
-; CHECK: ldpsw x2, x3, [x14, #16]! ; encoding: [0xc2,0x0d,0xc2,0x69]
-; CHECK: ldpsw x2, x3, [sp, #-16]! ; encoding: [0xe2,0x0f,0xfe,0x69]
-; CHECK: ldp s10, s1, [x2, #64]! ; encoding: [0x4a,0x04,0xc8,0x2d]
-; CHECK: ldp d10, d1, [x2, #16]! ; encoding: [0x4a,0x04,0xc1,0x6d]
-
- stp w3, w2, [x15, #16]!
- stp x4, x9, [sp, #-16]!
- stp s10, s1, [x2, #64]!
- stp d10, d1, [x2, #16]!
-
-; CHECK: stp w3, w2, [x15, #16]! ; encoding: [0xe3,0x09,0x82,0x29]
-; CHECK: stp x4, x9, [sp, #-16]! ; encoding: [0xe4,0x27,0xbf,0xa9]
-; CHECK: stp s10, s1, [x2, #64]! ; encoding: [0x4a,0x04,0x88,0x2d]
-; CHECK: stp d10, d1, [x2, #16]! ; encoding: [0x4a,0x04,0x81,0x6d]
-
-;-----------------------------------------------------------------------------
-; Load/Store pair (post-indexed)
-;-----------------------------------------------------------------------------
-
- ldp w3, w2, [x15], #16
- ldp x4, x9, [sp], #-16
- ldpsw x2, x3, [x14], #16
- ldpsw x2, x3, [sp], #-16
- ldp s10, s1, [x2], #64
- ldp d10, d1, [x2], #16
-
-; CHECK: ldp w3, w2, [x15], #16 ; encoding: [0xe3,0x09,0xc2,0x28]
-; CHECK: ldp x4, x9, [sp], #-16 ; encoding: [0xe4,0x27,0xff,0xa8]
-; CHECK: ldpsw x2, x3, [x14], #16 ; encoding: [0xc2,0x0d,0xc2,0x68]
-; CHECK: ldpsw x2, x3, [sp], #-16 ; encoding: [0xe2,0x0f,0xfe,0x68]
-; CHECK: ldp s10, s1, [x2], #64 ; encoding: [0x4a,0x04,0xc8,0x2c]
-; CHECK: ldp d10, d1, [x2], #16 ; encoding: [0x4a,0x04,0xc1,0x6c]
-
- stp w3, w2, [x15], #16
- stp x4, x9, [sp], #-16
- stp s10, s1, [x2], #64
- stp d10, d1, [x2], #16
-
-; CHECK: stp w3, w2, [x15], #16 ; encoding: [0xe3,0x09,0x82,0x28]
-; CHECK: stp x4, x9, [sp], #-16 ; encoding: [0xe4,0x27,0xbf,0xa8]
-; CHECK: stp s10, s1, [x2], #64 ; encoding: [0x4a,0x04,0x88,0x2c]
-; CHECK: stp d10, d1, [x2], #16 ; encoding: [0x4a,0x04,0x81,0x6c]
-
-;-----------------------------------------------------------------------------
-; Load/Store pair (no-allocate)
-;-----------------------------------------------------------------------------
-
- ldnp w3, w2, [x15, #16]
- ldnp x4, x9, [sp, #-16]
- ldnp s10, s1, [x2, #64]
- ldnp d10, d1, [x2]
-
-; CHECK: ldnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x28]
-; CHECK: ldnp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x7f,0xa8]
-; CHECK: ldnp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x48,0x2c]
-; CHECK: ldnp d10, d1, [x2] ; encoding: [0x4a,0x04,0x40,0x6c]
-
- stnp w3, w2, [x15, #16]
- stnp x4, x9, [sp, #-16]
- stnp s10, s1, [x2, #64]
- stnp d10, d1, [x2]
-
-; CHECK: stnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x02,0x28]
-; CHECK: stnp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x3f,0xa8]
-; CHECK: stnp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x08,0x2c]
-; CHECK: stnp d10, d1, [x2] ; encoding: [0x4a,0x04,0x00,0x6c]
-
-;-----------------------------------------------------------------------------
-; Load/Store register offset
-;-----------------------------------------------------------------------------
-
- ldr w0, [x0, x0]
- ldr w0, [x0, x0, lsl #2]
- ldr x0, [x0, x0]
- ldr x0, [x0, x0, lsl #3]
- ldr x0, [x0, x0, sxtx]
-
-; CHECK: ldr w0, [x0, x0] ; encoding: [0x00,0x68,0x60,0xb8]
-; CHECK: ldr w0, [x0, x0, lsl #2] ; encoding: [0x00,0x78,0x60,0xb8]
-; CHECK: ldr x0, [x0, x0] ; encoding: [0x00,0x68,0x60,0xf8]
-; CHECK: ldr x0, [x0, x0, lsl #3] ; encoding: [0x00,0x78,0x60,0xf8]
-; CHECK: ldr x0, [x0, x0, sxtx] ; encoding: [0x00,0xe8,0x60,0xf8]
-
- ldr b1, [x1, x2]
- ldr b1, [x1, x2, lsl #0]
- ldr h1, [x1, x2]
- ldr h1, [x1, x2, lsl #1]
- ldr s1, [x1, x2]
- ldr s1, [x1, x2, lsl #2]
- ldr d1, [x1, x2]
- ldr d1, [x1, x2, lsl #3]
- ldr q1, [x1, x2]
- ldr q1, [x1, x2, lsl #4]
-
-; CHECK: ldr b1, [x1, x2] ; encoding: [0x21,0x68,0x62,0x3c]
-; CHECK: ldr b1, [x1, x2, lsl #0] ; encoding: [0x21,0x78,0x62,0x3c]
-; CHECK: ldr h1, [x1, x2] ; encoding: [0x21,0x68,0x62,0x7c]
-; CHECK: ldr h1, [x1, x2, lsl #1] ; encoding: [0x21,0x78,0x62,0x7c]
-; CHECK: ldr s1, [x1, x2] ; encoding: [0x21,0x68,0x62,0xbc]
-; CHECK: ldr s1, [x1, x2, lsl #2] ; encoding: [0x21,0x78,0x62,0xbc]
-; CHECK: ldr d1, [x1, x2] ; encoding: [0x21,0x68,0x62,0xfc]
-; CHECK: ldr d1, [x1, x2, lsl #3] ; encoding: [0x21,0x78,0x62,0xfc]
-; CHECK: ldr q1, [x1, x2] ; encoding: [0x21,0x68,0xe2,0x3c]
-; CHECK: ldr q1, [x1, x2, lsl #4] ; encoding: [0x21,0x78,0xe2,0x3c]
-
- str d1, [sp, x3]
- str d1, [sp, w3, uxtw #3]
- str q1, [sp, x3]
- str q1, [sp, w3, uxtw #4]
-
-; CHECK: str d1, [sp, x3] ; encoding: [0xe1,0x6b,0x23,0xfc]
-; CHECK: str d1, [sp, w3, uxtw #3] ; encoding: [0xe1,0x5b,0x23,0xfc]
-; CHECK: str q1, [sp, x3] ; encoding: [0xe1,0x6b,0xa3,0x3c]
-; CHECK: str q1, [sp, w3, uxtw #4] ; encoding: [0xe1,0x5b,0xa3,0x3c]
-
-;-----------------------------------------------------------------------------
-; Load literal
-;-----------------------------------------------------------------------------
-
- ldr w5, foo
- ldr x4, foo
- ldrsw x9, foo
- prfm #5, foo
-
-; CHECK: ldr w5, foo ; encoding: [0bAAA00101,A,A,0x18]
-; CHECK: ldr x4, foo ; encoding: [0bAAA00100,A,A,0x58]
-; CHECK: ldrsw x9, foo ; encoding: [0bAAA01001,A,A,0x98]
-; CHECK: prfm pldl3strm, foo ; encoding: [0bAAA00101,A,A,0xd8]
-
-;-----------------------------------------------------------------------------
-; Load/Store exclusive
-;-----------------------------------------------------------------------------
-
- ldxr w6, [x1]
- ldxr x6, [x1]
- ldxrb w6, [x1]
- ldxrh w6, [x1]
- ldxp w7, w3, [x9]
- ldxp x7, x3, [x9]
-
-; CHECK: ldxrb w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x08]
-; CHECK: ldxrh w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x48]
-; CHECK: ldxp w7, w3, [x9] ; encoding: [0x27,0x0d,0x7f,0x88]
-; CHECK: ldxp x7, x3, [x9] ; encoding: [0x27,0x0d,0x7f,0xc8]
-
- stxr w1, x4, [x3]
- stxr w1, w4, [x3]
- stxrb w1, w4, [x3]
- stxrh w1, w4, [x3]
- stxp w1, x2, x6, [x1]
- stxp w1, w2, w6, [x1]
-
-; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8]
-; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
-; CHECK: stxrb w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x08]
-; CHECK: stxrh w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x48]
-; CHECK: stxp w1, x2, x6, [x1] ; encoding: [0x22,0x18,0x21,0xc8]
-; CHECK: stxp w1, w2, w6, [x1] ; encoding: [0x22,0x18,0x21,0x88]
-
-;-----------------------------------------------------------------------------
-; Load-acquire/Store-release non-exclusive
-;-----------------------------------------------------------------------------
-
- ldar w4, [sp]
- ldar x4, [sp, #0]
- ldarb w4, [sp]
- ldarh w4, [sp]
-
-; CHECK: ldar w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x88]
-; CHECK: ldar x4, [sp] ; encoding: [0xe4,0xff,0xdf,0xc8]
-; CHECK: ldarb w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x08]
-; CHECK: ldarh w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x48]
-
- stlr w3, [x6]
- stlr x3, [x6]
- stlrb w3, [x6]
- stlrh w3, [x6]
-
-; CHECK: stlr w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x88]
-; CHECK: stlr x3, [x6] ; encoding: [0xc3,0xfc,0x9f,0xc8]
-; CHECK: stlrb w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x08]
-; CHECK: stlrh w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x48]
-
-;-----------------------------------------------------------------------------
-; Load-acquire/Store-release exclusive
-;-----------------------------------------------------------------------------
-
- ldaxr w2, [x4]
- ldaxr x2, [x4]
- ldaxrb w2, [x4, #0]
- ldaxrh w2, [x4]
- ldaxp w2, w6, [x1]
- ldaxp x2, x6, [x1]
-
-; CHECK: ldaxr w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x88]
-; CHECK: ldaxr x2, [x4] ; encoding: [0x82,0xfc,0x5f,0xc8]
-; CHECK: ldaxrb w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x08]
-; CHECK: ldaxrh w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x48]
-; CHECK: ldaxp w2, w6, [x1] ; encoding: [0x22,0x98,0x7f,0x88]
-; CHECK: ldaxp x2, x6, [x1] ; encoding: [0x22,0x98,0x7f,0xc8]
-
- stlxr w8, x7, [x1]
- stlxr w8, w7, [x1]
- stlxrb w8, w7, [x1]
- stlxrh w8, w7, [x1]
- stlxp w1, x2, x6, [x1]
- stlxp w1, w2, w6, [x1]
-
-; CHECK: stlxr w8, x7, [x1] ; encoding: [0x27,0xfc,0x08,0xc8]
-; CHECK: stlxr w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x88]
-; CHECK: stlxrb w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x08]
-; CHECK: stlxrh w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x48]
-; CHECK: stlxp w1, x2, x6, [x1] ; encoding: [0x22,0x98,0x21,0xc8]
-; CHECK: stlxp w1, w2, w6, [x1] ; encoding: [0x22,0x98,0x21,0x88]
-
-
-;-----------------------------------------------------------------------------
-; LDUR/STUR aliases for negative and unaligned LDR/STR instructions.
-;
-; According to the ARM ISA documentation:
-; "A programmer-friendly assembler should also generate these instructions
-; in response to the standard LDR/STR mnemonics when the immediate offset is
-; unambiguous, i.e. negative or unaligned."
-;-----------------------------------------------------------------------------
-
- ldr x11, [x29, #-8]
- ldr x11, [x29, #7]
- ldr w0, [x0, #2]
- ldr w0, [x0, #-256]
- ldr b2, [x1, #-2]
- ldr h3, [x2, #3]
- ldr h3, [x3, #-4]
- ldr s3, [x4, #3]
- ldr s3, [x5, #-4]
- ldr d4, [x6, #4]
- ldr d4, [x7, #-8]
- ldr q5, [x8, #8]
- ldr q5, [x9, #-16]
-
-; CHECK: ldur x11, [x29, #-8] ; encoding: [0xab,0x83,0x5f,0xf8]
-; CHECK: ldur x11, [x29, #7] ; encoding: [0xab,0x73,0x40,0xf8]
-; CHECK: ldur w0, [x0, #2] ; encoding: [0x00,0x20,0x40,0xb8]
-; CHECK: ldur w0, [x0, #-256] ; encoding: [0x00,0x00,0x50,0xb8]
-; CHECK: ldur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x5f,0x3c]
-; CHECK: ldur h3, [x2, #3] ; encoding: [0x43,0x30,0x40,0x7c]
-; CHECK: ldur h3, [x3, #-4] ; encoding: [0x63,0xc0,0x5f,0x7c]
-; CHECK: ldur s3, [x4, #3] ; encoding: [0x83,0x30,0x40,0xbc]
-; CHECK: ldur s3, [x5, #-4] ; encoding: [0xa3,0xc0,0x5f,0xbc]
-; CHECK: ldur d4, [x6, #4] ; encoding: [0xc4,0x40,0x40,0xfc]
-; CHECK: ldur d4, [x7, #-8] ; encoding: [0xe4,0x80,0x5f,0xfc]
-; CHECK: ldur q5, [x8, #8] ; encoding: [0x05,0x81,0xc0,0x3c]
-; CHECK: ldur q5, [x9, #-16] ; encoding: [0x25,0x01,0xdf,0x3c]
-
- str x11, [x29, #-8]
- str x11, [x29, #7]
- str w0, [x0, #2]
- str w0, [x0, #-256]
- str b2, [x1, #-2]
- str h3, [x2, #3]
- str h3, [x3, #-4]
- str s3, [x4, #3]
- str s3, [x5, #-4]
- str d4, [x6, #4]
- str d4, [x7, #-8]
- str q5, [x8, #8]
- str q5, [x9, #-16]
-
-; CHECK: stur x11, [x29, #-8] ; encoding: [0xab,0x83,0x1f,0xf8]
-; CHECK: stur x11, [x29, #7] ; encoding: [0xab,0x73,0x00,0xf8]
-; CHECK: stur w0, [x0, #2] ; encoding: [0x00,0x20,0x00,0xb8]
-; CHECK: stur w0, [x0, #-256] ; encoding: [0x00,0x00,0x10,0xb8]
-; CHECK: stur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x1f,0x3c]
-; CHECK: stur h3, [x2, #3] ; encoding: [0x43,0x30,0x00,0x7c]
-; CHECK: stur h3, [x3, #-4] ; encoding: [0x63,0xc0,0x1f,0x7c]
-; CHECK: stur s3, [x4, #3] ; encoding: [0x83,0x30,0x00,0xbc]
-; CHECK: stur s3, [x5, #-4] ; encoding: [0xa3,0xc0,0x1f,0xbc]
-; CHECK: stur d4, [x6, #4] ; encoding: [0xc4,0x40,0x00,0xfc]
-; CHECK: stur d4, [x7, #-8] ; encoding: [0xe4,0x80,0x1f,0xfc]
-; CHECK: stur q5, [x8, #8] ; encoding: [0x05,0x81,0x80,0x3c]
-; CHECK: stur q5, [x9, #-16] ; encoding: [0x25,0x01,0x9f,0x3c]
-
- ldrb w3, [x1, #-1]
- ldrh w4, [x2, #1]
- ldrh w5, [x3, #-1]
- ldrsb w6, [x4, #-1]
- ldrsb x7, [x5, #-1]
- ldrsh w8, [x6, #1]
- ldrsh w9, [x7, #-1]
- ldrsh x1, [x8, #1]
- ldrsh x2, [x9, #-1]
- ldrsw x3, [x10, #10]
- ldrsw x4, [x11, #-1]
-
-; CHECK: ldurb w3, [x1, #-1] ; encoding: [0x23,0xf0,0x5f,0x38]
-; CHECK: ldurh w4, [x2, #1] ; encoding: [0x44,0x10,0x40,0x78]
-; CHECK: ldurh w5, [x3, #-1] ; encoding: [0x65,0xf0,0x5f,0x78]
-; CHECK: ldursb w6, [x4, #-1] ; encoding: [0x86,0xf0,0xdf,0x38]
-; CHECK: ldursb x7, [x5, #-1] ; encoding: [0xa7,0xf0,0x9f,0x38]
-; CHECK: ldursh w8, [x6, #1] ; encoding: [0xc8,0x10,0xc0,0x78]
-; CHECK: ldursh w9, [x7, #-1] ; encoding: [0xe9,0xf0,0xdf,0x78]
-; CHECK: ldursh x1, [x8, #1] ; encoding: [0x01,0x11,0x80,0x78]
-; CHECK: ldursh x2, [x9, #-1] ; encoding: [0x22,0xf1,0x9f,0x78]
-; CHECK: ldursw x3, [x10, #10] ; encoding: [0x43,0xa1,0x80,0xb8]
-; CHECK: ldursw x4, [x11, #-1] ; encoding: [0x64,0xf1,0x9f,0xb8]
-
- strb w3, [x1, #-1]
- strh w4, [x2, #1]
- strh w5, [x3, #-1]
-
-; CHECK: sturb w3, [x1, #-1] ; encoding: [0x23,0xf0,0x1f,0x38]
-; CHECK: sturh w4, [x2, #1] ; encoding: [0x44,0x10,0x00,0x78]
-; CHECK: sturh w5, [x3, #-1] ; encoding: [0x65,0xf0,0x1f,0x78]
Removed: llvm/trunk/test/MC/ARM64/nv-cond.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/nv-cond.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/nv-cond.s (original)
+++ llvm/trunk/test/MC/ARM64/nv-cond.s (removed)
@@ -1,11 +0,0 @@
-// RUN: llvm-mc < %s -triple arm64 -mattr=neon -show-encoding | FileCheck %s
-
-fcsel d28,d31,d31,nv
-csel x0,x0,x0,nv
-ccmp x0,x0,#0,nv
-b.nv #0
-
-// CHECK: fcsel d28, d31, d31, nv // encoding: [0xfc,0xff,0x7f,0x1e]
-// CHECK: csel x0, x0, x0, nv // encoding: [0x00,0xf0,0x80,0x9a]
-// CHECK: ccmp x0, x0, #0, nv // encoding: [0x00,0xf0,0x40,0xfa]
-// CHECK: b.nv #0 // encoding: [0x0f,0x00,0x00,0x54]
Removed: llvm/trunk/test/MC/ARM64/optional-hash.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/optional-hash.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/optional-hash.s (original)
+++ llvm/trunk/test/MC/ARM64/optional-hash.s (removed)
@@ -1,31 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
-.text
-; parseOperand check
-; CHECK: add sp, sp, #32 ; encoding: [0xff,0x83,0x00,0x91]
- add sp, sp, 32
-
-; Optional shift
-; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1]
-adds x3, x4, 1024, lsl 12
-
-; Optional extend
-; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b]
-add sp, x2, x3, uxtx 0
-
-; FP immediates
-; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e]
-fmov s1, 0.125
-
-; Barrier operand
-; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5]
-dmb 3
-
-; Prefetch and memory
-
-; Single register inside []
-; CHECK: ldnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x28]
-ldnp w3, w2, [x15, 16]
-
-; Memory, two registers inside []
-; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8]
-prfm pstl3strm, [x4, x5, lsl 3]
Removed: llvm/trunk/test/MC/ARM64/separator.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/separator.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/separator.s (original)
+++ llvm/trunk/test/MC/ARM64/separator.s (removed)
@@ -1,20 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
-
-; ARM64 uses a multi-character statement separator, "%%". Check that we lex
-; it properly and recognize the multiple assembly statements on the line.
-
-; To make sure the output assembly correctly handled the instructions,
-; tell it to show encodings. That will result in the two 'mov' instructions
-; being on separate lines in the output. We look for the "; encoding" string
-; to verify that. For this test, we don't care what the encoding is, just that
-; there is one for each 'mov' instruction.
-
-
-_foo:
-; CHECK: foo
-; CHECK: mov x0, x1 ; encoding
-; CHECK: mov x1, x0 ; encoding
- mov x0, x1 %% mov x1, x0
- ret lr
-
-
More information about the llvm-commits
mailing list