[llvm] r209577 - AArch64/ARM64: move ARM64 into AArch64's place
Tim Northover
tnorthover at apple.com
Sat May 24 05:50:31 PDT 2014
Removed: llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp (removed)
@@ -1,4030 +0,0 @@
-//===-- ARM64AsmParser.cpp - Parse ARM64 assembly to MCInst instructions --===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCTargetDesc/ARM64AddressingModes.h"
-#include "MCTargetDesc/ARM64MCExpr.h"
-#include "Utils/ARM64BaseInfo.h"
-#include "llvm/MC/MCParser/MCAsmLexer.h"
-#include "llvm/MC/MCParser/MCAsmParser.h"
-#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/MCTargetAsmParser.h"
-#include "llvm/Support/SourceMgr.h"
-#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/ADT/SmallString.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/StringSwitch.h"
-#include "llvm/ADT/Twine.h"
-#include <cstdio>
-using namespace llvm;
-
-namespace {
-
-class ARM64Operand;
-
-class ARM64AsmParser : public MCTargetAsmParser {
-public:
- typedef SmallVectorImpl<MCParsedAsmOperand *> OperandVector;
-
-private:
- StringRef Mnemonic; ///< Instruction mnemonic.
- MCSubtargetInfo &STI;
- MCAsmParser &Parser;
-
- MCAsmParser &getParser() const { return Parser; }
- MCAsmLexer &getLexer() const { return Parser.getLexer(); }
-
- SMLoc getLoc() const { return Parser.getTok().getLoc(); }
-
- bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
- ARM64CC::CondCode parseCondCodeString(StringRef Cond);
- bool parseCondCode(OperandVector &Operands, bool invertCondCode);
- int tryParseRegister();
- int tryMatchVectorRegister(StringRef &Kind, bool expected);
- bool parseRegister(OperandVector &Operands);
- bool parseSymbolicImmVal(const MCExpr *&ImmVal);
- bool parseVectorList(OperandVector &Operands);
- bool parseOperand(OperandVector &Operands, bool isCondCode,
- bool invertCondCode);
-
- void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
- bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
- bool showMatchError(SMLoc Loc, unsigned ErrCode);
-
- bool parseDirectiveWord(unsigned Size, SMLoc L);
- bool parseDirectiveTLSDescCall(SMLoc L);
-
- bool parseDirectiveLOH(StringRef LOH, SMLoc L);
-
- bool validateInstruction(MCInst &Inst, SmallVectorImpl<SMLoc> &Loc);
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
- OperandVector &Operands, MCStreamer &Out,
- unsigned &ErrorInfo,
- bool MatchingInlineAsm) override;
-/// @name Auto-generated Match Functions
-/// {
-
-#define GET_ASSEMBLER_HEADER
-#include "ARM64GenAsmMatcher.inc"
-
- /// }
-
- OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
- OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
- OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
- OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
- OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
- OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);
- OperandMatchResultTy tryParseAdrpLabel(OperandVector &Operands);
- OperandMatchResultTy tryParseAdrLabel(OperandVector &Operands);
- OperandMatchResultTy tryParseFPImm(OperandVector &Operands);
- OperandMatchResultTy tryParseAddSubImm(OperandVector &Operands);
- OperandMatchResultTy tryParseGPR64sp0Operand(OperandVector &Operands);
- bool tryParseVectorRegister(OperandVector &Operands);
-
-public:
- enum ARM64MatchResultTy {
- Match_InvalidSuffix = FIRST_TARGET_MATCH_RESULT_TY,
-#define GET_OPERAND_DIAGNOSTIC_TYPES
-#include "ARM64GenAsmMatcher.inc"
- };
- ARM64AsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
- const MCInstrInfo &MII,
- const MCTargetOptions &Options)
- : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
- MCAsmParserExtension::Initialize(_Parser);
-
- // Initialize the set of available features.
- setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
- }
-
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
- SMLoc NameLoc, OperandVector &Operands) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- bool ParseDirective(AsmToken DirectiveID) override;
- unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
- unsigned Kind) override;
-
- static bool classifySymbolRef(const MCExpr *Expr,
- ARM64MCExpr::VariantKind &ELFRefKind,
- MCSymbolRefExpr::VariantKind &DarwinRefKind,
- int64_t &Addend);
-};
-} // end anonymous namespace
-
-namespace {
-
-/// ARM64Operand - Instances of this class represent a parsed ARM64 machine
-/// instruction.
-class ARM64Operand : public MCParsedAsmOperand {
-private:
- enum KindTy {
- k_Immediate,
- k_ShiftedImm,
- k_CondCode,
- k_Register,
- k_VectorList,
- k_VectorIndex,
- k_Token,
- k_SysReg,
- k_SysCR,
- k_Prefetch,
- k_ShiftExtend,
- k_FPImm,
- k_Barrier
- } Kind;
-
- SMLoc StartLoc, EndLoc;
-
- struct TokOp {
- const char *Data;
- unsigned Length;
- bool IsSuffix; // Is the operand actually a suffix on the mnemonic.
- };
-
- struct RegOp {
- unsigned RegNum;
- bool isVector;
- };
-
- struct VectorListOp {
- unsigned RegNum;
- unsigned Count;
- unsigned NumElements;
- unsigned ElementKind;
- };
-
- struct VectorIndexOp {
- unsigned Val;
- };
-
- struct ImmOp {
- const MCExpr *Val;
- };
-
- struct ShiftedImmOp {
- const MCExpr *Val;
- unsigned ShiftAmount;
- };
-
- struct CondCodeOp {
- ARM64CC::CondCode Code;
- };
-
- struct FPImmOp {
- unsigned Val; // Encoded 8-bit representation.
- };
-
- struct BarrierOp {
- unsigned Val; // Not the enum since not all values have names.
- };
-
- struct SysRegOp {
- const char *Data;
- unsigned Length;
- uint64_t FeatureBits; // We need to pass through information about which
- // core we are compiling for so that the SysReg
- // Mappers can appropriately conditionalize.
- };
-
- struct SysCRImmOp {
- unsigned Val;
- };
-
- struct PrefetchOp {
- unsigned Val;
- };
-
- struct ShiftExtendOp {
- ARM64_AM::ShiftExtendType Type;
- unsigned Amount;
- bool HasExplicitAmount;
- };
-
- struct ExtendOp {
- unsigned Val;
- };
-
- union {
- struct TokOp Tok;
- struct RegOp Reg;
- struct VectorListOp VectorList;
- struct VectorIndexOp VectorIndex;
- struct ImmOp Imm;
- struct ShiftedImmOp ShiftedImm;
- struct CondCodeOp CondCode;
- struct FPImmOp FPImm;
- struct BarrierOp Barrier;
- struct SysRegOp SysReg;
- struct SysCRImmOp SysCRImm;
- struct PrefetchOp Prefetch;
- struct ShiftExtendOp ShiftExtend;
- };
-
- // Keep the MCContext around as the MCExprs may need manipulated during
- // the add<>Operands() calls.
- MCContext &Ctx;
-
- ARM64Operand(KindTy K, MCContext &_Ctx)
- : MCParsedAsmOperand(), Kind(K), Ctx(_Ctx) {}
-
-public:
- ARM64Operand(const ARM64Operand &o) : MCParsedAsmOperand(), Ctx(o.Ctx) {
- Kind = o.Kind;
- StartLoc = o.StartLoc;
- EndLoc = o.EndLoc;
- switch (Kind) {
- case k_Token:
- Tok = o.Tok;
- break;
- case k_Immediate:
- Imm = o.Imm;
- break;
- case k_ShiftedImm:
- ShiftedImm = o.ShiftedImm;
- break;
- case k_CondCode:
- CondCode = o.CondCode;
- break;
- case k_FPImm:
- FPImm = o.FPImm;
- break;
- case k_Barrier:
- Barrier = o.Barrier;
- break;
- case k_Register:
- Reg = o.Reg;
- break;
- case k_VectorList:
- VectorList = o.VectorList;
- break;
- case k_VectorIndex:
- VectorIndex = o.VectorIndex;
- break;
- case k_SysReg:
- SysReg = o.SysReg;
- break;
- case k_SysCR:
- SysCRImm = o.SysCRImm;
- break;
- case k_Prefetch:
- Prefetch = o.Prefetch;
- break;
- case k_ShiftExtend:
- ShiftExtend = o.ShiftExtend;
- break;
- }
- }
-
- /// getStartLoc - Get the location of the first token of this operand.
- SMLoc getStartLoc() const override { return StartLoc; }
- /// getEndLoc - Get the location of the last token of this operand.
- SMLoc getEndLoc() const override { return EndLoc; }
-
- StringRef getToken() const {
- assert(Kind == k_Token && "Invalid access!");
- return StringRef(Tok.Data, Tok.Length);
- }
-
- bool isTokenSuffix() const {
- assert(Kind == k_Token && "Invalid access!");
- return Tok.IsSuffix;
- }
-
- const MCExpr *getImm() const {
- assert(Kind == k_Immediate && "Invalid access!");
- return Imm.Val;
- }
-
- const MCExpr *getShiftedImmVal() const {
- assert(Kind == k_ShiftedImm && "Invalid access!");
- return ShiftedImm.Val;
- }
-
- unsigned getShiftedImmShift() const {
- assert(Kind == k_ShiftedImm && "Invalid access!");
- return ShiftedImm.ShiftAmount;
- }
-
- ARM64CC::CondCode getCondCode() const {
- assert(Kind == k_CondCode && "Invalid access!");
- return CondCode.Code;
- }
-
- unsigned getFPImm() const {
- assert(Kind == k_FPImm && "Invalid access!");
- return FPImm.Val;
- }
-
- unsigned getBarrier() const {
- assert(Kind == k_Barrier && "Invalid access!");
- return Barrier.Val;
- }
-
- unsigned getReg() const override {
- assert(Kind == k_Register && "Invalid access!");
- return Reg.RegNum;
- }
-
- unsigned getVectorListStart() const {
- assert(Kind == k_VectorList && "Invalid access!");
- return VectorList.RegNum;
- }
-
- unsigned getVectorListCount() const {
- assert(Kind == k_VectorList && "Invalid access!");
- return VectorList.Count;
- }
-
- unsigned getVectorIndex() const {
- assert(Kind == k_VectorIndex && "Invalid access!");
- return VectorIndex.Val;
- }
-
- StringRef getSysReg() const {
- assert(Kind == k_SysReg && "Invalid access!");
- return StringRef(SysReg.Data, SysReg.Length);
- }
-
- uint64_t getSysRegFeatureBits() const {
- assert(Kind == k_SysReg && "Invalid access!");
- return SysReg.FeatureBits;
- }
-
- unsigned getSysCR() const {
- assert(Kind == k_SysCR && "Invalid access!");
- return SysCRImm.Val;
- }
-
- unsigned getPrefetch() const {
- assert(Kind == k_Prefetch && "Invalid access!");
- return Prefetch.Val;
- }
-
- ARM64_AM::ShiftExtendType getShiftExtendType() const {
- assert(Kind == k_ShiftExtend && "Invalid access!");
- return ShiftExtend.Type;
- }
-
- unsigned getShiftExtendAmount() const {
- assert(Kind == k_ShiftExtend && "Invalid access!");
- return ShiftExtend.Amount;
- }
-
- bool hasShiftExtendAmount() const {
- assert(Kind == k_ShiftExtend && "Invalid access!");
- return ShiftExtend.HasExplicitAmount;
- }
-
- bool isImm() const override { return Kind == k_Immediate; }
- bool isMem() const override { return false; }
- bool isSImm9() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= -256 && Val < 256);
- }
- bool isSImm7s4() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= -256 && Val <= 252 && (Val & 3) == 0);
- }
- bool isSImm7s8() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= -512 && Val <= 504 && (Val & 7) == 0);
- }
- bool isSImm7s16() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= -1024 && Val <= 1008 && (Val & 15) == 0);
- }
-
- bool isSymbolicUImm12Offset(const MCExpr *Expr, unsigned Scale) const {
- ARM64MCExpr::VariantKind ELFRefKind;
- MCSymbolRefExpr::VariantKind DarwinRefKind;
- int64_t Addend;
- if (!ARM64AsmParser::classifySymbolRef(Expr, ELFRefKind, DarwinRefKind,
- Addend)) {
- // If we don't understand the expression, assume the best and
- // let the fixup and relocation code deal with it.
- return true;
- }
-
- if (DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF ||
- ELFRefKind == ARM64MCExpr::VK_LO12 ||
- ELFRefKind == ARM64MCExpr::VK_GOT_LO12 ||
- ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12 ||
- ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12_NC ||
- ELFRefKind == ARM64MCExpr::VK_TPREL_LO12 ||
- ELFRefKind == ARM64MCExpr::VK_TPREL_LO12_NC ||
- ELFRefKind == ARM64MCExpr::VK_GOTTPREL_LO12_NC ||
- ELFRefKind == ARM64MCExpr::VK_TLSDESC_LO12) {
- // Note that we don't range-check the addend. It's adjusted modulo page
- // size when converted, so there is no "out of range" condition when using
- // @pageoff.
- return Addend >= 0 && (Addend % Scale) == 0;
- } else if (DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGEOFF ||
- DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF) {
- // @gotpageoff/@tlvppageoff can only be used directly, not with an addend.
- return Addend == 0;
- }
-
- return false;
- }
-
- template <int Scale> bool isUImm12Offset() const {
- if (!isImm())
- return false;
-
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return isSymbolicUImm12Offset(getImm(), Scale);
-
- int64_t Val = MCE->getValue();
- return (Val % Scale) == 0 && Val >= 0 && (Val / Scale) < 0x1000;
- }
-
- bool isImm0_7() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 0 && Val < 8);
- }
- bool isImm1_8() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val > 0 && Val < 9);
- }
- bool isImm0_15() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 0 && Val < 16);
- }
- bool isImm1_16() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val > 0 && Val < 17);
- }
- bool isImm0_31() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 0 && Val < 32);
- }
- bool isImm1_31() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 1 && Val < 32);
- }
- bool isImm1_32() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 1 && Val < 33);
- }
- bool isImm0_63() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 0 && Val < 64);
- }
- bool isImm1_63() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 1 && Val < 64);
- }
- bool isImm1_64() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 1 && Val < 65);
- }
- bool isImm0_127() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 0 && Val < 128);
- }
- bool isImm0_255() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 0 && Val < 256);
- }
- bool isImm0_65535() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 0 && Val < 65536);
- }
- bool isImm32_63() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- int64_t Val = MCE->getValue();
- return (Val >= 32 && Val < 64);
- }
- bool isLogicalImm32() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- return ARM64_AM::isLogicalImmediate(MCE->getValue(), 32);
- }
- bool isLogicalImm64() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- return ARM64_AM::isLogicalImmediate(MCE->getValue(), 64);
- }
- bool isShiftedImm() const { return Kind == k_ShiftedImm; }
- bool isAddSubImm() const {
- if (!isShiftedImm() && !isImm())
- return false;
-
- const MCExpr *Expr;
-
- // An ADD/SUB shifter is either 'lsl #0' or 'lsl #12'.
- if (isShiftedImm()) {
- unsigned Shift = ShiftedImm.ShiftAmount;
- Expr = ShiftedImm.Val;
- if (Shift != 0 && Shift != 12)
- return false;
- } else {
- Expr = getImm();
- }
-
- ARM64MCExpr::VariantKind ELFRefKind;
- MCSymbolRefExpr::VariantKind DarwinRefKind;
- int64_t Addend;
- if (ARM64AsmParser::classifySymbolRef(Expr, ELFRefKind,
- DarwinRefKind, Addend)) {
- return DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF
- || DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF
- || (DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGEOFF && Addend == 0)
- || ELFRefKind == ARM64MCExpr::VK_LO12
- || ELFRefKind == ARM64MCExpr::VK_DTPREL_HI12
- || ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12
- || ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12_NC
- || ELFRefKind == ARM64MCExpr::VK_TPREL_HI12
- || ELFRefKind == ARM64MCExpr::VK_TPREL_LO12
- || ELFRefKind == ARM64MCExpr::VK_TPREL_LO12_NC
- || ELFRefKind == ARM64MCExpr::VK_TLSDESC_LO12;
- }
-
- // Otherwise it should be a real immediate in range:
- const MCConstantExpr *CE = cast<MCConstantExpr>(Expr);
- return CE->getValue() >= 0 && CE->getValue() <= 0xfff;
- }
- bool isCondCode() const { return Kind == k_CondCode; }
- bool isSIMDImmType10() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return false;
- return ARM64_AM::isAdvSIMDModImmType10(MCE->getValue());
- }
- bool isBranchTarget26() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return true;
- int64_t Val = MCE->getValue();
- if (Val & 0x3)
- return false;
- return (Val >= -(0x2000000 << 2) && Val <= (0x1ffffff << 2));
- }
- bool isPCRelLabel19() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return true;
- int64_t Val = MCE->getValue();
- if (Val & 0x3)
- return false;
- return (Val >= -(0x40000 << 2) && Val <= (0x3ffff << 2));
- }
- bool isBranchTarget14() const {
- if (!isImm())
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- return true;
- int64_t Val = MCE->getValue();
- if (Val & 0x3)
- return false;
- return (Val >= -(0x2000 << 2) && Val <= (0x1fff << 2));
- }
-
- bool isMovWSymbol(ArrayRef<ARM64MCExpr::VariantKind> AllowedModifiers) const {
- if (!isImm())
- return false;
-
- ARM64MCExpr::VariantKind ELFRefKind;
- MCSymbolRefExpr::VariantKind DarwinRefKind;
- int64_t Addend;
- if (!ARM64AsmParser::classifySymbolRef(getImm(), ELFRefKind, DarwinRefKind,
- Addend)) {
- return false;
- }
- if (DarwinRefKind != MCSymbolRefExpr::VK_None)
- return false;
-
- for (unsigned i = 0; i != AllowedModifiers.size(); ++i) {
- if (ELFRefKind == AllowedModifiers[i])
- return Addend == 0;
- }
-
- return false;
- }
-
- bool isMovZSymbolG3() const {
- static ARM64MCExpr::VariantKind Variants[] = { ARM64MCExpr::VK_ABS_G3 };
- return isMovWSymbol(Variants);
- }
-
- bool isMovZSymbolG2() const {
- static ARM64MCExpr::VariantKind Variants[] = { ARM64MCExpr::VK_ABS_G2,
- ARM64MCExpr::VK_ABS_G2_S,
- ARM64MCExpr::VK_TPREL_G2,
- ARM64MCExpr::VK_DTPREL_G2 };
- return isMovWSymbol(Variants);
- }
-
- bool isMovZSymbolG1() const {
- static ARM64MCExpr::VariantKind Variants[] = { ARM64MCExpr::VK_ABS_G1,
- ARM64MCExpr::VK_ABS_G1_S,
- ARM64MCExpr::VK_GOTTPREL_G1,
- ARM64MCExpr::VK_TPREL_G1,
- ARM64MCExpr::VK_DTPREL_G1, };
- return isMovWSymbol(Variants);
- }
-
- bool isMovZSymbolG0() const {
- static ARM64MCExpr::VariantKind Variants[] = { ARM64MCExpr::VK_ABS_G0,
- ARM64MCExpr::VK_ABS_G0_S,
- ARM64MCExpr::VK_TPREL_G0,
- ARM64MCExpr::VK_DTPREL_G0 };
- return isMovWSymbol(Variants);
- }
-
- bool isMovKSymbolG3() const {
- static ARM64MCExpr::VariantKind Variants[] = { ARM64MCExpr::VK_ABS_G3 };
- return isMovWSymbol(Variants);
- }
-
- bool isMovKSymbolG2() const {
- static ARM64MCExpr::VariantKind Variants[] = { ARM64MCExpr::VK_ABS_G2_NC };
- return isMovWSymbol(Variants);
- }
-
- bool isMovKSymbolG1() const {
- static ARM64MCExpr::VariantKind Variants[] = {
- ARM64MCExpr::VK_ABS_G1_NC, ARM64MCExpr::VK_TPREL_G1_NC,
- ARM64MCExpr::VK_DTPREL_G1_NC
- };
- return isMovWSymbol(Variants);
- }
-
- bool isMovKSymbolG0() const {
- static ARM64MCExpr::VariantKind Variants[] = {
- ARM64MCExpr::VK_ABS_G0_NC, ARM64MCExpr::VK_GOTTPREL_G0_NC,
- ARM64MCExpr::VK_TPREL_G0_NC, ARM64MCExpr::VK_DTPREL_G0_NC
- };
- return isMovWSymbol(Variants);
- }
-
- template<int RegWidth, int Shift>
- bool isMOVZMovAlias() const {
- if (!isImm()) return false;
-
- const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- if (!CE) return false;
- uint64_t Value = CE->getValue();
-
- if (RegWidth == 32)
- Value &= 0xffffffffULL;
-
- // "lsl #0" takes precedence: in practice this only affects "#0, lsl #0".
- if (Value == 0 && Shift != 0)
- return false;
-
- return (Value & ~(0xffffULL << Shift)) == 0;
- }
-
- template<int RegWidth, int Shift>
- bool isMOVNMovAlias() const {
- if (!isImm()) return false;
-
- const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- if (!CE) return false;
- uint64_t Value = CE->getValue();
-
- // MOVZ takes precedence over MOVN.
- for (int MOVZShift = 0; MOVZShift <= 48; MOVZShift += 16)
- if ((Value & ~(0xffffULL << MOVZShift)) == 0)
- return false;
-
- Value = ~Value;
- if (RegWidth == 32)
- Value &= 0xffffffffULL;
-
- return (Value & ~(0xffffULL << Shift)) == 0;
- }
-
- bool isFPImm() const { return Kind == k_FPImm; }
- bool isBarrier() const { return Kind == k_Barrier; }
- bool isSysReg() const { return Kind == k_SysReg; }
- bool isMRSSystemRegister() const {
- if (!isSysReg()) return false;
-
- bool IsKnownRegister;
- auto Mapper = ARM64SysReg::MRSMapper(getSysRegFeatureBits());
- Mapper.fromString(getSysReg(), IsKnownRegister);
-
- return IsKnownRegister;
- }
- bool isMSRSystemRegister() const {
- if (!isSysReg()) return false;
-
- bool IsKnownRegister;
- auto Mapper = ARM64SysReg::MSRMapper(getSysRegFeatureBits());
- Mapper.fromString(getSysReg(), IsKnownRegister);
-
- return IsKnownRegister;
- }
- bool isSystemPStateField() const {
- if (!isSysReg()) return false;
-
- bool IsKnownRegister;
- ARM64PState::PStateMapper().fromString(getSysReg(), IsKnownRegister);
-
- return IsKnownRegister;
- }
- bool isReg() const override { return Kind == k_Register && !Reg.isVector; }
- bool isVectorReg() const { return Kind == k_Register && Reg.isVector; }
- bool isVectorRegLo() const {
- return Kind == k_Register && Reg.isVector &&
- ARM64MCRegisterClasses[ARM64::FPR128_loRegClassID].contains(Reg.RegNum);
- }
- bool isGPR32as64() const {
- return Kind == k_Register && !Reg.isVector &&
- ARM64MCRegisterClasses[ARM64::GPR64RegClassID].contains(Reg.RegNum);
- }
-
- bool isGPR64sp0() const {
- return Kind == k_Register && !Reg.isVector &&
- ARM64MCRegisterClasses[ARM64::GPR64spRegClassID].contains(Reg.RegNum);
- }
-
- /// Is this a vector list with the type implicit (presumably attached to the
- /// instruction itself)?
- template <unsigned NumRegs> bool isImplicitlyTypedVectorList() const {
- return Kind == k_VectorList && VectorList.Count == NumRegs &&
- !VectorList.ElementKind;
- }
-
- template <unsigned NumRegs, unsigned NumElements, char ElementKind>
- bool isTypedVectorList() const {
- if (Kind != k_VectorList)
- return false;
- if (VectorList.Count != NumRegs)
- return false;
- if (VectorList.ElementKind != ElementKind)
- return false;
- return VectorList.NumElements == NumElements;
- }
-
- bool isVectorIndex1() const {
- return Kind == k_VectorIndex && VectorIndex.Val == 1;
- }
- bool isVectorIndexB() const {
- return Kind == k_VectorIndex && VectorIndex.Val < 16;
- }
- bool isVectorIndexH() const {
- return Kind == k_VectorIndex && VectorIndex.Val < 8;
- }
- bool isVectorIndexS() const {
- return Kind == k_VectorIndex && VectorIndex.Val < 4;
- }
- bool isVectorIndexD() const {
- return Kind == k_VectorIndex && VectorIndex.Val < 2;
- }
- bool isToken() const override { return Kind == k_Token; }
- bool isTokenEqual(StringRef Str) const {
- return Kind == k_Token && getToken() == Str;
- }
- bool isSysCR() const { return Kind == k_SysCR; }
- bool isPrefetch() const { return Kind == k_Prefetch; }
- bool isShiftExtend() const { return Kind == k_ShiftExtend; }
- bool isShifter() const {
- if (!isShiftExtend())
- return false;
-
- ARM64_AM::ShiftExtendType ST = getShiftExtendType();
- return (ST == ARM64_AM::LSL || ST == ARM64_AM::LSR || ST == ARM64_AM::ASR ||
- ST == ARM64_AM::ROR || ST == ARM64_AM::MSL);
- }
- bool isExtend() const {
- if (!isShiftExtend())
- return false;
-
- ARM64_AM::ShiftExtendType ET = getShiftExtendType();
- return (ET == ARM64_AM::UXTB || ET == ARM64_AM::SXTB ||
- ET == ARM64_AM::UXTH || ET == ARM64_AM::SXTH ||
- ET == ARM64_AM::UXTW || ET == ARM64_AM::SXTW ||
- ET == ARM64_AM::UXTX || ET == ARM64_AM::SXTX ||
- ET == ARM64_AM::LSL) &&
- getShiftExtendAmount() <= 4;
- }
-
- bool isExtend64() const {
- if (!isExtend())
- return false;
- // UXTX and SXTX require a 64-bit source register (the ExtendLSL64 class).
- ARM64_AM::ShiftExtendType ET = getShiftExtendType();
- return ET != ARM64_AM::UXTX && ET != ARM64_AM::SXTX;
- }
- bool isExtendLSL64() const {
- if (!isExtend())
- return false;
- ARM64_AM::ShiftExtendType ET = getShiftExtendType();
- return (ET == ARM64_AM::UXTX || ET == ARM64_AM::SXTX || ET == ARM64_AM::LSL) &&
- getShiftExtendAmount() <= 4;
- }
-
- template<int Width> bool isMemXExtend() const {
- if (!isExtend())
- return false;
- ARM64_AM::ShiftExtendType ET = getShiftExtendType();
- return (ET == ARM64_AM::LSL || ET == ARM64_AM::SXTX) &&
- (getShiftExtendAmount() == Log2_32(Width / 8) ||
- getShiftExtendAmount() == 0);
- }
-
- template<int Width> bool isMemWExtend() const {
- if (!isExtend())
- return false;
- ARM64_AM::ShiftExtendType ET = getShiftExtendType();
- return (ET == ARM64_AM::UXTW || ET == ARM64_AM::SXTW) &&
- (getShiftExtendAmount() == Log2_32(Width / 8) ||
- getShiftExtendAmount() == 0);
- }
-
- template <unsigned width>
- bool isArithmeticShifter() const {
- if (!isShifter())
- return false;
-
- // An arithmetic shifter is LSL, LSR, or ASR.
- ARM64_AM::ShiftExtendType ST = getShiftExtendType();
- return (ST == ARM64_AM::LSL || ST == ARM64_AM::LSR ||
- ST == ARM64_AM::ASR) && getShiftExtendAmount() < width;
- }
-
- template <unsigned width>
- bool isLogicalShifter() const {
- if (!isShifter())
- return false;
-
- // A logical shifter is LSL, LSR, ASR or ROR.
- ARM64_AM::ShiftExtendType ST = getShiftExtendType();
- return (ST == ARM64_AM::LSL || ST == ARM64_AM::LSR || ST == ARM64_AM::ASR ||
- ST == ARM64_AM::ROR) &&
- getShiftExtendAmount() < width;
- }
-
- bool isMovImm32Shifter() const {
- if (!isShifter())
- return false;
-
- // A MOVi shifter is LSL of 0, 16, 32, or 48.
- ARM64_AM::ShiftExtendType ST = getShiftExtendType();
- if (ST != ARM64_AM::LSL)
- return false;
- uint64_t Val = getShiftExtendAmount();
- return (Val == 0 || Val == 16);
- }
-
- bool isMovImm64Shifter() const {
- if (!isShifter())
- return false;
-
- // A MOVi shifter is LSL of 0 or 16.
- ARM64_AM::ShiftExtendType ST = getShiftExtendType();
- if (ST != ARM64_AM::LSL)
- return false;
- uint64_t Val = getShiftExtendAmount();
- return (Val == 0 || Val == 16 || Val == 32 || Val == 48);
- }
-
- bool isLogicalVecShifter() const {
- if (!isShifter())
- return false;
-
- // A logical vector shifter is a left shift by 0, 8, 16, or 24.
- unsigned Shift = getShiftExtendAmount();
- return getShiftExtendType() == ARM64_AM::LSL &&
- (Shift == 0 || Shift == 8 || Shift == 16 || Shift == 24);
- }
-
- bool isLogicalVecHalfWordShifter() const {
- if (!isLogicalVecShifter())
- return false;
-
- // A logical vector shifter is a left shift by 0 or 8.
- unsigned Shift = getShiftExtendAmount();
- return getShiftExtendType() == ARM64_AM::LSL && (Shift == 0 || Shift == 8);
- }
-
- bool isMoveVecShifter() const {
- if (!isShiftExtend())
- return false;
-
- // A logical vector shifter is a left shift by 8 or 16.
- unsigned Shift = getShiftExtendAmount();
- return getShiftExtendType() == ARM64_AM::MSL && (Shift == 8 || Shift == 16);
- }
-
- // Fallback unscaled operands are for aliases of LDR/STR that fall back
- // to LDUR/STUR when the offset is not legal for the former but is for
- // the latter. As such, in addition to checking for being a legal unscaled
- // address, also check that it is not a legal scaled address. This avoids
- // ambiguity in the matcher.
- template<int Width>
- bool isSImm9OffsetFB() const {
- return isSImm9() && !isUImm12Offset<Width / 8>();
- }
-
- bool isAdrpLabel() const {
- // Validation was handled during parsing, so we just sanity check that
- // something didn't go haywire.
- if (!isImm())
- return false;
-
- if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
- int64_t Val = CE->getValue();
- int64_t Min = - (4096 * (1LL << (21 - 1)));
- int64_t Max = 4096 * ((1LL << (21 - 1)) - 1);
- return (Val % 4096) == 0 && Val >= Min && Val <= Max;
- }
-
- return true;
- }
-
- bool isAdrLabel() const {
- // Validation was handled during parsing, so we just sanity check that
- // something didn't go haywire.
- if (!isImm())
- return false;
-
- if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
- int64_t Val = CE->getValue();
- int64_t Min = - (1LL << (21 - 1));
- int64_t Max = ((1LL << (21 - 1)) - 1);
- return Val >= Min && Val <= Max;
- }
-
- return true;
- }
-
- void addExpr(MCInst &Inst, const MCExpr *Expr) const {
- // Add as immediates when possible. Null MCExpr = 0.
- if (!Expr)
- Inst.addOperand(MCOperand::CreateImm(0));
- else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
- else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
- }
-
- void addRegOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
- }
-
- void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- assert(ARM64MCRegisterClasses[ARM64::GPR64RegClassID].contains(getReg()));
-
- const MCRegisterInfo *RI = Ctx.getRegisterInfo();
- uint32_t Reg = RI->getRegClass(ARM64::GPR32RegClassID).getRegister(
- RI->getEncodingValue(getReg()));
-
- Inst.addOperand(MCOperand::CreateReg(Reg));
- }
-
- void addVectorReg64Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- assert(ARM64MCRegisterClasses[ARM64::FPR128RegClassID].contains(getReg()));
- Inst.addOperand(MCOperand::CreateReg(ARM64::D0 + getReg() - ARM64::Q0));
- }
-
- void addVectorReg128Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- assert(ARM64MCRegisterClasses[ARM64::FPR128RegClassID].contains(getReg()));
- Inst.addOperand(MCOperand::CreateReg(getReg()));
- }
-
- void addVectorRegLoOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
- }
-
- template <unsigned NumRegs>
- void addVectorList64Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- static unsigned FirstRegs[] = { ARM64::D0, ARM64::D0_D1,
- ARM64::D0_D1_D2, ARM64::D0_D1_D2_D3 };
- unsigned FirstReg = FirstRegs[NumRegs - 1];
-
- Inst.addOperand(
- MCOperand::CreateReg(FirstReg + getVectorListStart() - ARM64::Q0));
- }
-
- template <unsigned NumRegs>
- void addVectorList128Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- static unsigned FirstRegs[] = { ARM64::Q0, ARM64::Q0_Q1,
- ARM64::Q0_Q1_Q2, ARM64::Q0_Q1_Q2_Q3 };
- unsigned FirstReg = FirstRegs[NumRegs - 1];
-
- Inst.addOperand(
- MCOperand::CreateReg(FirstReg + getVectorListStart() - ARM64::Q0));
- }
-
- void addVectorIndex1Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
- }
-
- void addVectorIndexBOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
- }
-
- void addVectorIndexHOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
- }
-
- void addVectorIndexSOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
- }
-
- void addVectorIndexDOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
- }
-
- void addImmOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- // If this is a pageoff symrefexpr with an addend, adjust the addend
- // to be only the page-offset portion. Otherwise, just add the expr
- // as-is.
- addExpr(Inst, getImm());
- }
-
- void addAddSubImmOperands(MCInst &Inst, unsigned N) const {
- assert(N == 2 && "Invalid number of operands!");
- if (isShiftedImm()) {
- addExpr(Inst, getShiftedImmVal());
- Inst.addOperand(MCOperand::CreateImm(getShiftedImmShift()));
- } else {
- addExpr(Inst, getImm());
- Inst.addOperand(MCOperand::CreateImm(0));
- }
- }
-
- void addCondCodeOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getCondCode()));
- }
-
- void addAdrpLabelOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE)
- addExpr(Inst, getImm());
- else
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 12));
- }
-
- void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
- addImmOperands(Inst, N);
- }
-
- template<int Scale>
- void addUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
-
- if (!MCE) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
- return;
- }
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / Scale));
- }
-
- void addSImm9Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addSImm7s4Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / 4));
- }
-
- void addSImm7s8Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / 8));
- }
-
- void addSImm7s16Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / 16));
- }
-
- void addImm0_7Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm1_8Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm0_15Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm1_16Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm0_31Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm1_31Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm1_32Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm0_63Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm1_63Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm1_64Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm0_127Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm0_255Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addImm32_63Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
- }
-
- void addLogicalImm32Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid logical immediate operand!");
- uint64_t encoding = ARM64_AM::encodeLogicalImmediate(MCE->getValue(), 32);
- Inst.addOperand(MCOperand::CreateImm(encoding));
- }
-
- void addLogicalImm64Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid logical immediate operand!");
- uint64_t encoding = ARM64_AM::encodeLogicalImmediate(MCE->getValue(), 64);
- Inst.addOperand(MCOperand::CreateImm(encoding));
- }
-
- void addSIMDImmType10Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- assert(MCE && "Invalid immediate operand!");
- uint64_t encoding = ARM64_AM::encodeAdvSIMDModImmType10(MCE->getValue());
- Inst.addOperand(MCOperand::CreateImm(encoding));
- }
-
- void addBranchTarget26Operands(MCInst &Inst, unsigned N) const {
- // Branch operands don't encode the low bits, so shift them off
- // here. If it's a label, however, just put it on directly as there's
- // not enough information now to do anything.
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE) {
- addExpr(Inst, getImm());
- return;
- }
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 2));
- }
-
- void addPCRelLabel19Operands(MCInst &Inst, unsigned N) const {
- // Branch operands don't encode the low bits, so shift them off
- // here. If it's a label, however, just put it on directly as there's
- // not enough information now to do anything.
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE) {
- addExpr(Inst, getImm());
- return;
- }
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 2));
- }
-
- void addBranchTarget14Operands(MCInst &Inst, unsigned N) const {
- // Branch operands don't encode the low bits, so shift them off
- // here. If it's a label, however, just put it on directly as there's
- // not enough information now to do anything.
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
- if (!MCE) {
- addExpr(Inst, getImm());
- return;
- }
- assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 2));
- }
-
- void addFPImmOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getFPImm()));
- }
-
- void addBarrierOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getBarrier()));
- }
-
- void addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
-
- bool Valid;
- auto Mapper = ARM64SysReg::MRSMapper(getSysRegFeatureBits());
- uint32_t Bits = Mapper.fromString(getSysReg(), Valid);
-
- Inst.addOperand(MCOperand::CreateImm(Bits));
- }
-
- void addMSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
-
- bool Valid;
- auto Mapper = ARM64SysReg::MSRMapper(getSysRegFeatureBits());
- uint32_t Bits = Mapper.fromString(getSysReg(), Valid);
-
- Inst.addOperand(MCOperand::CreateImm(Bits));
- }
-
- void addSystemPStateFieldOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
-
- bool Valid;
- uint32_t Bits = ARM64PState::PStateMapper().fromString(getSysReg(), Valid);
-
- Inst.addOperand(MCOperand::CreateImm(Bits));
- }
-
- void addSysCROperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getSysCR()));
- }
-
- void addPrefetchOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getPrefetch()));
- }
-
- void addShifterOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- unsigned Imm =
- ARM64_AM::getShifterImm(getShiftExtendType(), getShiftExtendAmount());
- Inst.addOperand(MCOperand::CreateImm(Imm));
- }
-
- void addExtendOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- ARM64_AM::ShiftExtendType ET = getShiftExtendType();
- if (ET == ARM64_AM::LSL) ET = ARM64_AM::UXTW;
- unsigned Imm = ARM64_AM::getArithExtendImm(ET, getShiftExtendAmount());
- Inst.addOperand(MCOperand::CreateImm(Imm));
- }
-
- void addExtend64Operands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- ARM64_AM::ShiftExtendType ET = getShiftExtendType();
- if (ET == ARM64_AM::LSL) ET = ARM64_AM::UXTX;
- unsigned Imm = ARM64_AM::getArithExtendImm(ET, getShiftExtendAmount());
- Inst.addOperand(MCOperand::CreateImm(Imm));
- }
-
- void addMemExtendOperands(MCInst &Inst, unsigned N) const {
- assert(N == 2 && "Invalid number of operands!");
- ARM64_AM::ShiftExtendType ET = getShiftExtendType();
- bool IsSigned = ET == ARM64_AM::SXTW || ET == ARM64_AM::SXTX;
- Inst.addOperand(MCOperand::CreateImm(IsSigned));
- Inst.addOperand(MCOperand::CreateImm(getShiftExtendAmount() != 0));
- }
-
- // For 8-bit load/store instructions with a register offset, both the
- // "DoShift" and "NoShift" variants have a shift of 0. Because of this,
- // they're disambiguated by whether the shift was explicit or implicit rather
- // than its size.
- void addMemExtend8Operands(MCInst &Inst, unsigned N) const {
- assert(N == 2 && "Invalid number of operands!");
- ARM64_AM::ShiftExtendType ET = getShiftExtendType();
- bool IsSigned = ET == ARM64_AM::SXTW || ET == ARM64_AM::SXTX;
- Inst.addOperand(MCOperand::CreateImm(IsSigned));
- Inst.addOperand(MCOperand::CreateImm(hasShiftExtendAmount()));
- }
-
- template<int Shift>
- void addMOVZMovAliasOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
-
- const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
- uint64_t Value = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm((Value >> Shift) & 0xffff));
- }
-
- template<int Shift>
- void addMOVNMovAliasOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
-
- const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
- uint64_t Value = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm((~Value >> Shift) & 0xffff));
- }
-
- void print(raw_ostream &OS) const override;
-
- static ARM64Operand *CreateToken(StringRef Str, bool IsSuffix, SMLoc S,
- MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_Token, Ctx);
- Op->Tok.Data = Str.data();
- Op->Tok.Length = Str.size();
- Op->Tok.IsSuffix = IsSuffix;
- Op->StartLoc = S;
- Op->EndLoc = S;
- return Op;
- }
-
- static ARM64Operand *CreateReg(unsigned RegNum, bool isVector, SMLoc S,
- SMLoc E, MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_Register, Ctx);
- Op->Reg.RegNum = RegNum;
- Op->Reg.isVector = isVector;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- static ARM64Operand *CreateVectorList(unsigned RegNum, unsigned Count,
- unsigned NumElements, char ElementKind,
- SMLoc S, SMLoc E, MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_VectorList, Ctx);
- Op->VectorList.RegNum = RegNum;
- Op->VectorList.Count = Count;
- Op->VectorList.NumElements = NumElements;
- Op->VectorList.ElementKind = ElementKind;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- static ARM64Operand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
- MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_VectorIndex, Ctx);
- Op->VectorIndex.Val = Idx;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- static ARM64Operand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E,
- MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_Immediate, Ctx);
- Op->Imm.Val = Val;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- static ARM64Operand *CreateShiftedImm(const MCExpr *Val, unsigned ShiftAmount,
- SMLoc S, SMLoc E, MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_ShiftedImm, Ctx);
- Op->ShiftedImm .Val = Val;
- Op->ShiftedImm.ShiftAmount = ShiftAmount;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- static ARM64Operand *CreateCondCode(ARM64CC::CondCode Code, SMLoc S, SMLoc E,
- MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_CondCode, Ctx);
- Op->CondCode.Code = Code;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- static ARM64Operand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_FPImm, Ctx);
- Op->FPImm.Val = Val;
- Op->StartLoc = S;
- Op->EndLoc = S;
- return Op;
- }
-
- static ARM64Operand *CreateBarrier(unsigned Val, SMLoc S, MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_Barrier, Ctx);
- Op->Barrier.Val = Val;
- Op->StartLoc = S;
- Op->EndLoc = S;
- return Op;
- }
-
- static ARM64Operand *CreateSysReg(StringRef Str, SMLoc S,
- uint64_t FeatureBits, MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_SysReg, Ctx);
- Op->SysReg.Data = Str.data();
- Op->SysReg.Length = Str.size();
- Op->SysReg.FeatureBits = FeatureBits;
- Op->StartLoc = S;
- Op->EndLoc = S;
- return Op;
- }
-
- static ARM64Operand *CreateSysCR(unsigned Val, SMLoc S, SMLoc E,
- MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_SysCR, Ctx);
- Op->SysCRImm.Val = Val;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- static ARM64Operand *CreatePrefetch(unsigned Val, SMLoc S, MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_Prefetch, Ctx);
- Op->Prefetch.Val = Val;
- Op->StartLoc = S;
- Op->EndLoc = S;
- return Op;
- }
-
- static ARM64Operand *CreateShiftExtend(ARM64_AM::ShiftExtendType ShOp,
- unsigned Val, bool HasExplicitAmount,
- SMLoc S, SMLoc E, MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_ShiftExtend, Ctx);
- Op->ShiftExtend.Type = ShOp;
- Op->ShiftExtend.Amount = Val;
- Op->ShiftExtend.HasExplicitAmount = HasExplicitAmount;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-};
-
-} // end anonymous namespace.
-
-void ARM64Operand::print(raw_ostream &OS) const {
- switch (Kind) {
- case k_FPImm:
- OS << "<fpimm " << getFPImm() << "(" << ARM64_AM::getFPImmFloat(getFPImm())
- << ") >";
- break;
- case k_Barrier: {
- bool Valid;
- StringRef Name = ARM64DB::DBarrierMapper().toString(getBarrier(), Valid);
- if (Valid)
- OS << "<barrier " << Name << ">";
- else
- OS << "<barrier invalid #" << getBarrier() << ">";
- break;
- }
- case k_Immediate:
- getImm()->print(OS);
- break;
- case k_ShiftedImm: {
- unsigned Shift = getShiftedImmShift();
- OS << "<shiftedimm ";
- getShiftedImmVal()->print(OS);
- OS << ", lsl #" << ARM64_AM::getShiftValue(Shift) << ">";
- break;
- }
- case k_CondCode:
- OS << "<condcode " << getCondCode() << ">";
- break;
- case k_Register:
- OS << "<register " << getReg() << ">";
- break;
- case k_VectorList: {
- OS << "<vectorlist ";
- unsigned Reg = getVectorListStart();
- for (unsigned i = 0, e = getVectorListCount(); i != e; ++i)
- OS << Reg + i << " ";
- OS << ">";
- break;
- }
- case k_VectorIndex:
- OS << "<vectorindex " << getVectorIndex() << ">";
- break;
- case k_SysReg:
- OS << "<sysreg: " << getSysReg() << '>';
- break;
- case k_Token:
- OS << "'" << getToken() << "'";
- break;
- case k_SysCR:
- OS << "c" << getSysCR();
- break;
- case k_Prefetch: {
- bool Valid;
- StringRef Name = ARM64PRFM::PRFMMapper().toString(getPrefetch(), Valid);
- if (Valid)
- OS << "<prfop " << Name << ">";
- else
- OS << "<prfop invalid #" << getPrefetch() << ">";
- break;
- }
- case k_ShiftExtend: {
- OS << "<" << ARM64_AM::getShiftExtendName(getShiftExtendType()) << " #"
- << getShiftExtendAmount();
- if (!hasShiftExtendAmount())
- OS << "<imp>";
- OS << '>';
- break;
- }
- }
-}
-
-/// @name Auto-generated Match Functions
-/// {
-
-static unsigned MatchRegisterName(StringRef Name);
-
-/// }
-
-static unsigned matchVectorRegName(StringRef Name) {
- return StringSwitch<unsigned>(Name)
- .Case("v0", ARM64::Q0)
- .Case("v1", ARM64::Q1)
- .Case("v2", ARM64::Q2)
- .Case("v3", ARM64::Q3)
- .Case("v4", ARM64::Q4)
- .Case("v5", ARM64::Q5)
- .Case("v6", ARM64::Q6)
- .Case("v7", ARM64::Q7)
- .Case("v8", ARM64::Q8)
- .Case("v9", ARM64::Q9)
- .Case("v10", ARM64::Q10)
- .Case("v11", ARM64::Q11)
- .Case("v12", ARM64::Q12)
- .Case("v13", ARM64::Q13)
- .Case("v14", ARM64::Q14)
- .Case("v15", ARM64::Q15)
- .Case("v16", ARM64::Q16)
- .Case("v17", ARM64::Q17)
- .Case("v18", ARM64::Q18)
- .Case("v19", ARM64::Q19)
- .Case("v20", ARM64::Q20)
- .Case("v21", ARM64::Q21)
- .Case("v22", ARM64::Q22)
- .Case("v23", ARM64::Q23)
- .Case("v24", ARM64::Q24)
- .Case("v25", ARM64::Q25)
- .Case("v26", ARM64::Q26)
- .Case("v27", ARM64::Q27)
- .Case("v28", ARM64::Q28)
- .Case("v29", ARM64::Q29)
- .Case("v30", ARM64::Q30)
- .Case("v31", ARM64::Q31)
- .Default(0);
-}
-
-static bool isValidVectorKind(StringRef Name) {
- return StringSwitch<bool>(Name.lower())
- .Case(".8b", true)
- .Case(".16b", true)
- .Case(".4h", true)
- .Case(".8h", true)
- .Case(".2s", true)
- .Case(".4s", true)
- .Case(".1d", true)
- .Case(".2d", true)
- .Case(".1q", true)
- // Accept the width neutral ones, too, for verbose syntax. If those
- // aren't used in the right places, the token operand won't match so
- // all will work out.
- .Case(".b", true)
- .Case(".h", true)
- .Case(".s", true)
- .Case(".d", true)
- .Default(false);
-}
-
-static void parseValidVectorKind(StringRef Name, unsigned &NumElements,
- char &ElementKind) {
- assert(isValidVectorKind(Name));
-
- ElementKind = Name.lower()[Name.size() - 1];
- NumElements = 0;
-
- if (Name.size() == 2)
- return;
-
- // Parse the lane count
- Name = Name.drop_front();
- while (isdigit(Name.front())) {
- NumElements = 10 * NumElements + (Name.front() - '0');
- Name = Name.drop_front();
- }
-}
-
-bool ARM64AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
- SMLoc &EndLoc) {
- StartLoc = getLoc();
- RegNo = tryParseRegister();
- EndLoc = SMLoc::getFromPointer(getLoc().getPointer() - 1);
- return (RegNo == (unsigned)-1);
-}
-
-/// tryParseRegister - Try to parse a register name. The token must be an
-/// Identifier when called, and if it is a register name the token is eaten and
-/// the register is added to the operand list.
-int ARM64AsmParser::tryParseRegister() {
- const AsmToken &Tok = Parser.getTok();
- assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
-
- std::string lowerCase = Tok.getString().lower();
- unsigned RegNum = MatchRegisterName(lowerCase);
- // Also handle a few aliases of registers.
- if (RegNum == 0)
- RegNum = StringSwitch<unsigned>(lowerCase)
- .Case("fp", ARM64::FP)
- .Case("lr", ARM64::LR)
- .Case("x31", ARM64::XZR)
- .Case("w31", ARM64::WZR)
- .Default(0);
-
- if (RegNum == 0)
- return -1;
-
- Parser.Lex(); // Eat identifier token.
- return RegNum;
-}
-
-/// tryMatchVectorRegister - Try to parse a vector register name with optional
-/// kind specifier. If it is a register specifier, eat the token and return it.
-int ARM64AsmParser::tryMatchVectorRegister(StringRef &Kind, bool expected) {
- if (Parser.getTok().isNot(AsmToken::Identifier)) {
- TokError("vector register expected");
- return -1;
- }
-
- StringRef Name = Parser.getTok().getString();
- // If there is a kind specifier, it's separated from the register name by
- // a '.'.
- size_t Start = 0, Next = Name.find('.');
- StringRef Head = Name.slice(Start, Next);
- unsigned RegNum = matchVectorRegName(Head);
- if (RegNum) {
- if (Next != StringRef::npos) {
- Kind = Name.slice(Next, StringRef::npos);
- if (!isValidVectorKind(Kind)) {
- TokError("invalid vector kind qualifier");
- return -1;
- }
- }
- Parser.Lex(); // Eat the register token.
- return RegNum;
- }
-
- if (expected)
- TokError("vector register expected");
- return -1;
-}
-
-/// tryParseSysCROperand - Try to parse a system instruction CR operand name.
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
- SMLoc S = getLoc();
-
- if (Parser.getTok().isNot(AsmToken::Identifier)) {
- Error(S, "Expected cN operand where 0 <= N <= 15");
- return MatchOperand_ParseFail;
- }
-
- StringRef Tok = Parser.getTok().getIdentifier();
- if (Tok[0] != 'c' && Tok[0] != 'C') {
- Error(S, "Expected cN operand where 0 <= N <= 15");
- return MatchOperand_ParseFail;
- }
-
- uint32_t CRNum;
- bool BadNum = Tok.drop_front().getAsInteger(10, CRNum);
- if (BadNum || CRNum > 15) {
- Error(S, "Expected cN operand where 0 <= N <= 15");
- return MatchOperand_ParseFail;
- }
-
- Parser.Lex(); // Eat identifier token.
- Operands.push_back(ARM64Operand::CreateSysCR(CRNum, S, getLoc(), getContext()));
- return MatchOperand_Success;
-}
-
-/// tryParsePrefetch - Try to parse a prefetch operand.
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParsePrefetch(OperandVector &Operands) {
- SMLoc S = getLoc();
- const AsmToken &Tok = Parser.getTok();
- // Either an identifier for named values or a 5-bit immediate.
- bool Hash = Tok.is(AsmToken::Hash);
- if (Hash || Tok.is(AsmToken::Integer)) {
- if (Hash)
- Parser.Lex(); // Eat hash token.
- const MCExpr *ImmVal;
- if (getParser().parseExpression(ImmVal))
- return MatchOperand_ParseFail;
-
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
- if (!MCE) {
- TokError("immediate value expected for prefetch operand");
- return MatchOperand_ParseFail;
- }
- unsigned prfop = MCE->getValue();
- if (prfop > 31) {
- TokError("prefetch operand out of range, [0,31] expected");
- return MatchOperand_ParseFail;
- }
-
- Operands.push_back(ARM64Operand::CreatePrefetch(prfop, S, getContext()));
- return MatchOperand_Success;
- }
-
- if (Tok.isNot(AsmToken::Identifier)) {
- TokError("pre-fetch hint expected");
- return MatchOperand_ParseFail;
- }
-
- bool Valid;
- unsigned prfop = ARM64PRFM::PRFMMapper().fromString(Tok.getString(), Valid);
- if (!Valid) {
- TokError("pre-fetch hint expected");
- return MatchOperand_ParseFail;
- }
-
- Parser.Lex(); // Eat identifier token.
- Operands.push_back(ARM64Operand::CreatePrefetch(prfop, S, getContext()));
- return MatchOperand_Success;
-}
-
-/// tryParseAdrpLabel - Parse and validate a source label for the ADRP
-/// instruction.
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
- SMLoc S = getLoc();
- const MCExpr *Expr;
-
- if (Parser.getTok().is(AsmToken::Hash)) {
- Parser.Lex(); // Eat hash token.
- }
-
- if (parseSymbolicImmVal(Expr))
- return MatchOperand_ParseFail;
-
- ARM64MCExpr::VariantKind ELFRefKind;
- MCSymbolRefExpr::VariantKind DarwinRefKind;
- int64_t Addend;
- if (classifySymbolRef(Expr, ELFRefKind, DarwinRefKind, Addend)) {
- if (DarwinRefKind == MCSymbolRefExpr::VK_None &&
- ELFRefKind == ARM64MCExpr::VK_INVALID) {
- // No modifier was specified at all; this is the syntax for an ELF basic
- // ADRP relocation (unfortunately).
- Expr = ARM64MCExpr::Create(Expr, ARM64MCExpr::VK_ABS_PAGE, getContext());
- } else if ((DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGE ||
- DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGE) &&
- Addend != 0) {
- Error(S, "gotpage label reference not allowed an addend");
- return MatchOperand_ParseFail;
- } else if (DarwinRefKind != MCSymbolRefExpr::VK_PAGE &&
- DarwinRefKind != MCSymbolRefExpr::VK_GOTPAGE &&
- DarwinRefKind != MCSymbolRefExpr::VK_TLVPPAGE &&
- ELFRefKind != ARM64MCExpr::VK_GOT_PAGE &&
- ELFRefKind != ARM64MCExpr::VK_GOTTPREL_PAGE &&
- ELFRefKind != ARM64MCExpr::VK_TLSDESC_PAGE) {
- // The operand must be an @page or @gotpage qualified symbolref.
- Error(S, "page or gotpage label reference expected");
- return MatchOperand_ParseFail;
- }
- }
-
- // We have either a label reference possibly with addend or an immediate. The
- // addend is a raw value here. The linker will adjust it to only reference the
- // page.
- SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
- Operands.push_back(ARM64Operand::CreateImm(Expr, S, E, getContext()));
-
- return MatchOperand_Success;
-}
-
-/// tryParseAdrLabel - Parse and validate a source label for the ADR
-/// instruction.
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
- SMLoc S = getLoc();
- const MCExpr *Expr;
-
- if (Parser.getTok().is(AsmToken::Hash)) {
- Parser.Lex(); // Eat hash token.
- }
-
- if (getParser().parseExpression(Expr))
- return MatchOperand_ParseFail;
-
- SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
- Operands.push_back(ARM64Operand::CreateImm(Expr, S, E, getContext()));
-
- return MatchOperand_Success;
-}
-
-/// tryParseFPImm - A floating point immediate expression operand.
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseFPImm(OperandVector &Operands) {
- SMLoc S = getLoc();
-
- bool Hash = false;
- if (Parser.getTok().is(AsmToken::Hash)) {
- Parser.Lex(); // Eat '#'
- Hash = true;
- }
-
- // Handle negation, as that still comes through as a separate token.
- bool isNegative = false;
- if (Parser.getTok().is(AsmToken::Minus)) {
- isNegative = true;
- Parser.Lex();
- }
- const AsmToken &Tok = Parser.getTok();
- if (Tok.is(AsmToken::Real)) {
- APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
- uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
- // If we had a '-' in front, toggle the sign bit.
- IntVal ^= (uint64_t)isNegative << 63;
- int Val = ARM64_AM::getFP64Imm(APInt(64, IntVal));
- Parser.Lex(); // Eat the token.
- // Check for out of range values. As an exception, we let Zero through,
- // as we handle that special case in post-processing before matching in
- // order to use the zero register for it.
- if (Val == -1 && !RealVal.isZero()) {
- TokError("expected compatible register or floating-point constant");
- return MatchOperand_ParseFail;
- }
- Operands.push_back(ARM64Operand::CreateFPImm(Val, S, getContext()));
- return MatchOperand_Success;
- }
- if (Tok.is(AsmToken::Integer)) {
- int64_t Val;
- if (!isNegative && Tok.getString().startswith("0x")) {
- Val = Tok.getIntVal();
- if (Val > 255 || Val < 0) {
- TokError("encoded floating point value out of range");
- return MatchOperand_ParseFail;
- }
- } else {
- APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
- uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
- // If we had a '-' in front, toggle the sign bit.
- IntVal ^= (uint64_t)isNegative << 63;
- Val = ARM64_AM::getFP64Imm(APInt(64, IntVal));
- }
- Parser.Lex(); // Eat the token.
- Operands.push_back(ARM64Operand::CreateFPImm(Val, S, getContext()));
- return MatchOperand_Success;
- }
-
- if (!Hash)
- return MatchOperand_NoMatch;
-
- TokError("invalid floating point immediate");
- return MatchOperand_ParseFail;
-}
-
-/// tryParseAddSubImm - Parse ADD/SUB shifted immediate operand
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseAddSubImm(OperandVector &Operands) {
- SMLoc S = getLoc();
-
- if (Parser.getTok().is(AsmToken::Hash))
- Parser.Lex(); // Eat '#'
- else if (Parser.getTok().isNot(AsmToken::Integer))
- // Operand should start from # or should be integer, emit error otherwise.
- return MatchOperand_NoMatch;
-
- const MCExpr *Imm;
- if (parseSymbolicImmVal(Imm))
- return MatchOperand_ParseFail;
- else if (Parser.getTok().isNot(AsmToken::Comma)) {
- uint64_t ShiftAmount = 0;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Imm);
- if (MCE) {
- int64_t Val = MCE->getValue();
- if (Val > 0xfff && (Val & 0xfff) == 0) {
- Imm = MCConstantExpr::Create(Val >> 12, getContext());
- ShiftAmount = 12;
- }
- }
- SMLoc E = Parser.getTok().getLoc();
- Operands.push_back(ARM64Operand::CreateShiftedImm(Imm, ShiftAmount, S, E,
- getContext()));
- return MatchOperand_Success;
- }
-
- // Eat ','
- Parser.Lex();
-
- // The optional operand must be "lsl #N" where N is non-negative.
- if (!Parser.getTok().is(AsmToken::Identifier) ||
- !Parser.getTok().getIdentifier().equals_lower("lsl")) {
- Error(Parser.getTok().getLoc(), "only 'lsl #+N' valid after immediate");
- return MatchOperand_ParseFail;
- }
-
- // Eat 'lsl'
- Parser.Lex();
-
- if (Parser.getTok().is(AsmToken::Hash)) {
- Parser.Lex();
- }
-
- if (Parser.getTok().isNot(AsmToken::Integer)) {
- Error(Parser.getTok().getLoc(), "only 'lsl #+N' valid after immediate");
- return MatchOperand_ParseFail;
- }
-
- int64_t ShiftAmount = Parser.getTok().getIntVal();
-
- if (ShiftAmount < 0) {
- Error(Parser.getTok().getLoc(), "positive shift amount required");
- return MatchOperand_ParseFail;
- }
- Parser.Lex(); // Eat the number
-
- SMLoc E = Parser.getTok().getLoc();
- Operands.push_back(ARM64Operand::CreateShiftedImm(Imm, ShiftAmount,
- S, E, getContext()));
- return MatchOperand_Success;
-}
-
-/// parseCondCodeString - Parse a Condition Code string.
-ARM64CC::CondCode ARM64AsmParser::parseCondCodeString(StringRef Cond) {
- ARM64CC::CondCode CC = StringSwitch<ARM64CC::CondCode>(Cond.lower())
- .Case("eq", ARM64CC::EQ)
- .Case("ne", ARM64CC::NE)
- .Case("cs", ARM64CC::HS)
- .Case("hs", ARM64CC::HS)
- .Case("cc", ARM64CC::LO)
- .Case("lo", ARM64CC::LO)
- .Case("mi", ARM64CC::MI)
- .Case("pl", ARM64CC::PL)
- .Case("vs", ARM64CC::VS)
- .Case("vc", ARM64CC::VC)
- .Case("hi", ARM64CC::HI)
- .Case("ls", ARM64CC::LS)
- .Case("ge", ARM64CC::GE)
- .Case("lt", ARM64CC::LT)
- .Case("gt", ARM64CC::GT)
- .Case("le", ARM64CC::LE)
- .Case("al", ARM64CC::AL)
- .Case("nv", ARM64CC::NV)
- .Default(ARM64CC::Invalid);
- return CC;
-}
-
-/// parseCondCode - Parse a Condition Code operand.
-bool ARM64AsmParser::parseCondCode(OperandVector &Operands,
- bool invertCondCode) {
- SMLoc S = getLoc();
- const AsmToken &Tok = Parser.getTok();
- assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
-
- StringRef Cond = Tok.getString();
- ARM64CC::CondCode CC = parseCondCodeString(Cond);
- if (CC == ARM64CC::Invalid)
- return TokError("invalid condition code");
- Parser.Lex(); // Eat identifier token.
-
- if (invertCondCode)
- CC = ARM64CC::getInvertedCondCode(ARM64CC::CondCode(CC));
-
- Operands.push_back(
- ARM64Operand::CreateCondCode(CC, S, getLoc(), getContext()));
- return false;
-}
-
-/// tryParseOptionalShift - Some operands take an optional shift argument. Parse
-/// them if present.
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
- const AsmToken &Tok = Parser.getTok();
- std::string LowerID = Tok.getString().lower();
- ARM64_AM::ShiftExtendType ShOp =
- StringSwitch<ARM64_AM::ShiftExtendType>(LowerID)
- .Case("lsl", ARM64_AM::LSL)
- .Case("lsr", ARM64_AM::LSR)
- .Case("asr", ARM64_AM::ASR)
- .Case("ror", ARM64_AM::ROR)
- .Case("msl", ARM64_AM::MSL)
- .Case("uxtb", ARM64_AM::UXTB)
- .Case("uxth", ARM64_AM::UXTH)
- .Case("uxtw", ARM64_AM::UXTW)
- .Case("uxtx", ARM64_AM::UXTX)
- .Case("sxtb", ARM64_AM::SXTB)
- .Case("sxth", ARM64_AM::SXTH)
- .Case("sxtw", ARM64_AM::SXTW)
- .Case("sxtx", ARM64_AM::SXTX)
- .Default(ARM64_AM::InvalidShiftExtend);
-
- if (ShOp == ARM64_AM::InvalidShiftExtend)
- return MatchOperand_NoMatch;
-
- SMLoc S = Tok.getLoc();
- Parser.Lex();
-
- bool Hash = getLexer().is(AsmToken::Hash);
- if (!Hash && getLexer().isNot(AsmToken::Integer)) {
- if (ShOp == ARM64_AM::LSL || ShOp == ARM64_AM::LSR ||
- ShOp == ARM64_AM::ASR || ShOp == ARM64_AM::ROR ||
- ShOp == ARM64_AM::MSL) {
- // We expect a number here.
- TokError("expected #imm after shift specifier");
- return MatchOperand_ParseFail;
- }
-
- // "extend" type operatoins don't need an immediate, #0 is implicit.
- SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
- Operands.push_back(
- ARM64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext()));
- return MatchOperand_Success;
- }
-
- if (Hash)
- Parser.Lex(); // Eat the '#'.
-
- // Make sure we do actually have a number
- if (!Parser.getTok().is(AsmToken::Integer)) {
- Error(Parser.getTok().getLoc(),
- "expected integer shift amount");
- return MatchOperand_ParseFail;
- }
-
- const MCExpr *ImmVal;
- if (getParser().parseExpression(ImmVal))
- return MatchOperand_ParseFail;
-
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
- if (!MCE) {
- TokError("expected #imm after shift specifier");
- return MatchOperand_ParseFail;
- }
-
- SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
- Operands.push_back(ARM64Operand::CreateShiftExtend(ShOp, MCE->getValue(),
- true, S, E, getContext()));
- return MatchOperand_Success;
-}
-
-/// parseSysAlias - The IC, DC, AT, and TLBI instructions are simple aliases for
-/// the SYS instruction. Parse them specially so that we create a SYS MCInst.
-bool ARM64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
- OperandVector &Operands) {
- if (Name.find('.') != StringRef::npos)
- return TokError("invalid operand");
-
- Mnemonic = Name;
- Operands.push_back(
- ARM64Operand::CreateToken("sys", false, NameLoc, getContext()));
-
- const AsmToken &Tok = Parser.getTok();
- StringRef Op = Tok.getString();
- SMLoc S = Tok.getLoc();
-
- const MCExpr *Expr = nullptr;
-
-#define SYS_ALIAS(op1, Cn, Cm, op2) \
- do { \
- Expr = MCConstantExpr::Create(op1, getContext()); \
- Operands.push_back( \
- ARM64Operand::CreateImm(Expr, S, getLoc(), getContext())); \
- Operands.push_back( \
- ARM64Operand::CreateSysCR(Cn, S, getLoc(), getContext())); \
- Operands.push_back( \
- ARM64Operand::CreateSysCR(Cm, S, getLoc(), getContext())); \
- Expr = MCConstantExpr::Create(op2, getContext()); \
- Operands.push_back( \
- ARM64Operand::CreateImm(Expr, S, getLoc(), getContext())); \
- } while (0)
-
- if (Mnemonic == "ic") {
- if (!Op.compare_lower("ialluis")) {
- // SYS #0, C7, C1, #0
- SYS_ALIAS(0, 7, 1, 0);
- } else if (!Op.compare_lower("iallu")) {
- // SYS #0, C7, C5, #0
- SYS_ALIAS(0, 7, 5, 0);
- } else if (!Op.compare_lower("ivau")) {
- // SYS #3, C7, C5, #1
- SYS_ALIAS(3, 7, 5, 1);
- } else {
- return TokError("invalid operand for IC instruction");
- }
- } else if (Mnemonic == "dc") {
- if (!Op.compare_lower("zva")) {
- // SYS #3, C7, C4, #1
- SYS_ALIAS(3, 7, 4, 1);
- } else if (!Op.compare_lower("ivac")) {
- // SYS #3, C7, C6, #1
- SYS_ALIAS(0, 7, 6, 1);
- } else if (!Op.compare_lower("isw")) {
- // SYS #0, C7, C6, #2
- SYS_ALIAS(0, 7, 6, 2);
- } else if (!Op.compare_lower("cvac")) {
- // SYS #3, C7, C10, #1
- SYS_ALIAS(3, 7, 10, 1);
- } else if (!Op.compare_lower("csw")) {
- // SYS #0, C7, C10, #2
- SYS_ALIAS(0, 7, 10, 2);
- } else if (!Op.compare_lower("cvau")) {
- // SYS #3, C7, C11, #1
- SYS_ALIAS(3, 7, 11, 1);
- } else if (!Op.compare_lower("civac")) {
- // SYS #3, C7, C14, #1
- SYS_ALIAS(3, 7, 14, 1);
- } else if (!Op.compare_lower("cisw")) {
- // SYS #0, C7, C14, #2
- SYS_ALIAS(0, 7, 14, 2);
- } else {
- return TokError("invalid operand for DC instruction");
- }
- } else if (Mnemonic == "at") {
- if (!Op.compare_lower("s1e1r")) {
- // SYS #0, C7, C8, #0
- SYS_ALIAS(0, 7, 8, 0);
- } else if (!Op.compare_lower("s1e2r")) {
- // SYS #4, C7, C8, #0
- SYS_ALIAS(4, 7, 8, 0);
- } else if (!Op.compare_lower("s1e3r")) {
- // SYS #6, C7, C8, #0
- SYS_ALIAS(6, 7, 8, 0);
- } else if (!Op.compare_lower("s1e1w")) {
- // SYS #0, C7, C8, #1
- SYS_ALIAS(0, 7, 8, 1);
- } else if (!Op.compare_lower("s1e2w")) {
- // SYS #4, C7, C8, #1
- SYS_ALIAS(4, 7, 8, 1);
- } else if (!Op.compare_lower("s1e3w")) {
- // SYS #6, C7, C8, #1
- SYS_ALIAS(6, 7, 8, 1);
- } else if (!Op.compare_lower("s1e0r")) {
- // SYS #0, C7, C8, #3
- SYS_ALIAS(0, 7, 8, 2);
- } else if (!Op.compare_lower("s1e0w")) {
- // SYS #0, C7, C8, #3
- SYS_ALIAS(0, 7, 8, 3);
- } else if (!Op.compare_lower("s12e1r")) {
- // SYS #4, C7, C8, #4
- SYS_ALIAS(4, 7, 8, 4);
- } else if (!Op.compare_lower("s12e1w")) {
- // SYS #4, C7, C8, #5
- SYS_ALIAS(4, 7, 8, 5);
- } else if (!Op.compare_lower("s12e0r")) {
- // SYS #4, C7, C8, #6
- SYS_ALIAS(4, 7, 8, 6);
- } else if (!Op.compare_lower("s12e0w")) {
- // SYS #4, C7, C8, #7
- SYS_ALIAS(4, 7, 8, 7);
- } else {
- return TokError("invalid operand for AT instruction");
- }
- } else if (Mnemonic == "tlbi") {
- if (!Op.compare_lower("vmalle1is")) {
- // SYS #0, C8, C3, #0
- SYS_ALIAS(0, 8, 3, 0);
- } else if (!Op.compare_lower("alle2is")) {
- // SYS #4, C8, C3, #0
- SYS_ALIAS(4, 8, 3, 0);
- } else if (!Op.compare_lower("alle3is")) {
- // SYS #6, C8, C3, #0
- SYS_ALIAS(6, 8, 3, 0);
- } else if (!Op.compare_lower("vae1is")) {
- // SYS #0, C8, C3, #1
- SYS_ALIAS(0, 8, 3, 1);
- } else if (!Op.compare_lower("vae2is")) {
- // SYS #4, C8, C3, #1
- SYS_ALIAS(4, 8, 3, 1);
- } else if (!Op.compare_lower("vae3is")) {
- // SYS #6, C8, C3, #1
- SYS_ALIAS(6, 8, 3, 1);
- } else if (!Op.compare_lower("aside1is")) {
- // SYS #0, C8, C3, #2
- SYS_ALIAS(0, 8, 3, 2);
- } else if (!Op.compare_lower("vaae1is")) {
- // SYS #0, C8, C3, #3
- SYS_ALIAS(0, 8, 3, 3);
- } else if (!Op.compare_lower("alle1is")) {
- // SYS #4, C8, C3, #4
- SYS_ALIAS(4, 8, 3, 4);
- } else if (!Op.compare_lower("vale1is")) {
- // SYS #0, C8, C3, #5
- SYS_ALIAS(0, 8, 3, 5);
- } else if (!Op.compare_lower("vaale1is")) {
- // SYS #0, C8, C3, #7
- SYS_ALIAS(0, 8, 3, 7);
- } else if (!Op.compare_lower("vmalle1")) {
- // SYS #0, C8, C7, #0
- SYS_ALIAS(0, 8, 7, 0);
- } else if (!Op.compare_lower("alle2")) {
- // SYS #4, C8, C7, #0
- SYS_ALIAS(4, 8, 7, 0);
- } else if (!Op.compare_lower("vale2is")) {
- // SYS #4, C8, C3, #5
- SYS_ALIAS(4, 8, 3, 5);
- } else if (!Op.compare_lower("vale3is")) {
- // SYS #6, C8, C3, #5
- SYS_ALIAS(6, 8, 3, 5);
- } else if (!Op.compare_lower("alle3")) {
- // SYS #6, C8, C7, #0
- SYS_ALIAS(6, 8, 7, 0);
- } else if (!Op.compare_lower("vae1")) {
- // SYS #0, C8, C7, #1
- SYS_ALIAS(0, 8, 7, 1);
- } else if (!Op.compare_lower("vae2")) {
- // SYS #4, C8, C7, #1
- SYS_ALIAS(4, 8, 7, 1);
- } else if (!Op.compare_lower("vae3")) {
- // SYS #6, C8, C7, #1
- SYS_ALIAS(6, 8, 7, 1);
- } else if (!Op.compare_lower("aside1")) {
- // SYS #0, C8, C7, #2
- SYS_ALIAS(0, 8, 7, 2);
- } else if (!Op.compare_lower("vaae1")) {
- // SYS #0, C8, C7, #3
- SYS_ALIAS(0, 8, 7, 3);
- } else if (!Op.compare_lower("alle1")) {
- // SYS #4, C8, C7, #4
- SYS_ALIAS(4, 8, 7, 4);
- } else if (!Op.compare_lower("vale1")) {
- // SYS #0, C8, C7, #5
- SYS_ALIAS(0, 8, 7, 5);
- } else if (!Op.compare_lower("vale2")) {
- // SYS #4, C8, C7, #5
- SYS_ALIAS(4, 8, 7, 5);
- } else if (!Op.compare_lower("vale3")) {
- // SYS #6, C8, C7, #5
- SYS_ALIAS(6, 8, 7, 5);
- } else if (!Op.compare_lower("vaale1")) {
- // SYS #0, C8, C7, #7
- SYS_ALIAS(0, 8, 7, 7);
- } else if (!Op.compare_lower("ipas2e1")) {
- // SYS #4, C8, C4, #1
- SYS_ALIAS(4, 8, 4, 1);
- } else if (!Op.compare_lower("ipas2le1")) {
- // SYS #4, C8, C4, #5
- SYS_ALIAS(4, 8, 4, 5);
- } else if (!Op.compare_lower("ipas2e1is")) {
- // SYS #4, C8, C4, #1
- SYS_ALIAS(4, 8, 0, 1);
- } else if (!Op.compare_lower("ipas2le1is")) {
- // SYS #4, C8, C4, #5
- SYS_ALIAS(4, 8, 0, 5);
- } else if (!Op.compare_lower("vmalls12e1")) {
- // SYS #4, C8, C7, #6
- SYS_ALIAS(4, 8, 7, 6);
- } else if (!Op.compare_lower("vmalls12e1is")) {
- // SYS #4, C8, C3, #6
- SYS_ALIAS(4, 8, 3, 6);
- } else {
- return TokError("invalid operand for TLBI instruction");
- }
- }
-
-#undef SYS_ALIAS
-
- Parser.Lex(); // Eat operand.
-
- bool ExpectRegister = (Op.lower().find("all") == StringRef::npos);
- bool HasRegister = false;
-
- // Check for the optional register operand.
- if (getLexer().is(AsmToken::Comma)) {
- Parser.Lex(); // Eat comma.
-
- if (Tok.isNot(AsmToken::Identifier) || parseRegister(Operands))
- return TokError("expected register operand");
-
- HasRegister = true;
- }
-
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- Parser.eatToEndOfStatement();
- return TokError("unexpected token in argument list");
- }
-
- if (ExpectRegister && !HasRegister) {
- return TokError("specified " + Mnemonic + " op requires a register");
- }
- else if (!ExpectRegister && HasRegister) {
- return TokError("specified " + Mnemonic + " op does not use a register");
- }
-
- Parser.Lex(); // Consume the EndOfStatement
- return false;
-}
-
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
- const AsmToken &Tok = Parser.getTok();
-
- // Can be either a #imm style literal or an option name
- bool Hash = Tok.is(AsmToken::Hash);
- if (Hash || Tok.is(AsmToken::Integer)) {
- // Immediate operand.
- if (Hash)
- Parser.Lex(); // Eat the '#'
- const MCExpr *ImmVal;
- SMLoc ExprLoc = getLoc();
- if (getParser().parseExpression(ImmVal))
- return MatchOperand_ParseFail;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
- if (!MCE) {
- Error(ExprLoc, "immediate value expected for barrier operand");
- return MatchOperand_ParseFail;
- }
- if (MCE->getValue() < 0 || MCE->getValue() > 15) {
- Error(ExprLoc, "barrier operand out of range");
- return MatchOperand_ParseFail;
- }
- Operands.push_back(
- ARM64Operand::CreateBarrier(MCE->getValue(), ExprLoc, getContext()));
- return MatchOperand_Success;
- }
-
- if (Tok.isNot(AsmToken::Identifier)) {
- TokError("invalid operand for instruction");
- return MatchOperand_ParseFail;
- }
-
- bool Valid;
- unsigned Opt = ARM64DB::DBarrierMapper().fromString(Tok.getString(), Valid);
- if (!Valid) {
- TokError("invalid barrier option name");
- return MatchOperand_ParseFail;
- }
-
- // The only valid named option for ISB is 'sy'
- if (Mnemonic == "isb" && Opt != ARM64DB::SY) {
- TokError("'sy' or #imm operand expected");
- return MatchOperand_ParseFail;
- }
-
- Operands.push_back(ARM64Operand::CreateBarrier(Opt, getLoc(), getContext()));
- Parser.Lex(); // Consume the option
-
- return MatchOperand_Success;
-}
-
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseSysReg(OperandVector &Operands) {
- const AsmToken &Tok = Parser.getTok();
-
- if (Tok.isNot(AsmToken::Identifier))
- return MatchOperand_NoMatch;
-
- Operands.push_back(ARM64Operand::CreateSysReg(Tok.getString(), getLoc(),
- STI.getFeatureBits(), getContext()));
- Parser.Lex(); // Eat identifier
-
- return MatchOperand_Success;
-}
-
-/// tryParseVectorRegister - Parse a vector register operand.
-bool ARM64AsmParser::tryParseVectorRegister(OperandVector &Operands) {
- if (Parser.getTok().isNot(AsmToken::Identifier))
- return true;
-
- SMLoc S = getLoc();
- // Check for a vector register specifier first.
- StringRef Kind;
- int64_t Reg = tryMatchVectorRegister(Kind, false);
- if (Reg == -1)
- return true;
- Operands.push_back(
- ARM64Operand::CreateReg(Reg, true, S, getLoc(), getContext()));
- // If there was an explicit qualifier, that goes on as a literal text
- // operand.
- if (!Kind.empty())
- Operands.push_back(ARM64Operand::CreateToken(Kind, false, S, getContext()));
-
- // If there is an index specifier following the register, parse that too.
- if (Parser.getTok().is(AsmToken::LBrac)) {
- SMLoc SIdx = getLoc();
- Parser.Lex(); // Eat left bracket token.
-
- const MCExpr *ImmVal;
- if (getParser().parseExpression(ImmVal))
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
- if (!MCE) {
- TokError("immediate value expected for vector index");
- return false;
- }
-
- SMLoc E = getLoc();
- if (Parser.getTok().isNot(AsmToken::RBrac)) {
- Error(E, "']' expected");
- return false;
- }
-
- Parser.Lex(); // Eat right bracket token.
-
- Operands.push_back(ARM64Operand::CreateVectorIndex(MCE->getValue(), SIdx, E,
- getContext()));
- }
-
- return false;
-}
-
-/// parseRegister - Parse a non-vector register operand.
-bool ARM64AsmParser::parseRegister(OperandVector &Operands) {
- SMLoc S = getLoc();
- // Try for a vector register.
- if (!tryParseVectorRegister(Operands))
- return false;
-
- // Try for a scalar register.
- int64_t Reg = tryParseRegister();
- if (Reg == -1)
- return true;
- Operands.push_back(
- ARM64Operand::CreateReg(Reg, false, S, getLoc(), getContext()));
-
- // A small number of instructions (FMOVXDhighr, for example) have "[1]"
- // as a string token in the instruction itself.
- if (getLexer().getKind() == AsmToken::LBrac) {
- SMLoc LBracS = getLoc();
- Parser.Lex();
- const AsmToken &Tok = Parser.getTok();
- if (Tok.is(AsmToken::Integer)) {
- SMLoc IntS = getLoc();
- int64_t Val = Tok.getIntVal();
- if (Val == 1) {
- Parser.Lex();
- if (getLexer().getKind() == AsmToken::RBrac) {
- SMLoc RBracS = getLoc();
- Parser.Lex();
- Operands.push_back(
- ARM64Operand::CreateToken("[", false, LBracS, getContext()));
- Operands.push_back(
- ARM64Operand::CreateToken("1", false, IntS, getContext()));
- Operands.push_back(
- ARM64Operand::CreateToken("]", false, RBracS, getContext()));
- return false;
- }
- }
- }
- }
-
- return false;
-}
-
-bool ARM64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
- bool HasELFModifier = false;
- ARM64MCExpr::VariantKind RefKind;
-
- if (Parser.getTok().is(AsmToken::Colon)) {
- Parser.Lex(); // Eat ':"
- HasELFModifier = true;
-
- if (Parser.getTok().isNot(AsmToken::Identifier)) {
- Error(Parser.getTok().getLoc(),
- "expect relocation specifier in operand after ':'");
- return true;
- }
-
- std::string LowerCase = Parser.getTok().getIdentifier().lower();
- RefKind = StringSwitch<ARM64MCExpr::VariantKind>(LowerCase)
- .Case("lo12", ARM64MCExpr::VK_LO12)
- .Case("abs_g3", ARM64MCExpr::VK_ABS_G3)
- .Case("abs_g2", ARM64MCExpr::VK_ABS_G2)
- .Case("abs_g2_s", ARM64MCExpr::VK_ABS_G2_S)
- .Case("abs_g2_nc", ARM64MCExpr::VK_ABS_G2_NC)
- .Case("abs_g1", ARM64MCExpr::VK_ABS_G1)
- .Case("abs_g1_s", ARM64MCExpr::VK_ABS_G1_S)
- .Case("abs_g1_nc", ARM64MCExpr::VK_ABS_G1_NC)
- .Case("abs_g0", ARM64MCExpr::VK_ABS_G0)
- .Case("abs_g0_s", ARM64MCExpr::VK_ABS_G0_S)
- .Case("abs_g0_nc", ARM64MCExpr::VK_ABS_G0_NC)
- .Case("dtprel_g2", ARM64MCExpr::VK_DTPREL_G2)
- .Case("dtprel_g1", ARM64MCExpr::VK_DTPREL_G1)
- .Case("dtprel_g1_nc", ARM64MCExpr::VK_DTPREL_G1_NC)
- .Case("dtprel_g0", ARM64MCExpr::VK_DTPREL_G0)
- .Case("dtprel_g0_nc", ARM64MCExpr::VK_DTPREL_G0_NC)
- .Case("dtprel_hi12", ARM64MCExpr::VK_DTPREL_HI12)
- .Case("dtprel_lo12", ARM64MCExpr::VK_DTPREL_LO12)
- .Case("dtprel_lo12_nc", ARM64MCExpr::VK_DTPREL_LO12_NC)
- .Case("tprel_g2", ARM64MCExpr::VK_TPREL_G2)
- .Case("tprel_g1", ARM64MCExpr::VK_TPREL_G1)
- .Case("tprel_g1_nc", ARM64MCExpr::VK_TPREL_G1_NC)
- .Case("tprel_g0", ARM64MCExpr::VK_TPREL_G0)
- .Case("tprel_g0_nc", ARM64MCExpr::VK_TPREL_G0_NC)
- .Case("tprel_hi12", ARM64MCExpr::VK_TPREL_HI12)
- .Case("tprel_lo12", ARM64MCExpr::VK_TPREL_LO12)
- .Case("tprel_lo12_nc", ARM64MCExpr::VK_TPREL_LO12_NC)
- .Case("tlsdesc_lo12", ARM64MCExpr::VK_TLSDESC_LO12)
- .Case("got", ARM64MCExpr::VK_GOT_PAGE)
- .Case("got_lo12", ARM64MCExpr::VK_GOT_LO12)
- .Case("gottprel", ARM64MCExpr::VK_GOTTPREL_PAGE)
- .Case("gottprel_lo12", ARM64MCExpr::VK_GOTTPREL_LO12_NC)
- .Case("gottprel_g1", ARM64MCExpr::VK_GOTTPREL_G1)
- .Case("gottprel_g0_nc", ARM64MCExpr::VK_GOTTPREL_G0_NC)
- .Case("tlsdesc", ARM64MCExpr::VK_TLSDESC_PAGE)
- .Default(ARM64MCExpr::VK_INVALID);
-
- if (RefKind == ARM64MCExpr::VK_INVALID) {
- Error(Parser.getTok().getLoc(),
- "expect relocation specifier in operand after ':'");
- return true;
- }
-
- Parser.Lex(); // Eat identifier
-
- if (Parser.getTok().isNot(AsmToken::Colon)) {
- Error(Parser.getTok().getLoc(), "expect ':' after relocation specifier");
- return true;
- }
- Parser.Lex(); // Eat ':'
- }
-
- if (getParser().parseExpression(ImmVal))
- return true;
-
- if (HasELFModifier)
- ImmVal = ARM64MCExpr::Create(ImmVal, RefKind, getContext());
-
- return false;
-}
-
-/// parseVectorList - Parse a vector list operand for AdvSIMD instructions.
-bool ARM64AsmParser::parseVectorList(OperandVector &Operands) {
- assert(Parser.getTok().is(AsmToken::LCurly) && "Token is not a Left Bracket");
- SMLoc S = getLoc();
- Parser.Lex(); // Eat left bracket token.
- StringRef Kind;
- int64_t FirstReg = tryMatchVectorRegister(Kind, true);
- if (FirstReg == -1)
- return true;
- int64_t PrevReg = FirstReg;
- unsigned Count = 1;
-
- if (Parser.getTok().is(AsmToken::Minus)) {
- Parser.Lex(); // Eat the minus.
-
- SMLoc Loc = getLoc();
- StringRef NextKind;
- int64_t Reg = tryMatchVectorRegister(NextKind, true);
- if (Reg == -1)
- return true;
- // Any Kind suffices must match on all regs in the list.
- if (Kind != NextKind)
- return Error(Loc, "mismatched register size suffix");
-
- unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg);
-
- if (Space == 0 || Space > 3) {
- return Error(Loc, "invalid number of vectors");
- }
-
- Count += Space;
- }
- else {
- while (Parser.getTok().is(AsmToken::Comma)) {
- Parser.Lex(); // Eat the comma token.
-
- SMLoc Loc = getLoc();
- StringRef NextKind;
- int64_t Reg = tryMatchVectorRegister(NextKind, true);
- if (Reg == -1)
- return true;
- // Any Kind suffices must match on all regs in the list.
- if (Kind != NextKind)
- return Error(Loc, "mismatched register size suffix");
-
- // Registers must be incremental (with wraparound at 31)
- if (getContext().getRegisterInfo()->getEncodingValue(Reg) !=
- (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32)
- return Error(Loc, "registers must be sequential");
-
- PrevReg = Reg;
- ++Count;
- }
- }
-
- if (Parser.getTok().isNot(AsmToken::RCurly))
- return Error(getLoc(), "'}' expected");
- Parser.Lex(); // Eat the '}' token.
-
- if (Count > 4)
- return Error(S, "invalid number of vectors");
-
- unsigned NumElements = 0;
- char ElementKind = 0;
- if (!Kind.empty())
- parseValidVectorKind(Kind, NumElements, ElementKind);
-
- Operands.push_back(ARM64Operand::CreateVectorList(
- FirstReg, Count, NumElements, ElementKind, S, getLoc(), getContext()));
-
- // If there is an index specifier following the list, parse that too.
- if (Parser.getTok().is(AsmToken::LBrac)) {
- SMLoc SIdx = getLoc();
- Parser.Lex(); // Eat left bracket token.
-
- const MCExpr *ImmVal;
- if (getParser().parseExpression(ImmVal))
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
- if (!MCE) {
- TokError("immediate value expected for vector index");
- return false;
- }
-
- SMLoc E = getLoc();
- if (Parser.getTok().isNot(AsmToken::RBrac)) {
- Error(E, "']' expected");
- return false;
- }
-
- Parser.Lex(); // Eat right bracket token.
-
- Operands.push_back(ARM64Operand::CreateVectorIndex(MCE->getValue(), SIdx, E,
- getContext()));
- }
- return false;
-}
-
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
- const AsmToken &Tok = Parser.getTok();
- if (!Tok.is(AsmToken::Identifier))
- return MatchOperand_NoMatch;
-
- unsigned RegNum = MatchRegisterName(Tok.getString().lower());
-
- MCContext &Ctx = getContext();
- const MCRegisterInfo *RI = Ctx.getRegisterInfo();
- if (!RI->getRegClass(ARM64::GPR64spRegClassID).contains(RegNum))
- return MatchOperand_NoMatch;
-
- SMLoc S = getLoc();
- Parser.Lex(); // Eat register
-
- if (Parser.getTok().isNot(AsmToken::Comma)) {
- Operands.push_back(ARM64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx));
- return MatchOperand_Success;
- }
- Parser.Lex(); // Eat comma.
-
- if (Parser.getTok().is(AsmToken::Hash))
- Parser.Lex(); // Eat hash
-
- if (Parser.getTok().isNot(AsmToken::Integer)) {
- Error(getLoc(), "index must be absent or #0");
- return MatchOperand_ParseFail;
- }
-
- const MCExpr *ImmVal;
- if (Parser.parseExpression(ImmVal) || !isa<MCConstantExpr>(ImmVal) ||
- cast<MCConstantExpr>(ImmVal)->getValue() != 0) {
- Error(getLoc(), "index must be absent or #0");
- return MatchOperand_ParseFail;
- }
-
- Operands.push_back(ARM64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx));
- return MatchOperand_Success;
-}
-
-/// parseOperand - Parse a arm instruction operand. For now this parses the
-/// operand regardless of the mnemonic.
-bool ARM64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
- bool invertCondCode) {
- // Check if the current operand has a custom associated parser, if so, try to
- // custom parse the operand, or fallback to the general approach.
- OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
- if (ResTy == MatchOperand_Success)
- return false;
- // If there wasn't a custom match, try the generic matcher below. Otherwise,
- // there was a match, but an error occurred, in which case, just return that
- // the operand parsing failed.
- if (ResTy == MatchOperand_ParseFail)
- return true;
-
- // Nothing custom, so do general case parsing.
- SMLoc S, E;
- switch (getLexer().getKind()) {
- default: {
- SMLoc S = getLoc();
- const MCExpr *Expr;
- if (parseSymbolicImmVal(Expr))
- return Error(S, "invalid operand");
-
- SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
- Operands.push_back(ARM64Operand::CreateImm(Expr, S, E, getContext()));
- return false;
- }
- case AsmToken::LBrac: {
- SMLoc Loc = Parser.getTok().getLoc();
- Operands.push_back(ARM64Operand::CreateToken("[", false, Loc,
- getContext()));
- Parser.Lex(); // Eat '['
-
- // There's no comma after a '[', so we can parse the next operand
- // immediately.
- return parseOperand(Operands, false, false);
- }
- case AsmToken::LCurly:
- return parseVectorList(Operands);
- case AsmToken::Identifier: {
- // If we're expecting a Condition Code operand, then just parse that.
- if (isCondCode)
- return parseCondCode(Operands, invertCondCode);
-
- // If it's a register name, parse it.
- if (!parseRegister(Operands))
- return false;
-
- // This could be an optional "shift" or "extend" operand.
- OperandMatchResultTy GotShift = tryParseOptionalShiftExtend(Operands);
- // We can only continue if no tokens were eaten.
- if (GotShift != MatchOperand_NoMatch)
- return GotShift;
-
- // This was not a register so parse other operands that start with an
- // identifier (like labels) as expressions and create them as immediates.
- const MCExpr *IdVal;
- S = getLoc();
- if (getParser().parseExpression(IdVal))
- return true;
-
- E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
- Operands.push_back(ARM64Operand::CreateImm(IdVal, S, E, getContext()));
- return false;
- }
- case AsmToken::Integer:
- case AsmToken::Real:
- case AsmToken::Hash: {
- // #42 -> immediate.
- S = getLoc();
- if (getLexer().is(AsmToken::Hash))
- Parser.Lex();
-
- // Parse a negative sign
- bool isNegative = false;
- if (Parser.getTok().is(AsmToken::Minus)) {
- isNegative = true;
- // We need to consume this token only when we have a Real, otherwise
- // we let parseSymbolicImmVal take care of it
- if (Parser.getLexer().peekTok().is(AsmToken::Real))
- Parser.Lex();
- }
-
- // The only Real that should come through here is a literal #0.0 for
- // the fcmp[e] r, #0.0 instructions. They expect raw token operands,
- // so convert the value.
- const AsmToken &Tok = Parser.getTok();
- if (Tok.is(AsmToken::Real)) {
- APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
- uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
- if (Mnemonic != "fcmp" && Mnemonic != "fcmpe" && Mnemonic != "fcmeq" &&
- Mnemonic != "fcmge" && Mnemonic != "fcmgt" && Mnemonic != "fcmle" &&
- Mnemonic != "fcmlt")
- return TokError("unexpected floating point literal");
- else if (IntVal != 0 || isNegative)
- return TokError("expected floating-point constant #0.0");
- Parser.Lex(); // Eat the token.
-
- Operands.push_back(
- ARM64Operand::CreateToken("#0", false, S, getContext()));
- Operands.push_back(
- ARM64Operand::CreateToken(".0", false, S, getContext()));
- return false;
- }
-
- const MCExpr *ImmVal;
- if (parseSymbolicImmVal(ImmVal))
- return true;
-
- E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
- Operands.push_back(ARM64Operand::CreateImm(ImmVal, S, E, getContext()));
- return false;
- }
- }
-}
-
-/// ParseInstruction - Parse an ARM64 instruction mnemonic followed by its
-/// operands.
-bool ARM64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
- StringRef Name, SMLoc NameLoc,
- OperandVector &Operands) {
- Name = StringSwitch<StringRef>(Name.lower())
- .Case("beq", "b.eq")
- .Case("bne", "b.ne")
- .Case("bhs", "b.hs")
- .Case("bcs", "b.cs")
- .Case("blo", "b.lo")
- .Case("bcc", "b.cc")
- .Case("bmi", "b.mi")
- .Case("bpl", "b.pl")
- .Case("bvs", "b.vs")
- .Case("bvc", "b.vc")
- .Case("bhi", "b.hi")
- .Case("bls", "b.ls")
- .Case("bge", "b.ge")
- .Case("blt", "b.lt")
- .Case("bgt", "b.gt")
- .Case("ble", "b.le")
- .Case("bal", "b.al")
- .Case("bnv", "b.nv")
- .Default(Name);
-
- // Create the leading tokens for the mnemonic, split by '.' characters.
- size_t Start = 0, Next = Name.find('.');
- StringRef Head = Name.slice(Start, Next);
-
- // IC, DC, AT, and TLBI instructions are aliases for the SYS instruction.
- if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi") {
- bool IsError = parseSysAlias(Head, NameLoc, Operands);
- if (IsError && getLexer().isNot(AsmToken::EndOfStatement))
- Parser.eatToEndOfStatement();
- return IsError;
- }
-
- Operands.push_back(
- ARM64Operand::CreateToken(Head, false, NameLoc, getContext()));
- Mnemonic = Head;
-
- // Handle condition codes for a branch mnemonic
- if (Head == "b" && Next != StringRef::npos) {
- Start = Next;
- Next = Name.find('.', Start + 1);
- Head = Name.slice(Start + 1, Next);
-
- SMLoc SuffixLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
- (Head.data() - Name.data()));
- ARM64CC::CondCode CC = parseCondCodeString(Head);
- if (CC == ARM64CC::Invalid)
- return Error(SuffixLoc, "invalid condition code");
- Operands.push_back(
- ARM64Operand::CreateToken(".", true, SuffixLoc, getContext()));
- Operands.push_back(
- ARM64Operand::CreateCondCode(CC, NameLoc, NameLoc, getContext()));
- }
-
- // Add the remaining tokens in the mnemonic.
- while (Next != StringRef::npos) {
- Start = Next;
- Next = Name.find('.', Start + 1);
- Head = Name.slice(Start, Next);
- SMLoc SuffixLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
- (Head.data() - Name.data()) + 1);
- Operands.push_back(
- ARM64Operand::CreateToken(Head, true, SuffixLoc, getContext()));
- }
-
- // Conditional compare instructions have a Condition Code operand, which needs
- // to be parsed and an immediate operand created.
- bool condCodeFourthOperand =
- (Head == "ccmp" || Head == "ccmn" || Head == "fccmp" ||
- Head == "fccmpe" || Head == "fcsel" || Head == "csel" ||
- Head == "csinc" || Head == "csinv" || Head == "csneg");
-
- // These instructions are aliases to some of the conditional select
- // instructions. However, the condition code is inverted in the aliased
- // instruction.
- //
- // FIXME: Is this the correct way to handle these? Or should the parser
- // generate the aliased instructions directly?
- bool condCodeSecondOperand = (Head == "cset" || Head == "csetm");
- bool condCodeThirdOperand =
- (Head == "cinc" || Head == "cinv" || Head == "cneg");
-
- // Read the remaining operands.
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- // Read the first operand.
- if (parseOperand(Operands, false, false)) {
- Parser.eatToEndOfStatement();
- return true;
- }
-
- unsigned N = 2;
- while (getLexer().is(AsmToken::Comma)) {
- Parser.Lex(); // Eat the comma.
-
- // Parse and remember the operand.
- if (parseOperand(Operands, (N == 4 && condCodeFourthOperand) ||
- (N == 3 && condCodeThirdOperand) ||
- (N == 2 && condCodeSecondOperand),
- condCodeSecondOperand || condCodeThirdOperand)) {
- Parser.eatToEndOfStatement();
- return true;
- }
-
- // After successfully parsing some operands there are two special cases to
- // consider (i.e. notional operands not separated by commas). Both are due
- // to memory specifiers:
- // + An RBrac will end an address for load/store/prefetch
- // + An '!' will indicate a pre-indexed operation.
- //
- // It's someone else's responsibility to make sure these tokens are sane
- // in the given context!
- if (Parser.getTok().is(AsmToken::RBrac)) {
- SMLoc Loc = Parser.getTok().getLoc();
- Operands.push_back(ARM64Operand::CreateToken("]", false, Loc,
- getContext()));
- Parser.Lex();
- }
-
- if (Parser.getTok().is(AsmToken::Exclaim)) {
- SMLoc Loc = Parser.getTok().getLoc();
- Operands.push_back(ARM64Operand::CreateToken("!", false, Loc,
- getContext()));
- Parser.Lex();
- }
-
- ++N;
- }
- }
-
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- SMLoc Loc = Parser.getTok().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, "unexpected token in argument list");
- }
-
- Parser.Lex(); // Consume the EndOfStatement
- return false;
-}
-
-// FIXME: This entire function is a giant hack to provide us with decent
-// operand range validation/diagnostics until TableGen/MC can be extended
-// to support autogeneration of this kind of validation.
-bool ARM64AsmParser::validateInstruction(MCInst &Inst,
- SmallVectorImpl<SMLoc> &Loc) {
- const MCRegisterInfo *RI = getContext().getRegisterInfo();
- // Check for indexed addressing modes w/ the base register being the
- // same as a destination/source register or pair load where
- // the Rt == Rt2. All of those are undefined behaviour.
- switch (Inst.getOpcode()) {
- case ARM64::LDPSWpre:
- case ARM64::LDPWpost:
- case ARM64::LDPWpre:
- case ARM64::LDPXpost:
- case ARM64::LDPXpre: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rt2 = Inst.getOperand(2).getReg();
- unsigned Rn = Inst.getOperand(3).getReg();
- if (RI->isSubRegisterEq(Rn, Rt))
- return Error(Loc[0], "unpredictable LDP instruction, writeback base "
- "is also a destination");
- if (RI->isSubRegisterEq(Rn, Rt2))
- return Error(Loc[1], "unpredictable LDP instruction, writeback base "
- "is also a destination");
- // FALLTHROUGH
- }
- case ARM64::LDPDi:
- case ARM64::LDPQi:
- case ARM64::LDPSi:
- case ARM64::LDPSWi:
- case ARM64::LDPWi:
- case ARM64::LDPXi: {
- unsigned Rt = Inst.getOperand(0).getReg();
- unsigned Rt2 = Inst.getOperand(1).getReg();
- if (Rt == Rt2)
- return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
- break;
- }
- case ARM64::LDPDpost:
- case ARM64::LDPDpre:
- case ARM64::LDPQpost:
- case ARM64::LDPQpre:
- case ARM64::LDPSpost:
- case ARM64::LDPSpre:
- case ARM64::LDPSWpost: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rt2 = Inst.getOperand(2).getReg();
- if (Rt == Rt2)
- return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
- break;
- }
- case ARM64::STPDpost:
- case ARM64::STPDpre:
- case ARM64::STPQpost:
- case ARM64::STPQpre:
- case ARM64::STPSpost:
- case ARM64::STPSpre:
- case ARM64::STPWpost:
- case ARM64::STPWpre:
- case ARM64::STPXpost:
- case ARM64::STPXpre: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rt2 = Inst.getOperand(2).getReg();
- unsigned Rn = Inst.getOperand(3).getReg();
- if (RI->isSubRegisterEq(Rn, Rt))
- return Error(Loc[0], "unpredictable STP instruction, writeback base "
- "is also a source");
- if (RI->isSubRegisterEq(Rn, Rt2))
- return Error(Loc[1], "unpredictable STP instruction, writeback base "
- "is also a source");
- break;
- }
- case ARM64::LDRBBpre:
- case ARM64::LDRBpre:
- case ARM64::LDRHHpre:
- case ARM64::LDRHpre:
- case ARM64::LDRSBWpre:
- case ARM64::LDRSBXpre:
- case ARM64::LDRSHWpre:
- case ARM64::LDRSHXpre:
- case ARM64::LDRSWpre:
- case ARM64::LDRWpre:
- case ARM64::LDRXpre:
- case ARM64::LDRBBpost:
- case ARM64::LDRBpost:
- case ARM64::LDRHHpost:
- case ARM64::LDRHpost:
- case ARM64::LDRSBWpost:
- case ARM64::LDRSBXpost:
- case ARM64::LDRSHWpost:
- case ARM64::LDRSHXpost:
- case ARM64::LDRSWpost:
- case ARM64::LDRWpost:
- case ARM64::LDRXpost: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rn = Inst.getOperand(2).getReg();
- if (RI->isSubRegisterEq(Rn, Rt))
- return Error(Loc[0], "unpredictable LDR instruction, writeback base "
- "is also a source");
- break;
- }
- case ARM64::STRBBpost:
- case ARM64::STRBpost:
- case ARM64::STRHHpost:
- case ARM64::STRHpost:
- case ARM64::STRWpost:
- case ARM64::STRXpost:
- case ARM64::STRBBpre:
- case ARM64::STRBpre:
- case ARM64::STRHHpre:
- case ARM64::STRHpre:
- case ARM64::STRWpre:
- case ARM64::STRXpre: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rn = Inst.getOperand(2).getReg();
- if (RI->isSubRegisterEq(Rn, Rt))
- return Error(Loc[0], "unpredictable STR instruction, writeback base "
- "is also a source");
- break;
- }
- }
-
- // Now check immediate ranges. Separate from the above as there is overlap
- // in the instructions being checked and this keeps the nested conditionals
- // to a minimum.
- switch (Inst.getOpcode()) {
- case ARM64::ADDSWri:
- case ARM64::ADDSXri:
- case ARM64::ADDWri:
- case ARM64::ADDXri:
- case ARM64::SUBSWri:
- case ARM64::SUBSXri:
- case ARM64::SUBWri:
- case ARM64::SUBXri: {
- // Annoyingly we can't do this in the isAddSubImm predicate, so there is
- // some slight duplication here.
- if (Inst.getOperand(2).isExpr()) {
- const MCExpr *Expr = Inst.getOperand(2).getExpr();
- ARM64MCExpr::VariantKind ELFRefKind;
- MCSymbolRefExpr::VariantKind DarwinRefKind;
- int64_t Addend;
- if (!classifySymbolRef(Expr, ELFRefKind, DarwinRefKind, Addend)) {
- return Error(Loc[2], "invalid immediate expression");
- }
-
- // Only allow these with ADDXri.
- if ((DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF ||
- DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF) &&
- Inst.getOpcode() == ARM64::ADDXri)
- return false;
-
- // Only allow these with ADDXri/ADDWri
- if ((ELFRefKind == ARM64MCExpr::VK_LO12 ||
- ELFRefKind == ARM64MCExpr::VK_DTPREL_HI12 ||
- ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12 ||
- ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12_NC ||
- ELFRefKind == ARM64MCExpr::VK_TPREL_HI12 ||
- ELFRefKind == ARM64MCExpr::VK_TPREL_LO12 ||
- ELFRefKind == ARM64MCExpr::VK_TPREL_LO12_NC ||
- ELFRefKind == ARM64MCExpr::VK_TLSDESC_LO12) &&
- (Inst.getOpcode() == ARM64::ADDXri ||
- Inst.getOpcode() == ARM64::ADDWri))
- return false;
-
- // Don't allow expressions in the immediate field otherwise
- return Error(Loc[2], "invalid immediate expression");
- }
- return false;
- }
- default:
- return false;
- }
-}
-
-bool ARM64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) {
- switch (ErrCode) {
- case Match_MissingFeature:
- return Error(Loc,
- "instruction requires a CPU feature not currently enabled");
- case Match_InvalidOperand:
- return Error(Loc, "invalid operand for instruction");
- case Match_InvalidSuffix:
- return Error(Loc, "invalid type suffix for instruction");
- case Match_InvalidCondCode:
- return Error(Loc, "expected AArch64 condition code");
- case Match_AddSubRegExtendSmall:
- return Error(Loc,
- "expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]");
- case Match_AddSubRegExtendLarge:
- return Error(Loc,
- "expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]");
- case Match_AddSubSecondSource:
- return Error(Loc,
- "expected compatible register, symbol or integer in range [0, 4095]");
- case Match_LogicalSecondSource:
- return Error(Loc, "expected compatible register or logical immediate");
- case Match_InvalidMovImm32Shift:
- return Error(Loc, "expected 'lsl' with optional integer 0 or 16");
- case Match_InvalidMovImm64Shift:
- return Error(Loc, "expected 'lsl' with optional integer 0, 16, 32 or 48");
- case Match_AddSubRegShift32:
- return Error(Loc,
- "expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]");
- case Match_AddSubRegShift64:
- return Error(Loc,
- "expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 63]");
- case Match_InvalidFPImm:
- return Error(Loc,
- "expected compatible register or floating-point constant");
- case Match_InvalidMemoryIndexedSImm9:
- return Error(Loc, "index must be an integer in range [-256, 255].");
- case Match_InvalidMemoryIndexed4SImm7:
- return Error(Loc, "index must be a multiple of 4 in range [-256, 252].");
- case Match_InvalidMemoryIndexed8SImm7:
- return Error(Loc, "index must be a multiple of 8 in range [-512, 504].");
- case Match_InvalidMemoryIndexed16SImm7:
- return Error(Loc, "index must be a multiple of 16 in range [-1024, 1008].");
- case Match_InvalidMemoryWExtend8:
- return Error(Loc,
- "expected 'uxtw' or 'sxtw' with optional shift of #0");
- case Match_InvalidMemoryWExtend16:
- return Error(Loc,
- "expected 'uxtw' or 'sxtw' with optional shift of #0 or #1");
- case Match_InvalidMemoryWExtend32:
- return Error(Loc,
- "expected 'uxtw' or 'sxtw' with optional shift of #0 or #2");
- case Match_InvalidMemoryWExtend64:
- return Error(Loc,
- "expected 'uxtw' or 'sxtw' with optional shift of #0 or #3");
- case Match_InvalidMemoryWExtend128:
- return Error(Loc,
- "expected 'uxtw' or 'sxtw' with optional shift of #0 or #4");
- case Match_InvalidMemoryXExtend8:
- return Error(Loc,
- "expected 'lsl' or 'sxtx' with optional shift of #0");
- case Match_InvalidMemoryXExtend16:
- return Error(Loc,
- "expected 'lsl' or 'sxtx' with optional shift of #0 or #1");
- case Match_InvalidMemoryXExtend32:
- return Error(Loc,
- "expected 'lsl' or 'sxtx' with optional shift of #0 or #2");
- case Match_InvalidMemoryXExtend64:
- return Error(Loc,
- "expected 'lsl' or 'sxtx' with optional shift of #0 or #3");
- case Match_InvalidMemoryXExtend128:
- return Error(Loc,
- "expected 'lsl' or 'sxtx' with optional shift of #0 or #4");
- case Match_InvalidMemoryIndexed1:
- return Error(Loc, "index must be an integer in range [0, 4095].");
- case Match_InvalidMemoryIndexed2:
- return Error(Loc, "index must be a multiple of 2 in range [0, 8190].");
- case Match_InvalidMemoryIndexed4:
- return Error(Loc, "index must be a multiple of 4 in range [0, 16380].");
- case Match_InvalidMemoryIndexed8:
- return Error(Loc, "index must be a multiple of 8 in range [0, 32760].");
- case Match_InvalidMemoryIndexed16:
- return Error(Loc, "index must be a multiple of 16 in range [0, 65520].");
- case Match_InvalidImm0_7:
- return Error(Loc, "immediate must be an integer in range [0, 7].");
- case Match_InvalidImm0_15:
- return Error(Loc, "immediate must be an integer in range [0, 15].");
- case Match_InvalidImm0_31:
- return Error(Loc, "immediate must be an integer in range [0, 31].");
- case Match_InvalidImm0_63:
- return Error(Loc, "immediate must be an integer in range [0, 63].");
- case Match_InvalidImm0_127:
- return Error(Loc, "immediate must be an integer in range [0, 127].");
- case Match_InvalidImm0_65535:
- return Error(Loc, "immediate must be an integer in range [0, 65535].");
- case Match_InvalidImm1_8:
- return Error(Loc, "immediate must be an integer in range [1, 8].");
- case Match_InvalidImm1_16:
- return Error(Loc, "immediate must be an integer in range [1, 16].");
- case Match_InvalidImm1_32:
- return Error(Loc, "immediate must be an integer in range [1, 32].");
- case Match_InvalidImm1_64:
- return Error(Loc, "immediate must be an integer in range [1, 64].");
- case Match_InvalidIndex1:
- return Error(Loc, "expected lane specifier '[1]'");
- case Match_InvalidIndexB:
- return Error(Loc, "vector lane must be an integer in range [0, 15].");
- case Match_InvalidIndexH:
- return Error(Loc, "vector lane must be an integer in range [0, 7].");
- case Match_InvalidIndexS:
- return Error(Loc, "vector lane must be an integer in range [0, 3].");
- case Match_InvalidIndexD:
- return Error(Loc, "vector lane must be an integer in range [0, 1].");
- case Match_InvalidLabel:
- return Error(Loc, "expected label or encodable integer pc offset");
- case Match_MRS:
- return Error(Loc, "expected readable system register");
- case Match_MSR:
- return Error(Loc, "expected writable system register or pstate");
- case Match_MnemonicFail:
- return Error(Loc, "unrecognized instruction mnemonic");
- default:
- assert(0 && "unexpected error code!");
- return Error(Loc, "invalid instruction format");
- }
-}
-
-static const char *getSubtargetFeatureName(unsigned Val);
-
-bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
- OperandVector &Operands,
- MCStreamer &Out,
- unsigned &ErrorInfo,
- bool MatchingInlineAsm) {
- assert(!Operands.empty() && "Unexpect empty operand list!");
- ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[0]);
- assert(Op->isToken() && "Leading operand should always be a mnemonic!");
-
- StringRef Tok = Op->getToken();
- unsigned NumOperands = Operands.size();
-
- if (NumOperands == 4 && Tok == "lsl") {
- ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
- ARM64Operand *Op3 = static_cast<ARM64Operand *>(Operands[3]);
- if (Op2->isReg() && Op3->isImm()) {
- const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3->getImm());
- if (Op3CE) {
- uint64_t Op3Val = Op3CE->getValue();
- uint64_t NewOp3Val = 0;
- uint64_t NewOp4Val = 0;
- if (ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(
- Op2->getReg())) {
- NewOp3Val = (32 - Op3Val) & 0x1f;
- NewOp4Val = 31 - Op3Val;
- } else {
- NewOp3Val = (64 - Op3Val) & 0x3f;
- NewOp4Val = 63 - Op3Val;
- }
-
- const MCExpr *NewOp3 = MCConstantExpr::Create(NewOp3Val, getContext());
- const MCExpr *NewOp4 = MCConstantExpr::Create(NewOp4Val, getContext());
-
- Operands[0] = ARM64Operand::CreateToken(
- "ubfm", false, Op->getStartLoc(), getContext());
- Operands[3] = ARM64Operand::CreateImm(NewOp3, Op3->getStartLoc(),
- Op3->getEndLoc(), getContext());
- Operands.push_back(ARM64Operand::CreateImm(
- NewOp4, Op3->getStartLoc(), Op3->getEndLoc(), getContext()));
- delete Op3;
- delete Op;
- }
- }
- } else if (NumOperands == 5) {
- // FIXME: Horrible hack to handle the BFI -> BFM, SBFIZ->SBFM, and
- // UBFIZ -> UBFM aliases.
- if (Tok == "bfi" || Tok == "sbfiz" || Tok == "ubfiz") {
- ARM64Operand *Op1 = static_cast<ARM64Operand *>(Operands[1]);
- ARM64Operand *Op3 = static_cast<ARM64Operand *>(Operands[3]);
- ARM64Operand *Op4 = static_cast<ARM64Operand *>(Operands[4]);
-
- if (Op1->isReg() && Op3->isImm() && Op4->isImm()) {
- const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3->getImm());
- const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4->getImm());
-
- if (Op3CE && Op4CE) {
- uint64_t Op3Val = Op3CE->getValue();
- uint64_t Op4Val = Op4CE->getValue();
-
- uint64_t RegWidth = 0;
- if (ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
- Op1->getReg()))
- RegWidth = 64;
- else
- RegWidth = 32;
-
- if (Op3Val >= RegWidth)
- return Error(Op3->getStartLoc(),
- "expected integer in range [0, 31]");
- if (Op4Val < 1 || Op4Val > RegWidth)
- return Error(Op4->getStartLoc(),
- "expected integer in range [1, 32]");
-
- uint64_t NewOp3Val = 0;
- if (ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(
- Op1->getReg()))
- NewOp3Val = (32 - Op3Val) & 0x1f;
- else
- NewOp3Val = (64 - Op3Val) & 0x3f;
-
- uint64_t NewOp4Val = Op4Val - 1;
-
- if (NewOp3Val != 0 && NewOp4Val >= NewOp3Val)
- return Error(Op4->getStartLoc(),
- "requested insert overflows register");
-
- const MCExpr *NewOp3 =
- MCConstantExpr::Create(NewOp3Val, getContext());
- const MCExpr *NewOp4 =
- MCConstantExpr::Create(NewOp4Val, getContext());
- Operands[3] = ARM64Operand::CreateImm(NewOp3, Op3->getStartLoc(),
- Op3->getEndLoc(), getContext());
- Operands[4] = ARM64Operand::CreateImm(NewOp4, Op4->getStartLoc(),
- Op4->getEndLoc(), getContext());
- if (Tok == "bfi")
- Operands[0] = ARM64Operand::CreateToken(
- "bfm", false, Op->getStartLoc(), getContext());
- else if (Tok == "sbfiz")
- Operands[0] = ARM64Operand::CreateToken(
- "sbfm", false, Op->getStartLoc(), getContext());
- else if (Tok == "ubfiz")
- Operands[0] = ARM64Operand::CreateToken(
- "ubfm", false, Op->getStartLoc(), getContext());
- else
- llvm_unreachable("No valid mnemonic for alias?");
-
- delete Op;
- delete Op3;
- delete Op4;
- }
- }
-
- // FIXME: Horrible hack to handle the BFXIL->BFM, SBFX->SBFM, and
- // UBFX -> UBFM aliases.
- } else if (NumOperands == 5 &&
- (Tok == "bfxil" || Tok == "sbfx" || Tok == "ubfx")) {
- ARM64Operand *Op1 = static_cast<ARM64Operand *>(Operands[1]);
- ARM64Operand *Op3 = static_cast<ARM64Operand *>(Operands[3]);
- ARM64Operand *Op4 = static_cast<ARM64Operand *>(Operands[4]);
-
- if (Op1->isReg() && Op3->isImm() && Op4->isImm()) {
- const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3->getImm());
- const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4->getImm());
-
- if (Op3CE && Op4CE) {
- uint64_t Op3Val = Op3CE->getValue();
- uint64_t Op4Val = Op4CE->getValue();
-
- uint64_t RegWidth = 0;
- if (ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
- Op1->getReg()))
- RegWidth = 64;
- else
- RegWidth = 32;
-
- if (Op3Val >= RegWidth)
- return Error(Op3->getStartLoc(),
- "expected integer in range [0, 31]");
- if (Op4Val < 1 || Op4Val > RegWidth)
- return Error(Op4->getStartLoc(),
- "expected integer in range [1, 32]");
-
- uint64_t NewOp4Val = Op3Val + Op4Val - 1;
-
- if (NewOp4Val >= RegWidth || NewOp4Val < Op3Val)
- return Error(Op4->getStartLoc(),
- "requested extract overflows register");
-
- const MCExpr *NewOp4 =
- MCConstantExpr::Create(NewOp4Val, getContext());
- Operands[4] = ARM64Operand::CreateImm(
- NewOp4, Op4->getStartLoc(), Op4->getEndLoc(), getContext());
- if (Tok == "bfxil")
- Operands[0] = ARM64Operand::CreateToken(
- "bfm", false, Op->getStartLoc(), getContext());
- else if (Tok == "sbfx")
- Operands[0] = ARM64Operand::CreateToken(
- "sbfm", false, Op->getStartLoc(), getContext());
- else if (Tok == "ubfx")
- Operands[0] = ARM64Operand::CreateToken(
- "ubfm", false, Op->getStartLoc(), getContext());
- else
- llvm_unreachable("No valid mnemonic for alias?");
-
- delete Op;
- delete Op4;
- }
- }
- }
- }
- // FIXME: Horrible hack for sxtw and uxtw with Wn src and Xd dst operands.
- // InstAlias can't quite handle this since the reg classes aren't
- // subclasses.
- if (NumOperands == 3 && (Tok == "sxtw" || Tok == "uxtw")) {
- // The source register can be Wn here, but the matcher expects a
- // GPR64. Twiddle it here if necessary.
- ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[2]);
- if (Op->isReg()) {
- unsigned Reg = getXRegFromWReg(Op->getReg());
- Operands[2] = ARM64Operand::CreateReg(Reg, false, Op->getStartLoc(),
- Op->getEndLoc(), getContext());
- delete Op;
- }
- }
- // FIXME: Likewise for sxt[bh] with a Xd dst operand
- else if (NumOperands == 3 && (Tok == "sxtb" || Tok == "sxth")) {
- ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
- if (Op->isReg() &&
- ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
- Op->getReg())) {
- // The source register can be Wn here, but the matcher expects a
- // GPR64. Twiddle it here if necessary.
- ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[2]);
- if (Op->isReg()) {
- unsigned Reg = getXRegFromWReg(Op->getReg());
- Operands[2] = ARM64Operand::CreateReg(Reg, false, Op->getStartLoc(),
- Op->getEndLoc(), getContext());
- delete Op;
- }
- }
- }
- // FIXME: Likewise for uxt[bh] with a Xd dst operand
- else if (NumOperands == 3 && (Tok == "uxtb" || Tok == "uxth")) {
- ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
- if (Op->isReg() &&
- ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
- Op->getReg())) {
- // The source register can be Wn here, but the matcher expects a
- // GPR32. Twiddle it here if necessary.
- ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
- if (Op->isReg()) {
- unsigned Reg = getWRegFromXReg(Op->getReg());
- Operands[1] = ARM64Operand::CreateReg(Reg, false, Op->getStartLoc(),
- Op->getEndLoc(), getContext());
- delete Op;
- }
- }
- }
-
- // Yet another horrible hack to handle FMOV Rd, #0.0 using [WX]ZR.
- if (NumOperands == 3 && Tok == "fmov") {
- ARM64Operand *RegOp = static_cast<ARM64Operand *>(Operands[1]);
- ARM64Operand *ImmOp = static_cast<ARM64Operand *>(Operands[2]);
- if (RegOp->isReg() && ImmOp->isFPImm() &&
- ImmOp->getFPImm() == (unsigned)-1) {
- unsigned zreg = ARM64MCRegisterClasses[ARM64::FPR32RegClassID].contains(
- RegOp->getReg())
- ? ARM64::WZR
- : ARM64::XZR;
- Operands[2] = ARM64Operand::CreateReg(zreg, false, Op->getStartLoc(),
- Op->getEndLoc(), getContext());
- delete ImmOp;
- }
- }
-
- MCInst Inst;
- // First try to match against the secondary set of tables containing the
- // short-form NEON instructions (e.g. "fadd.2s v0, v1, v2").
- unsigned MatchResult =
- MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm, 1);
-
- // If that fails, try against the alternate table containing long-form NEON:
- // "fadd v0.2s, v1.2s, v2.2s"
- if (MatchResult != Match_Success)
- MatchResult =
- MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm, 0);
-
- switch (MatchResult) {
- case Match_Success: {
- // Perform range checking and other semantic validations
- SmallVector<SMLoc, 8> OperandLocs;
- NumOperands = Operands.size();
- for (unsigned i = 1; i < NumOperands; ++i)
- OperandLocs.push_back(Operands[i]->getStartLoc());
- if (validateInstruction(Inst, OperandLocs))
- return true;
-
- Inst.setLoc(IDLoc);
- Out.EmitInstruction(Inst, STI);
- return false;
- }
- case Match_MissingFeature: {
- assert(ErrorInfo && "Unknown missing feature!");
- // Special case the error message for the very common case where only
- // a single subtarget feature is missing (neon, e.g.).
- std::string Msg = "instruction requires:";
- unsigned Mask = 1;
- for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
- if (ErrorInfo & Mask) {
- Msg += " ";
- Msg += getSubtargetFeatureName(ErrorInfo & Mask);
- }
- Mask <<= 1;
- }
- return Error(IDLoc, Msg);
- }
- case Match_MnemonicFail:
- return showMatchError(IDLoc, MatchResult);
- case Match_InvalidOperand: {
- SMLoc ErrorLoc = IDLoc;
- if (ErrorInfo != ~0U) {
- if (ErrorInfo >= Operands.size())
- return Error(IDLoc, "too few operands for instruction");
-
- ErrorLoc = ((ARM64Operand *)Operands[ErrorInfo])->getStartLoc();
- if (ErrorLoc == SMLoc())
- ErrorLoc = IDLoc;
- }
- // If the match failed on a suffix token operand, tweak the diagnostic
- // accordingly.
- if (((ARM64Operand *)Operands[ErrorInfo])->isToken() &&
- ((ARM64Operand *)Operands[ErrorInfo])->isTokenSuffix())
- MatchResult = Match_InvalidSuffix;
-
- return showMatchError(ErrorLoc, MatchResult);
- }
- case Match_InvalidMemoryIndexed1:
- case Match_InvalidMemoryIndexed2:
- case Match_InvalidMemoryIndexed4:
- case Match_InvalidMemoryIndexed8:
- case Match_InvalidMemoryIndexed16:
- case Match_InvalidCondCode:
- case Match_AddSubRegExtendSmall:
- case Match_AddSubRegExtendLarge:
- case Match_AddSubSecondSource:
- case Match_LogicalSecondSource:
- case Match_AddSubRegShift32:
- case Match_AddSubRegShift64:
- case Match_InvalidMovImm32Shift:
- case Match_InvalidMovImm64Shift:
- case Match_InvalidFPImm:
- case Match_InvalidMemoryWExtend8:
- case Match_InvalidMemoryWExtend16:
- case Match_InvalidMemoryWExtend32:
- case Match_InvalidMemoryWExtend64:
- case Match_InvalidMemoryWExtend128:
- case Match_InvalidMemoryXExtend8:
- case Match_InvalidMemoryXExtend16:
- case Match_InvalidMemoryXExtend32:
- case Match_InvalidMemoryXExtend64:
- case Match_InvalidMemoryXExtend128:
- case Match_InvalidMemoryIndexed4SImm7:
- case Match_InvalidMemoryIndexed8SImm7:
- case Match_InvalidMemoryIndexed16SImm7:
- case Match_InvalidMemoryIndexedSImm9:
- case Match_InvalidImm0_7:
- case Match_InvalidImm0_15:
- case Match_InvalidImm0_31:
- case Match_InvalidImm0_63:
- case Match_InvalidImm0_127:
- case Match_InvalidImm0_65535:
- case Match_InvalidImm1_8:
- case Match_InvalidImm1_16:
- case Match_InvalidImm1_32:
- case Match_InvalidImm1_64:
- case Match_InvalidIndex1:
- case Match_InvalidIndexB:
- case Match_InvalidIndexH:
- case Match_InvalidIndexS:
- case Match_InvalidIndexD:
- case Match_InvalidLabel:
- case Match_MSR:
- case Match_MRS: {
- // Any time we get here, there's nothing fancy to do. Just get the
- // operand SMLoc and display the diagnostic.
- SMLoc ErrorLoc = ((ARM64Operand *)Operands[ErrorInfo])->getStartLoc();
- if (ErrorLoc == SMLoc())
- ErrorLoc = IDLoc;
- return showMatchError(ErrorLoc, MatchResult);
- }
- }
-
- llvm_unreachable("Implement any new match types added!");
- return true;
-}
-
-/// ParseDirective parses the arm specific directives
-bool ARM64AsmParser::ParseDirective(AsmToken DirectiveID) {
- StringRef IDVal = DirectiveID.getIdentifier();
- SMLoc Loc = DirectiveID.getLoc();
- if (IDVal == ".hword")
- return parseDirectiveWord(2, Loc);
- if (IDVal == ".word")
- return parseDirectiveWord(4, Loc);
- if (IDVal == ".xword")
- return parseDirectiveWord(8, Loc);
- if (IDVal == ".tlsdesccall")
- return parseDirectiveTLSDescCall(Loc);
-
- return parseDirectiveLOH(IDVal, Loc);
-}
-
-/// parseDirectiveWord
-/// ::= .word [ expression (, expression)* ]
-bool ARM64AsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- for (;;) {
- const MCExpr *Value;
- if (getParser().parseExpression(Value))
- return true;
-
- getParser().getStreamer().EmitValue(Value, Size);
-
- if (getLexer().is(AsmToken::EndOfStatement))
- break;
-
- // FIXME: Improve diagnostic.
- if (getLexer().isNot(AsmToken::Comma))
- return Error(L, "unexpected token in directive");
- Parser.Lex();
- }
- }
-
- Parser.Lex();
- return false;
-}
-
-// parseDirectiveTLSDescCall:
-// ::= .tlsdesccall symbol
-bool ARM64AsmParser::parseDirectiveTLSDescCall(SMLoc L) {
- StringRef Name;
- if (getParser().parseIdentifier(Name))
- return Error(L, "expected symbol after directive");
-
- MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
- const MCExpr *Expr = MCSymbolRefExpr::Create(Sym, getContext());
- Expr = ARM64MCExpr::Create(Expr, ARM64MCExpr::VK_TLSDESC, getContext());
-
- MCInst Inst;
- Inst.setOpcode(ARM64::TLSDESCCALL);
- Inst.addOperand(MCOperand::CreateExpr(Expr));
-
- getParser().getStreamer().EmitInstruction(Inst, STI);
- return false;
-}
-
-/// ::= .loh <lohName | lohId> label1, ..., labelN
-/// The number of arguments depends on the loh identifier.
-bool ARM64AsmParser::parseDirectiveLOH(StringRef IDVal, SMLoc Loc) {
- if (IDVal != MCLOHDirectiveName())
- return true;
- MCLOHType Kind;
- if (getParser().getTok().isNot(AsmToken::Identifier)) {
- if (getParser().getTok().isNot(AsmToken::Integer))
- return TokError("expected an identifier or a number in directive");
- // We successfully get a numeric value for the identifier.
- // Check if it is valid.
- int64_t Id = getParser().getTok().getIntVal();
- Kind = (MCLOHType)Id;
- // Check that Id does not overflow MCLOHType.
- if (!isValidMCLOHType(Kind) || Id != Kind)
- return TokError("invalid numeric identifier in directive");
- } else {
- StringRef Name = getTok().getIdentifier();
- // We successfully parse an identifier.
- // Check if it is a recognized one.
- int Id = MCLOHNameToId(Name);
-
- if (Id == -1)
- return TokError("invalid identifier in directive");
- Kind = (MCLOHType)Id;
- }
- // Consume the identifier.
- Lex();
- // Get the number of arguments of this LOH.
- int NbArgs = MCLOHIdToNbArgs(Kind);
-
- assert(NbArgs != -1 && "Invalid number of arguments");
-
- SmallVector<MCSymbol *, 3> Args;
- for (int Idx = 0; Idx < NbArgs; ++Idx) {
- StringRef Name;
- if (getParser().parseIdentifier(Name))
- return TokError("expected identifier in directive");
- Args.push_back(getContext().GetOrCreateSymbol(Name));
-
- if (Idx + 1 == NbArgs)
- break;
- if (getLexer().isNot(AsmToken::Comma))
- return TokError("unexpected token in '" + Twine(IDVal) + "' directive");
- Lex();
- }
- if (getLexer().isNot(AsmToken::EndOfStatement))
- return TokError("unexpected token in '" + Twine(IDVal) + "' directive");
-
- getStreamer().EmitLOHDirective((MCLOHType)Kind, Args);
- return false;
-}
-
-bool
-ARM64AsmParser::classifySymbolRef(const MCExpr *Expr,
- ARM64MCExpr::VariantKind &ELFRefKind,
- MCSymbolRefExpr::VariantKind &DarwinRefKind,
- int64_t &Addend) {
- ELFRefKind = ARM64MCExpr::VK_INVALID;
- DarwinRefKind = MCSymbolRefExpr::VK_None;
- Addend = 0;
-
- if (const ARM64MCExpr *AE = dyn_cast<ARM64MCExpr>(Expr)) {
- ELFRefKind = AE->getKind();
- Expr = AE->getSubExpr();
- }
-
- const MCSymbolRefExpr *SE = dyn_cast<MCSymbolRefExpr>(Expr);
- if (SE) {
- // It's a simple symbol reference with no addend.
- DarwinRefKind = SE->getKind();
- return true;
- }
-
- const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr);
- if (!BE)
- return false;
-
- SE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
- if (!SE)
- return false;
- DarwinRefKind = SE->getKind();
-
- if (BE->getOpcode() != MCBinaryExpr::Add &&
- BE->getOpcode() != MCBinaryExpr::Sub)
- return false;
-
- // See if the addend is is a constant, otherwise there's more going
- // on here than we can deal with.
- auto AddendExpr = dyn_cast<MCConstantExpr>(BE->getRHS());
- if (!AddendExpr)
- return false;
-
- Addend = AddendExpr->getValue();
- if (BE->getOpcode() == MCBinaryExpr::Sub)
- Addend = -Addend;
-
- // It's some symbol reference + a constant addend, but really
- // shouldn't use both Darwin and ELF syntax.
- return ELFRefKind == ARM64MCExpr::VK_INVALID ||
- DarwinRefKind == MCSymbolRefExpr::VK_None;
-}
-
-/// Force static initialization.
-extern "C" void LLVMInitializeARM64AsmParser() {
- RegisterMCAsmParser<ARM64AsmParser> X(TheARM64leTarget);
- RegisterMCAsmParser<ARM64AsmParser> Y(TheARM64beTarget);
-
- RegisterMCAsmParser<ARM64AsmParser> Z(TheAArch64leTarget);
- RegisterMCAsmParser<ARM64AsmParser> W(TheAArch64beTarget);
-}
-
-#define GET_REGISTER_MATCHER
-#define GET_SUBTARGET_FEATURE_NAME
-#define GET_MATCHER_IMPLEMENTATION
-#include "ARM64GenAsmMatcher.inc"
-
-// Define this matcher function after the auto-generated include so we
-// have the match class enum definitions.
-unsigned ARM64AsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
- unsigned Kind) {
- ARM64Operand *Op = static_cast<ARM64Operand *>(AsmOp);
- // If the kind is a token for a literal immediate, check if our asm
- // operand matches. This is for InstAliases which have a fixed-value
- // immediate in the syntax.
- int64_t ExpectedVal;
- switch (Kind) {
- default:
- return Match_InvalidOperand;
- case MCK__35_0:
- ExpectedVal = 0;
- break;
- case MCK__35_1:
- ExpectedVal = 1;
- break;
- case MCK__35_12:
- ExpectedVal = 12;
- break;
- case MCK__35_16:
- ExpectedVal = 16;
- break;
- case MCK__35_2:
- ExpectedVal = 2;
- break;
- case MCK__35_24:
- ExpectedVal = 24;
- break;
- case MCK__35_3:
- ExpectedVal = 3;
- break;
- case MCK__35_32:
- ExpectedVal = 32;
- break;
- case MCK__35_4:
- ExpectedVal = 4;
- break;
- case MCK__35_48:
- ExpectedVal = 48;
- break;
- case MCK__35_6:
- ExpectedVal = 6;
- break;
- case MCK__35_64:
- ExpectedVal = 64;
- break;
- case MCK__35_8:
- ExpectedVal = 8;
- break;
- }
- if (!Op->isImm())
- return Match_InvalidOperand;
- const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
- if (!CE)
- return Match_InvalidOperand;
- if (CE->getValue() == ExpectedVal)
- return Match_Success;
- return Match_InvalidOperand;
-}
Removed: llvm/trunk/lib/Target/ARM64/AsmParser/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/CMakeLists.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/CMakeLists.txt (removed)
@@ -1,6 +0,0 @@
-include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
-
-add_llvm_library(LLVMARM64AsmParser
- ARM64AsmParser.cpp
- )
-
Removed: llvm/trunk/lib/Target/ARM64/AsmParser/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/LLVMBuild.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/LLVMBuild.txt (removed)
@@ -1,23 +0,0 @@
-;===- ./lib/Target/ARM64/AsmParser/LLVMBuild.txt ---------------*- Conf -*--===;
-;
-; The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-; http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = ARM64AsmParser
-parent = ARM64
-required_libraries = ARM64Desc ARM64Info ARM64Utils MC MCParser Support
-add_to_library_groups = ARM64
Removed: llvm/trunk/lib/Target/ARM64/AsmParser/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/Makefile?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/Makefile (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/Makefile (removed)
@@ -1,15 +0,0 @@
-##===- lib/Target/ARM/AsmParser/Makefile -------------------*- Makefile -*-===##
-#
-# The LLVM Compiler Infrastructure
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-##===----------------------------------------------------------------------===##
-LEVEL = ../../../..
-LIBRARYNAME = LLVMARM64AsmParser
-
-# Hack: we need to include 'main' ARM target directory to grab private headers
-CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
-
-include $(LEVEL)/Makefile.common
Removed: llvm/trunk/lib/Target/ARM64/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/CMakeLists.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM64/CMakeLists.txt (removed)
@@ -1,51 +0,0 @@
-set(LLVM_TARGET_DEFINITIONS ARM64.td)
-
-tablegen(LLVM ARM64GenRegisterInfo.inc -gen-register-info)
-tablegen(LLVM ARM64GenInstrInfo.inc -gen-instr-info)
-tablegen(LLVM ARM64GenMCCodeEmitter.inc -gen-emitter -mc-emitter)
-tablegen(LLVM ARM64GenMCPseudoLowering.inc -gen-pseudo-lowering)
-tablegen(LLVM ARM64GenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM ARM64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
-tablegen(LLVM ARM64GenAsmMatcher.inc -gen-asm-matcher)
-tablegen(LLVM ARM64GenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM ARM64GenFastISel.inc -gen-fast-isel)
-tablegen(LLVM ARM64GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM ARM64GenSubtargetInfo.inc -gen-subtarget)
-tablegen(LLVM ARM64GenDisassemblerTables.inc -gen-disassembler)
-add_public_tablegen_target(ARM64CommonTableGen)
-
-add_llvm_target(ARM64CodeGen
- ARM64AddressTypePromotion.cpp
- ARM64AdvSIMDScalarPass.cpp
- ARM64AsmPrinter.cpp
- ARM64BranchRelaxation.cpp
- ARM64CleanupLocalDynamicTLSPass.cpp
- ARM64CollectLOH.cpp
- ARM64ConditionalCompares.cpp
- ARM64DeadRegisterDefinitionsPass.cpp
- ARM64ExpandPseudoInsts.cpp
- ARM64FastISel.cpp
- ARM64FrameLowering.cpp
- ARM64ISelDAGToDAG.cpp
- ARM64ISelLowering.cpp
- ARM64InstrInfo.cpp
- ARM64LoadStoreOptimizer.cpp
- ARM64MCInstLower.cpp
- ARM64PromoteConstant.cpp
- ARM64RegisterInfo.cpp
- ARM64SelectionDAGInfo.cpp
- ARM64StorePairSuppress.cpp
- ARM64Subtarget.cpp
- ARM64TargetMachine.cpp
- ARM64TargetObjectFile.cpp
- ARM64TargetTransformInfo.cpp
-)
-
-add_dependencies(LLVMARM64CodeGen intrinsics_gen)
-
-add_subdirectory(TargetInfo)
-add_subdirectory(AsmParser)
-add_subdirectory(Disassembler)
-add_subdirectory(InstPrinter)
-add_subdirectory(MCTargetDesc)
-add_subdirectory(Utils)
Removed: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (removed)
@@ -1,1548 +0,0 @@
-//===- ARM64Disassembler.cpp - Disassembler for ARM64 -----------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
-
-#include "ARM64Disassembler.h"
-#include "ARM64ExternalSymbolizer.h"
-#include "ARM64Subtarget.h"
-#include "MCTargetDesc/ARM64AddressingModes.h"
-#include "Utils/ARM64BaseInfo.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCFixedLenDisassembler.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/MemoryObject.h"
-#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Support/ErrorHandling.h"
-
-using namespace llvm;
-
-#define DEBUG_TYPE "arm64-disassembler"
-
-// Pull DecodeStatus and its enum values into the global namespace.
-typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
-
-// Forward declare these because the autogenerated code will reference them.
-// Definitions are further down.
-static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
- unsigned RegNo, uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
- unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
- unsigned RegNo, uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
- unsigned RegNo, uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
-
-static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
- uint32_t insn,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
- uint32_t insn,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
- uint32_t insn,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
- uint32_t insn,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Address, const void *Decoder);
-
-static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const void *Decoder);
-static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr,
- const void *Decoder);
-static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr,
- const void *Decoder);
-static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr,
- const void *Decoder);
-static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder);
-
-static bool Check(DecodeStatus &Out, DecodeStatus In) {
- switch (In) {
- case MCDisassembler::Success:
- // Out stays the same.
- return true;
- case MCDisassembler::SoftFail:
- Out = In;
- return true;
- case MCDisassembler::Fail:
- Out = In;
- return false;
- }
- llvm_unreachable("Invalid DecodeStatus!");
-}
-
-#include "ARM64GenDisassemblerTables.inc"
-#include "ARM64GenInstrInfo.inc"
-
-#define Success llvm::MCDisassembler::Success
-#define Fail llvm::MCDisassembler::Fail
-#define SoftFail llvm::MCDisassembler::SoftFail
-
-static MCDisassembler *createARM64Disassembler(const Target &T,
- const MCSubtargetInfo &STI,
- MCContext &Ctx) {
- return new ARM64Disassembler(STI, Ctx);
-}
-
-DecodeStatus ARM64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
- const MemoryObject &Region,
- uint64_t Address,
- raw_ostream &os,
- raw_ostream &cs) const {
- CommentStream = &cs;
-
- uint8_t bytes[4];
-
- Size = 0;
- // We want to read exactly 4 bytes of data.
- if (Region.readBytes(Address, 4, (uint8_t *)bytes) == -1)
- return Fail;
- Size = 4;
-
- // Encoded as a small-endian 32-bit word in the stream.
- uint32_t insn =
- (bytes[3] << 24) | (bytes[2] << 16) | (bytes[1] << 8) | (bytes[0] << 0);
-
- // Calling the auto-generated decoder function.
- return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
-}
-
-static MCSymbolizer *
-createARM64ExternalSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
- LLVMSymbolLookupCallback SymbolLookUp,
- void *DisInfo, MCContext *Ctx,
- MCRelocationInfo *RelInfo) {
- return new llvm::ARM64ExternalSymbolizer(
- *Ctx,
- std::unique_ptr<MCRelocationInfo>(RelInfo),
- GetOpInfo, SymbolLookUp, DisInfo);
-}
-
-extern "C" void LLVMInitializeARM64Disassembler() {
- TargetRegistry::RegisterMCDisassembler(TheARM64leTarget,
- createARM64Disassembler);
- TargetRegistry::RegisterMCDisassembler(TheARM64beTarget,
- createARM64Disassembler);
- TargetRegistry::RegisterMCSymbolizer(TheARM64leTarget,
- createARM64ExternalSymbolizer);
- TargetRegistry::RegisterMCSymbolizer(TheARM64beTarget,
- createARM64ExternalSymbolizer);
-
- TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
- createARM64Disassembler);
- TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
- createARM64Disassembler);
- TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget,
- createARM64ExternalSymbolizer);
- TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget,
- createARM64ExternalSymbolizer);
-}
-
-static const unsigned FPR128DecoderTable[] = {
- ARM64::Q0, ARM64::Q1, ARM64::Q2, ARM64::Q3, ARM64::Q4, ARM64::Q5,
- ARM64::Q6, ARM64::Q7, ARM64::Q8, ARM64::Q9, ARM64::Q10, ARM64::Q11,
- ARM64::Q12, ARM64::Q13, ARM64::Q14, ARM64::Q15, ARM64::Q16, ARM64::Q17,
- ARM64::Q18, ARM64::Q19, ARM64::Q20, ARM64::Q21, ARM64::Q22, ARM64::Q23,
- ARM64::Q24, ARM64::Q25, ARM64::Q26, ARM64::Q27, ARM64::Q28, ARM64::Q29,
- ARM64::Q30, ARM64::Q31
-};
-
-static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
-
- unsigned Register = FPR128DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 15)
- return Fail;
- return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
-}
-
-static const unsigned FPR64DecoderTable[] = {
- ARM64::D0, ARM64::D1, ARM64::D2, ARM64::D3, ARM64::D4, ARM64::D5,
- ARM64::D6, ARM64::D7, ARM64::D8, ARM64::D9, ARM64::D10, ARM64::D11,
- ARM64::D12, ARM64::D13, ARM64::D14, ARM64::D15, ARM64::D16, ARM64::D17,
- ARM64::D18, ARM64::D19, ARM64::D20, ARM64::D21, ARM64::D22, ARM64::D23,
- ARM64::D24, ARM64::D25, ARM64::D26, ARM64::D27, ARM64::D28, ARM64::D29,
- ARM64::D30, ARM64::D31
-};
-
-static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
-
- unsigned Register = FPR64DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned FPR32DecoderTable[] = {
- ARM64::S0, ARM64::S1, ARM64::S2, ARM64::S3, ARM64::S4, ARM64::S5,
- ARM64::S6, ARM64::S7, ARM64::S8, ARM64::S9, ARM64::S10, ARM64::S11,
- ARM64::S12, ARM64::S13, ARM64::S14, ARM64::S15, ARM64::S16, ARM64::S17,
- ARM64::S18, ARM64::S19, ARM64::S20, ARM64::S21, ARM64::S22, ARM64::S23,
- ARM64::S24, ARM64::S25, ARM64::S26, ARM64::S27, ARM64::S28, ARM64::S29,
- ARM64::S30, ARM64::S31
-};
-
-static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
-
- unsigned Register = FPR32DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned FPR16DecoderTable[] = {
- ARM64::H0, ARM64::H1, ARM64::H2, ARM64::H3, ARM64::H4, ARM64::H5,
- ARM64::H6, ARM64::H7, ARM64::H8, ARM64::H9, ARM64::H10, ARM64::H11,
- ARM64::H12, ARM64::H13, ARM64::H14, ARM64::H15, ARM64::H16, ARM64::H17,
- ARM64::H18, ARM64::H19, ARM64::H20, ARM64::H21, ARM64::H22, ARM64::H23,
- ARM64::H24, ARM64::H25, ARM64::H26, ARM64::H27, ARM64::H28, ARM64::H29,
- ARM64::H30, ARM64::H31
-};
-
-static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
-
- unsigned Register = FPR16DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned FPR8DecoderTable[] = {
- ARM64::B0, ARM64::B1, ARM64::B2, ARM64::B3, ARM64::B4, ARM64::B5,
- ARM64::B6, ARM64::B7, ARM64::B8, ARM64::B9, ARM64::B10, ARM64::B11,
- ARM64::B12, ARM64::B13, ARM64::B14, ARM64::B15, ARM64::B16, ARM64::B17,
- ARM64::B18, ARM64::B19, ARM64::B20, ARM64::B21, ARM64::B22, ARM64::B23,
- ARM64::B24, ARM64::B25, ARM64::B26, ARM64::B27, ARM64::B28, ARM64::B29,
- ARM64::B30, ARM64::B31
-};
-
-static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
-
- unsigned Register = FPR8DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned GPR64DecoderTable[] = {
- ARM64::X0, ARM64::X1, ARM64::X2, ARM64::X3, ARM64::X4, ARM64::X5,
- ARM64::X6, ARM64::X7, ARM64::X8, ARM64::X9, ARM64::X10, ARM64::X11,
- ARM64::X12, ARM64::X13, ARM64::X14, ARM64::X15, ARM64::X16, ARM64::X17,
- ARM64::X18, ARM64::X19, ARM64::X20, ARM64::X21, ARM64::X22, ARM64::X23,
- ARM64::X24, ARM64::X25, ARM64::X26, ARM64::X27, ARM64::X28, ARM64::FP,
- ARM64::LR, ARM64::XZR
-};
-
-static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
-
- unsigned Register = GPR64DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
- unsigned Register = GPR64DecoderTable[RegNo];
- if (Register == ARM64::XZR)
- Register = ARM64::SP;
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned GPR32DecoderTable[] = {
- ARM64::W0, ARM64::W1, ARM64::W2, ARM64::W3, ARM64::W4, ARM64::W5,
- ARM64::W6, ARM64::W7, ARM64::W8, ARM64::W9, ARM64::W10, ARM64::W11,
- ARM64::W12, ARM64::W13, ARM64::W14, ARM64::W15, ARM64::W16, ARM64::W17,
- ARM64::W18, ARM64::W19, ARM64::W20, ARM64::W21, ARM64::W22, ARM64::W23,
- ARM64::W24, ARM64::W25, ARM64::W26, ARM64::W27, ARM64::W28, ARM64::W29,
- ARM64::W30, ARM64::WZR
-};
-
-static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
-
- unsigned Register = GPR32DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
-
- unsigned Register = GPR32DecoderTable[RegNo];
- if (Register == ARM64::WZR)
- Register = ARM64::WSP;
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned VectorDecoderTable[] = {
- ARM64::Q0, ARM64::Q1, ARM64::Q2, ARM64::Q3, ARM64::Q4, ARM64::Q5,
- ARM64::Q6, ARM64::Q7, ARM64::Q8, ARM64::Q9, ARM64::Q10, ARM64::Q11,
- ARM64::Q12, ARM64::Q13, ARM64::Q14, ARM64::Q15, ARM64::Q16, ARM64::Q17,
- ARM64::Q18, ARM64::Q19, ARM64::Q20, ARM64::Q21, ARM64::Q22, ARM64::Q23,
- ARM64::Q24, ARM64::Q25, ARM64::Q26, ARM64::Q27, ARM64::Q28, ARM64::Q29,
- ARM64::Q30, ARM64::Q31
-};
-
-static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
-
- unsigned Register = VectorDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned QQDecoderTable[] = {
- ARM64::Q0_Q1, ARM64::Q1_Q2, ARM64::Q2_Q3, ARM64::Q3_Q4,
- ARM64::Q4_Q5, ARM64::Q5_Q6, ARM64::Q6_Q7, ARM64::Q7_Q8,
- ARM64::Q8_Q9, ARM64::Q9_Q10, ARM64::Q10_Q11, ARM64::Q11_Q12,
- ARM64::Q12_Q13, ARM64::Q13_Q14, ARM64::Q14_Q15, ARM64::Q15_Q16,
- ARM64::Q16_Q17, ARM64::Q17_Q18, ARM64::Q18_Q19, ARM64::Q19_Q20,
- ARM64::Q20_Q21, ARM64::Q21_Q22, ARM64::Q22_Q23, ARM64::Q23_Q24,
- ARM64::Q24_Q25, ARM64::Q25_Q26, ARM64::Q26_Q27, ARM64::Q27_Q28,
- ARM64::Q28_Q29, ARM64::Q29_Q30, ARM64::Q30_Q31, ARM64::Q31_Q0
-};
-
-static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr, const void *Decoder) {
- if (RegNo > 31)
- return Fail;
- unsigned Register = QQDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned QQQDecoderTable[] = {
- ARM64::Q0_Q1_Q2, ARM64::Q1_Q2_Q3, ARM64::Q2_Q3_Q4,
- ARM64::Q3_Q4_Q5, ARM64::Q4_Q5_Q6, ARM64::Q5_Q6_Q7,
- ARM64::Q6_Q7_Q8, ARM64::Q7_Q8_Q9, ARM64::Q8_Q9_Q10,
- ARM64::Q9_Q10_Q11, ARM64::Q10_Q11_Q12, ARM64::Q11_Q12_Q13,
- ARM64::Q12_Q13_Q14, ARM64::Q13_Q14_Q15, ARM64::Q14_Q15_Q16,
- ARM64::Q15_Q16_Q17, ARM64::Q16_Q17_Q18, ARM64::Q17_Q18_Q19,
- ARM64::Q18_Q19_Q20, ARM64::Q19_Q20_Q21, ARM64::Q20_Q21_Q22,
- ARM64::Q21_Q22_Q23, ARM64::Q22_Q23_Q24, ARM64::Q23_Q24_Q25,
- ARM64::Q24_Q25_Q26, ARM64::Q25_Q26_Q27, ARM64::Q26_Q27_Q28,
- ARM64::Q27_Q28_Q29, ARM64::Q28_Q29_Q30, ARM64::Q29_Q30_Q31,
- ARM64::Q30_Q31_Q0, ARM64::Q31_Q0_Q1
-};
-
-static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr, const void *Decoder) {
- if (RegNo > 31)
- return Fail;
- unsigned Register = QQQDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned QQQQDecoderTable[] = {
- ARM64::Q0_Q1_Q2_Q3, ARM64::Q1_Q2_Q3_Q4, ARM64::Q2_Q3_Q4_Q5,
- ARM64::Q3_Q4_Q5_Q6, ARM64::Q4_Q5_Q6_Q7, ARM64::Q5_Q6_Q7_Q8,
- ARM64::Q6_Q7_Q8_Q9, ARM64::Q7_Q8_Q9_Q10, ARM64::Q8_Q9_Q10_Q11,
- ARM64::Q9_Q10_Q11_Q12, ARM64::Q10_Q11_Q12_Q13, ARM64::Q11_Q12_Q13_Q14,
- ARM64::Q12_Q13_Q14_Q15, ARM64::Q13_Q14_Q15_Q16, ARM64::Q14_Q15_Q16_Q17,
- ARM64::Q15_Q16_Q17_Q18, ARM64::Q16_Q17_Q18_Q19, ARM64::Q17_Q18_Q19_Q20,
- ARM64::Q18_Q19_Q20_Q21, ARM64::Q19_Q20_Q21_Q22, ARM64::Q20_Q21_Q22_Q23,
- ARM64::Q21_Q22_Q23_Q24, ARM64::Q22_Q23_Q24_Q25, ARM64::Q23_Q24_Q25_Q26,
- ARM64::Q24_Q25_Q26_Q27, ARM64::Q25_Q26_Q27_Q28, ARM64::Q26_Q27_Q28_Q29,
- ARM64::Q27_Q28_Q29_Q30, ARM64::Q28_Q29_Q30_Q31, ARM64::Q29_Q30_Q31_Q0,
- ARM64::Q30_Q31_Q0_Q1, ARM64::Q31_Q0_Q1_Q2
-};
-
-static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
- unsigned Register = QQQQDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned DDDecoderTable[] = {
- ARM64::D0_D1, ARM64::D1_D2, ARM64::D2_D3, ARM64::D3_D4,
- ARM64::D4_D5, ARM64::D5_D6, ARM64::D6_D7, ARM64::D7_D8,
- ARM64::D8_D9, ARM64::D9_D10, ARM64::D10_D11, ARM64::D11_D12,
- ARM64::D12_D13, ARM64::D13_D14, ARM64::D14_D15, ARM64::D15_D16,
- ARM64::D16_D17, ARM64::D17_D18, ARM64::D18_D19, ARM64::D19_D20,
- ARM64::D20_D21, ARM64::D21_D22, ARM64::D22_D23, ARM64::D23_D24,
- ARM64::D24_D25, ARM64::D25_D26, ARM64::D26_D27, ARM64::D27_D28,
- ARM64::D28_D29, ARM64::D29_D30, ARM64::D30_D31, ARM64::D31_D0
-};
-
-static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr, const void *Decoder) {
- if (RegNo > 31)
- return Fail;
- unsigned Register = DDDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned DDDDecoderTable[] = {
- ARM64::D0_D1_D2, ARM64::D1_D2_D3, ARM64::D2_D3_D4,
- ARM64::D3_D4_D5, ARM64::D4_D5_D6, ARM64::D5_D6_D7,
- ARM64::D6_D7_D8, ARM64::D7_D8_D9, ARM64::D8_D9_D10,
- ARM64::D9_D10_D11, ARM64::D10_D11_D12, ARM64::D11_D12_D13,
- ARM64::D12_D13_D14, ARM64::D13_D14_D15, ARM64::D14_D15_D16,
- ARM64::D15_D16_D17, ARM64::D16_D17_D18, ARM64::D17_D18_D19,
- ARM64::D18_D19_D20, ARM64::D19_D20_D21, ARM64::D20_D21_D22,
- ARM64::D21_D22_D23, ARM64::D22_D23_D24, ARM64::D23_D24_D25,
- ARM64::D24_D25_D26, ARM64::D25_D26_D27, ARM64::D26_D27_D28,
- ARM64::D27_D28_D29, ARM64::D28_D29_D30, ARM64::D29_D30_D31,
- ARM64::D30_D31_D0, ARM64::D31_D0_D1
-};
-
-static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr, const void *Decoder) {
- if (RegNo > 31)
- return Fail;
- unsigned Register = DDDDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static const unsigned DDDDDecoderTable[] = {
- ARM64::D0_D1_D2_D3, ARM64::D1_D2_D3_D4, ARM64::D2_D3_D4_D5,
- ARM64::D3_D4_D5_D6, ARM64::D4_D5_D6_D7, ARM64::D5_D6_D7_D8,
- ARM64::D6_D7_D8_D9, ARM64::D7_D8_D9_D10, ARM64::D8_D9_D10_D11,
- ARM64::D9_D10_D11_D12, ARM64::D10_D11_D12_D13, ARM64::D11_D12_D13_D14,
- ARM64::D12_D13_D14_D15, ARM64::D13_D14_D15_D16, ARM64::D14_D15_D16_D17,
- ARM64::D15_D16_D17_D18, ARM64::D16_D17_D18_D19, ARM64::D17_D18_D19_D20,
- ARM64::D18_D19_D20_D21, ARM64::D19_D20_D21_D22, ARM64::D20_D21_D22_D23,
- ARM64::D21_D22_D23_D24, ARM64::D22_D23_D24_D25, ARM64::D23_D24_D25_D26,
- ARM64::D24_D25_D26_D27, ARM64::D25_D26_D27_D28, ARM64::D26_D27_D28_D29,
- ARM64::D27_D28_D29_D30, ARM64::D28_D29_D30_D31, ARM64::D29_D30_D31_D0,
- ARM64::D30_D31_D0_D1, ARM64::D31_D0_D1_D2
-};
-
-static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Addr,
- const void *Decoder) {
- if (RegNo > 31)
- return Fail;
- unsigned Register = DDDDDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
-}
-
-static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr,
- const void *Decoder) {
- // scale{5} is asserted as 1 in tblgen.
- Imm |= 0x20;
- Inst.addOperand(MCOperand::CreateImm(64 - Imm));
- return Success;
-}
-
-static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr,
- const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(64 - Imm));
- return Success;
-}
-
-static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- int64_t ImmVal = Imm;
- const ARM64Disassembler *Dis =
- static_cast<const ARM64Disassembler *>(Decoder);
-
- // Sign-extend 19-bit immediate.
- if (ImmVal & (1 << (19 - 1)))
- ImmVal |= ~((1LL << 19) - 1);
-
- if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal << 2, Addr,
- Inst.getOpcode() != ARM64::LDRXl, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(ImmVal));
- return Success;
-}
-
-static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm((Imm >> 1) & 1));
- Inst.addOperand(MCOperand::CreateImm(Imm & 1));
- return Success;
-}
-
-static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address,
- const void *Decoder) {
- const ARM64Disassembler *Dis =
- static_cast<const ARM64Disassembler *>(Decoder);
- const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
-
- Imm |= 0x8000;
- Inst.addOperand(MCOperand::CreateImm(Imm));
-
- bool ValidNamed;
- (void)ARM64SysReg::MRSMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
-
- return ValidNamed ? Success : Fail;
-}
-
-static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address,
- const void *Decoder) {
- const ARM64Disassembler *Dis =
- static_cast<const ARM64Disassembler *>(Decoder);
- const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
-
- Imm |= 0x8000;
- Inst.addOperand(MCOperand::CreateImm(Imm));
-
- bool ValidNamed;
- (void)ARM64SysReg::MSRMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
-
- return ValidNamed ? Success : Fail;
-}
-
-static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const void *Decoder) {
- // This decoder exists to add the dummy Lane operand to the MCInst, which must
- // be 1 in assembly but has no other real manifestation.
- unsigned Rd = fieldFromInstruction(Insn, 0, 5);
- unsigned Rn = fieldFromInstruction(Insn, 5, 5);
- unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
-
- if (IsToVec) {
- DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
- DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
- } else {
- DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
- DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
- }
-
- // Add the lane
- Inst.addOperand(MCOperand::CreateImm(1));
-
- return Success;
-}
-
-static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
- unsigned Add) {
- Inst.addOperand(MCOperand::CreateImm(Add - Imm));
- return Success;
-}
-
-static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
- unsigned Add) {
- Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1)));
- return Success;
-}
-
-static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- return DecodeVecShiftRImm(Inst, Imm, 64);
-}
-
-static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr,
- const void *Decoder) {
- return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
-}
-
-static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- return DecodeVecShiftRImm(Inst, Imm, 32);
-}
-
-static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr,
- const void *Decoder) {
- return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
-}
-
-static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- return DecodeVecShiftRImm(Inst, Imm, 16);
-}
-
-static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr,
- const void *Decoder) {
- return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
-}
-
-static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- return DecodeVecShiftRImm(Inst, Imm, 8);
-}
-
-static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- return DecodeVecShiftLImm(Inst, Imm, 64);
-}
-
-static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- return DecodeVecShiftLImm(Inst, Imm, 32);
-}
-
-static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- return DecodeVecShiftLImm(Inst, Imm, 16);
-}
-
-static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- return DecodeVecShiftLImm(Inst, Imm, 8);
-}
-
-static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Addr,
- const void *Decoder) {
- unsigned Rd = fieldFromInstruction(insn, 0, 5);
- unsigned Rn = fieldFromInstruction(insn, 5, 5);
- unsigned Rm = fieldFromInstruction(insn, 16, 5);
- unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
- unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
- unsigned shift = (shiftHi << 6) | shiftLo;
- switch (Inst.getOpcode()) {
- default:
- return Fail;
- case ARM64::ADDWrs:
- case ARM64::ADDSWrs:
- case ARM64::SUBWrs:
- case ARM64::SUBSWrs:
- // if shift == '11' then ReservedValue()
- if (shiftHi == 0x3)
- return Fail;
- // Deliberate fallthrough
- case ARM64::ANDWrs:
- case ARM64::ANDSWrs:
- case ARM64::BICWrs:
- case ARM64::BICSWrs:
- case ARM64::ORRWrs:
- case ARM64::ORNWrs:
- case ARM64::EORWrs:
- case ARM64::EONWrs: {
- // if sf == '0' and imm6<5> == '1' then ReservedValue()
- if (shiftLo >> 5 == 1)
- return Fail;
- DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
- DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
- break;
- }
- case ARM64::ADDXrs:
- case ARM64::ADDSXrs:
- case ARM64::SUBXrs:
- case ARM64::SUBSXrs:
- // if shift == '11' then ReservedValue()
- if (shiftHi == 0x3)
- return Fail;
- // Deliberate fallthrough
- case ARM64::ANDXrs:
- case ARM64::ANDSXrs:
- case ARM64::BICXrs:
- case ARM64::BICSXrs:
- case ARM64::ORRXrs:
- case ARM64::ORNXrs:
- case ARM64::EORXrs:
- case ARM64::EONXrs:
- DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
- DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
- break;
- }
-
- Inst.addOperand(MCOperand::CreateImm(shift));
- return Success;
-}
-
-static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Addr,
- const void *Decoder) {
- unsigned Rd = fieldFromInstruction(insn, 0, 5);
- unsigned imm = fieldFromInstruction(insn, 5, 16);
- unsigned shift = fieldFromInstruction(insn, 21, 2);
- shift <<= 4;
- switch (Inst.getOpcode()) {
- default:
- return Fail;
- case ARM64::MOVZWi:
- case ARM64::MOVNWi:
- case ARM64::MOVKWi:
- if (shift & (1U << 5))
- return Fail;
- DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
- break;
- case ARM64::MOVZXi:
- case ARM64::MOVNXi:
- case ARM64::MOVKXi:
- DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
- break;
- }
-
- if (Inst.getOpcode() == ARM64::MOVKWi || Inst.getOpcode() == ARM64::MOVKXi)
- Inst.addOperand(Inst.getOperand(0));
-
- Inst.addOperand(MCOperand::CreateImm(imm));
- Inst.addOperand(MCOperand::CreateImm(shift));
- return Success;
-}
-
-static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Addr,
- const void *Decoder) {
- unsigned Rt = fieldFromInstruction(insn, 0, 5);
- unsigned Rn = fieldFromInstruction(insn, 5, 5);
- unsigned offset = fieldFromInstruction(insn, 10, 12);
- const ARM64Disassembler *Dis =
- static_cast<const ARM64Disassembler *>(Decoder);
-
- switch (Inst.getOpcode()) {
- default:
- return Fail;
- case ARM64::PRFMui:
- // Rt is an immediate in prefetch.
- Inst.addOperand(MCOperand::CreateImm(Rt));
- break;
- case ARM64::STRBBui:
- case ARM64::LDRBBui:
- case ARM64::LDRSBWui:
- case ARM64::STRHHui:
- case ARM64::LDRHHui:
- case ARM64::LDRSHWui:
- case ARM64::STRWui:
- case ARM64::LDRWui:
- DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDRSBXui:
- case ARM64::LDRSHXui:
- case ARM64::LDRSWui:
- case ARM64::STRXui:
- case ARM64::LDRXui:
- DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDRQui:
- case ARM64::STRQui:
- DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDRDui:
- case ARM64::STRDui:
- DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDRSui:
- case ARM64::STRSui:
- DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDRHui:
- case ARM64::STRHui:
- DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDRBui:
- case ARM64::STRBui:
- DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- }
-
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(offset));
- return Success;
-}
-
-static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Addr,
- const void *Decoder) {
- unsigned Rt = fieldFromInstruction(insn, 0, 5);
- unsigned Rn = fieldFromInstruction(insn, 5, 5);
- int64_t offset = fieldFromInstruction(insn, 12, 9);
-
- // offset is a 9-bit signed immediate, so sign extend it to
- // fill the unsigned.
- if (offset & (1 << (9 - 1)))
- offset |= ~((1LL << 9) - 1);
-
- // First operand is always the writeback to the address register, if needed.
- switch (Inst.getOpcode()) {
- default:
- break;
- case ARM64::LDRSBWpre:
- case ARM64::LDRSHWpre:
- case ARM64::STRBBpre:
- case ARM64::LDRBBpre:
- case ARM64::STRHHpre:
- case ARM64::LDRHHpre:
- case ARM64::STRWpre:
- case ARM64::LDRWpre:
- case ARM64::LDRSBWpost:
- case ARM64::LDRSHWpost:
- case ARM64::STRBBpost:
- case ARM64::LDRBBpost:
- case ARM64::STRHHpost:
- case ARM64::LDRHHpost:
- case ARM64::STRWpost:
- case ARM64::LDRWpost:
- case ARM64::LDRSBXpre:
- case ARM64::LDRSHXpre:
- case ARM64::STRXpre:
- case ARM64::LDRSWpre:
- case ARM64::LDRXpre:
- case ARM64::LDRSBXpost:
- case ARM64::LDRSHXpost:
- case ARM64::STRXpost:
- case ARM64::LDRSWpost:
- case ARM64::LDRXpost:
- case ARM64::LDRQpre:
- case ARM64::STRQpre:
- case ARM64::LDRQpost:
- case ARM64::STRQpost:
- case ARM64::LDRDpre:
- case ARM64::STRDpre:
- case ARM64::LDRDpost:
- case ARM64::STRDpost:
- case ARM64::LDRSpre:
- case ARM64::STRSpre:
- case ARM64::LDRSpost:
- case ARM64::STRSpost:
- case ARM64::LDRHpre:
- case ARM64::STRHpre:
- case ARM64::LDRHpost:
- case ARM64::STRHpost:
- case ARM64::LDRBpre:
- case ARM64::STRBpre:
- case ARM64::LDRBpost:
- case ARM64::STRBpost:
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- break;
- }
-
- switch (Inst.getOpcode()) {
- default:
- return Fail;
- case ARM64::PRFUMi:
- // Rt is an immediate in prefetch.
- Inst.addOperand(MCOperand::CreateImm(Rt));
- break;
- case ARM64::STURBBi:
- case ARM64::LDURBBi:
- case ARM64::LDURSBWi:
- case ARM64::STURHHi:
- case ARM64::LDURHHi:
- case ARM64::LDURSHWi:
- case ARM64::STURWi:
- case ARM64::LDURWi:
- case ARM64::LDTRSBWi:
- case ARM64::LDTRSHWi:
- case ARM64::STTRWi:
- case ARM64::LDTRWi:
- case ARM64::STTRHi:
- case ARM64::LDTRHi:
- case ARM64::LDTRBi:
- case ARM64::STTRBi:
- case ARM64::LDRSBWpre:
- case ARM64::LDRSHWpre:
- case ARM64::STRBBpre:
- case ARM64::LDRBBpre:
- case ARM64::STRHHpre:
- case ARM64::LDRHHpre:
- case ARM64::STRWpre:
- case ARM64::LDRWpre:
- case ARM64::LDRSBWpost:
- case ARM64::LDRSHWpost:
- case ARM64::STRBBpost:
- case ARM64::LDRBBpost:
- case ARM64::STRHHpost:
- case ARM64::LDRHHpost:
- case ARM64::STRWpost:
- case ARM64::LDRWpost:
- DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDURSBXi:
- case ARM64::LDURSHXi:
- case ARM64::LDURSWi:
- case ARM64::STURXi:
- case ARM64::LDURXi:
- case ARM64::LDTRSBXi:
- case ARM64::LDTRSHXi:
- case ARM64::LDTRSWi:
- case ARM64::STTRXi:
- case ARM64::LDTRXi:
- case ARM64::LDRSBXpre:
- case ARM64::LDRSHXpre:
- case ARM64::STRXpre:
- case ARM64::LDRSWpre:
- case ARM64::LDRXpre:
- case ARM64::LDRSBXpost:
- case ARM64::LDRSHXpost:
- case ARM64::STRXpost:
- case ARM64::LDRSWpost:
- case ARM64::LDRXpost:
- DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDURQi:
- case ARM64::STURQi:
- case ARM64::LDRQpre:
- case ARM64::STRQpre:
- case ARM64::LDRQpost:
- case ARM64::STRQpost:
- DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDURDi:
- case ARM64::STURDi:
- case ARM64::LDRDpre:
- case ARM64::STRDpre:
- case ARM64::LDRDpost:
- case ARM64::STRDpost:
- DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDURSi:
- case ARM64::STURSi:
- case ARM64::LDRSpre:
- case ARM64::STRSpre:
- case ARM64::LDRSpost:
- case ARM64::STRSpost:
- DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDURHi:
- case ARM64::STURHi:
- case ARM64::LDRHpre:
- case ARM64::STRHpre:
- case ARM64::LDRHpost:
- case ARM64::STRHpost:
- DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::LDURBi:
- case ARM64::STURBi:
- case ARM64::LDRBpre:
- case ARM64::STRBpre:
- case ARM64::LDRBpost:
- case ARM64::STRBpost:
- DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- }
-
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- Inst.addOperand(MCOperand::CreateImm(offset));
-
- bool IsLoad = fieldFromInstruction(insn, 22, 1);
- bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
- bool IsFP = fieldFromInstruction(insn, 26, 1);
-
- // Cannot write back to a transfer register (but xzr != sp).
- if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
- return SoftFail;
-
- return Success;
-}
-
-static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Addr,
- const void *Decoder) {
- unsigned Rt = fieldFromInstruction(insn, 0, 5);
- unsigned Rn = fieldFromInstruction(insn, 5, 5);
- unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
- unsigned Rs = fieldFromInstruction(insn, 16, 5);
-
- unsigned Opcode = Inst.getOpcode();
- switch (Opcode) {
- default:
- return Fail;
- case ARM64::STLXRW:
- case ARM64::STLXRB:
- case ARM64::STLXRH:
- case ARM64::STXRW:
- case ARM64::STXRB:
- case ARM64::STXRH:
- DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
- // FALLTHROUGH
- case ARM64::LDARW:
- case ARM64::LDARB:
- case ARM64::LDARH:
- case ARM64::LDAXRW:
- case ARM64::LDAXRB:
- case ARM64::LDAXRH:
- case ARM64::LDXRW:
- case ARM64::LDXRB:
- case ARM64::LDXRH:
- case ARM64::STLRW:
- case ARM64::STLRB:
- case ARM64::STLRH:
- DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::STLXRX:
- case ARM64::STXRX:
- DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
- // FALLTHROUGH
- case ARM64::LDARX:
- case ARM64::LDAXRX:
- case ARM64::LDXRX:
- case ARM64::STLRX:
- DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
- break;
- case ARM64::STLXPW:
- case ARM64::STXPW:
- DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
- // FALLTHROUGH
- case ARM64::LDAXPW:
- case ARM64::LDXPW:
- DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
- DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
- break;
- case ARM64::STLXPX:
- case ARM64::STXPX:
- DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
- // FALLTHROUGH
- case ARM64::LDAXPX:
- case ARM64::LDXPX:
- DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
- DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
- break;
- }
-
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
-
- // You shouldn't load to the same register twice in an instruction...
- if ((Opcode == ARM64::LDAXPW || Opcode == ARM64::LDXPW ||
- Opcode == ARM64::LDAXPX || Opcode == ARM64::LDXPX) &&
- Rt == Rt2)
- return SoftFail;
-
- return Success;
-}
-
-static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Addr,
- const void *Decoder) {
- unsigned Rt = fieldFromInstruction(insn, 0, 5);
- unsigned Rn = fieldFromInstruction(insn, 5, 5);
- unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
- int64_t offset = fieldFromInstruction(insn, 15, 7);
- bool IsLoad = fieldFromInstruction(insn, 22, 1);
-
- // offset is a 7-bit signed immediate, so sign extend it to
- // fill the unsigned.
- if (offset & (1 << (7 - 1)))
- offset |= ~((1LL << 7) - 1);
-
- unsigned Opcode = Inst.getOpcode();
- bool NeedsDisjointWritebackTransfer = false;
-
- // First operand is always writeback of base register.
- switch (Opcode) {
- default:
- break;
- case ARM64::LDPXpost:
- case ARM64::STPXpost:
- case ARM64::LDPSWpost:
- case ARM64::LDPXpre:
- case ARM64::STPXpre:
- case ARM64::LDPSWpre:
- case ARM64::LDPWpost:
- case ARM64::STPWpost:
- case ARM64::LDPWpre:
- case ARM64::STPWpre:
- case ARM64::LDPQpost:
- case ARM64::STPQpost:
- case ARM64::LDPQpre:
- case ARM64::STPQpre:
- case ARM64::LDPDpost:
- case ARM64::STPDpost:
- case ARM64::LDPDpre:
- case ARM64::STPDpre:
- case ARM64::LDPSpost:
- case ARM64::STPSpost:
- case ARM64::LDPSpre:
- case ARM64::STPSpre:
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- break;
- }
-
- switch (Opcode) {
- default:
- return Fail;
- case ARM64::LDPXpost:
- case ARM64::STPXpost:
- case ARM64::LDPSWpost:
- case ARM64::LDPXpre:
- case ARM64::STPXpre:
- case ARM64::LDPSWpre:
- NeedsDisjointWritebackTransfer = true;
- // Fallthrough
- case ARM64::LDNPXi:
- case ARM64::STNPXi:
- case ARM64::LDPXi:
- case ARM64::STPXi:
- case ARM64::LDPSWi:
- DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
- DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
- break;
- case ARM64::LDPWpost:
- case ARM64::STPWpost:
- case ARM64::LDPWpre:
- case ARM64::STPWpre:
- NeedsDisjointWritebackTransfer = true;
- // Fallthrough
- case ARM64::LDNPWi:
- case ARM64::STNPWi:
- case ARM64::LDPWi:
- case ARM64::STPWi:
- DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
- DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
- break;
- case ARM64::LDNPQi:
- case ARM64::STNPQi:
- case ARM64::LDPQpost:
- case ARM64::STPQpost:
- case ARM64::LDPQi:
- case ARM64::STPQi:
- case ARM64::LDPQpre:
- case ARM64::STPQpre:
- DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
- DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
- break;
- case ARM64::LDNPDi:
- case ARM64::STNPDi:
- case ARM64::LDPDpost:
- case ARM64::STPDpost:
- case ARM64::LDPDi:
- case ARM64::STPDi:
- case ARM64::LDPDpre:
- case ARM64::STPDpre:
- DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
- DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
- break;
- case ARM64::LDNPSi:
- case ARM64::STNPSi:
- case ARM64::LDPSpost:
- case ARM64::STPSpost:
- case ARM64::LDPSi:
- case ARM64::STPSi:
- case ARM64::LDPSpre:
- case ARM64::STPSpre:
- DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
- DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
- break;
- }
-
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- Inst.addOperand(MCOperand::CreateImm(offset));
-
- // You shouldn't load to the same register twice in an instruction...
- if (IsLoad && Rt == Rt2)
- return SoftFail;
-
- // ... or do any operation that writes-back to a transfer register. But note
- // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
- if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
- return SoftFail;
-
- return Success;
-}
-
-static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Addr,
- const void *Decoder) {
- unsigned Rd = fieldFromInstruction(insn, 0, 5);
- unsigned Rn = fieldFromInstruction(insn, 5, 5);
- unsigned Rm = fieldFromInstruction(insn, 16, 5);
- unsigned extend = fieldFromInstruction(insn, 10, 6);
-
- unsigned shift = extend & 0x7;
- if (shift > 4)
- return Fail;
-
- switch (Inst.getOpcode()) {
- default:
- return Fail;
- case ARM64::ADDWrx:
- case ARM64::SUBWrx:
- DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
- DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
- break;
- case ARM64::ADDSWrx:
- case ARM64::SUBSWrx:
- DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
- DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
- break;
- case ARM64::ADDXrx:
- case ARM64::SUBXrx:
- DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
- break;
- case ARM64::ADDSXrx:
- case ARM64::SUBSXrx:
- DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
- break;
- case ARM64::ADDXrx64:
- case ARM64::SUBXrx64:
- DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
- break;
- case ARM64::SUBSXrx64:
- case ARM64::ADDSXrx64:
- DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
- break;
- }
-
- Inst.addOperand(MCOperand::CreateImm(extend));
- return Success;
-}
-
-static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Addr,
- const void *Decoder) {
- unsigned Rd = fieldFromInstruction(insn, 0, 5);
- unsigned Rn = fieldFromInstruction(insn, 5, 5);
- unsigned Datasize = fieldFromInstruction(insn, 31, 1);
- unsigned imm;
-
- if (Datasize) {
- if (Inst.getOpcode() == ARM64::ANDSXri)
- DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
- else
- DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
- imm = fieldFromInstruction(insn, 10, 13);
- if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 64))
- return Fail;
- } else {
- if (Inst.getOpcode() == ARM64::ANDSWri)
- DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
- else
- DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
- imm = fieldFromInstruction(insn, 10, 12);
- if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 32))
- return Fail;
- }
- Inst.addOperand(MCOperand::CreateImm(imm));
- return Success;
-}
-
-static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Addr,
- const void *Decoder) {
- unsigned Rd = fieldFromInstruction(insn, 0, 5);
- unsigned cmode = fieldFromInstruction(insn, 12, 4);
- unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
- imm |= fieldFromInstruction(insn, 5, 5);
-
- if (Inst.getOpcode() == ARM64::MOVID)
- DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
- else
- DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
-
- Inst.addOperand(MCOperand::CreateImm(imm));
-
- switch (Inst.getOpcode()) {
- default:
- break;
- case ARM64::MOVIv4i16:
- case ARM64::MOVIv8i16:
- case ARM64::MVNIv4i16:
- case ARM64::MVNIv8i16:
- case ARM64::MOVIv2i32:
- case ARM64::MOVIv4i32:
- case ARM64::MVNIv2i32:
- case ARM64::MVNIv4i32:
- Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
- break;
- case ARM64::MOVIv2s_msl:
- case ARM64::MOVIv4s_msl:
- case ARM64::MVNIv2s_msl:
- case ARM64::MVNIv4s_msl:
- Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108));
- break;
- }
-
- return Success;
-}
-
-static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Addr,
- const void *Decoder) {
- unsigned Rd = fieldFromInstruction(insn, 0, 5);
- unsigned cmode = fieldFromInstruction(insn, 12, 4);
- unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
- imm |= fieldFromInstruction(insn, 5, 5);
-
- // Tied operands added twice.
- DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
- DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
-
- Inst.addOperand(MCOperand::CreateImm(imm));
- Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
-
- return Success;
-}
-
-static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Addr, const void *Decoder) {
- unsigned Rd = fieldFromInstruction(insn, 0, 5);
- int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
- imm |= fieldFromInstruction(insn, 29, 2);
- const ARM64Disassembler *Dis =
- static_cast<const ARM64Disassembler *>(Decoder);
-
- // Sign-extend the 21-bit immediate.
- if (imm & (1 << (21 - 1)))
- imm |= ~((1LL << 21) - 1);
-
- DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
- if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(imm));
-
- return Success;
-}
-
-static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Addr, const void *Decoder) {
- unsigned Rd = fieldFromInstruction(insn, 0, 5);
- unsigned Rn = fieldFromInstruction(insn, 5, 5);
- unsigned Imm = fieldFromInstruction(insn, 10, 14);
- unsigned S = fieldFromInstruction(insn, 29, 1);
- unsigned Datasize = fieldFromInstruction(insn, 31, 1);
-
- unsigned ShifterVal = (Imm >> 12) & 3;
- unsigned ImmVal = Imm & 0xFFF;
- const ARM64Disassembler *Dis =
- static_cast<const ARM64Disassembler *>(Decoder);
-
- if (ShifterVal != 0 && ShifterVal != 1)
- return Fail;
-
- if (Datasize) {
- if (Rd == 31 && !S)
- DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
- else
- DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- } else {
- if (Rd == 31 && !S)
- DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
- else
- DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
- DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
- }
-
- if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(ImmVal));
- Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal));
- return Success;
-}
-
-static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Addr,
- const void *Decoder) {
- int64_t imm = fieldFromInstruction(insn, 0, 26);
- const ARM64Disassembler *Dis =
- static_cast<const ARM64Disassembler *>(Decoder);
-
- // Sign-extend the 26-bit immediate.
- if (imm & (1 << (26 - 1)))
- imm |= ~((1LL << 26) - 1);
-
- if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(imm));
-
- return Success;
-}
-
-static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
- uint32_t insn, uint64_t Addr,
- const void *Decoder) {
- uint64_t op1 = fieldFromInstruction(insn, 16, 3);
- uint64_t op2 = fieldFromInstruction(insn, 5, 3);
- uint64_t crm = fieldFromInstruction(insn, 8, 4);
-
- uint64_t pstate_field = (op1 << 3) | op2;
-
- Inst.addOperand(MCOperand::CreateImm(pstate_field));
- Inst.addOperand(MCOperand::CreateImm(crm));
-
- bool ValidNamed;
- (void)ARM64PState::PStateMapper().toString(pstate_field, ValidNamed);
-
- return ValidNamed ? Success : Fail;
-}
-
-static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
- uint64_t Addr, const void *Decoder) {
- uint64_t Rt = fieldFromInstruction(insn, 0, 5);
- uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
- bit |= fieldFromInstruction(insn, 19, 5);
- int64_t dst = fieldFromInstruction(insn, 5, 14);
- const ARM64Disassembler *Dis =
- static_cast<const ARM64Disassembler *>(Decoder);
-
- // Sign-extend 14-bit immediate.
- if (dst & (1 << (14 - 1)))
- dst |= ~((1LL << 14) - 1);
-
- if (fieldFromInstruction(insn, 31, 1) == 0)
- DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
- else
- DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
- Inst.addOperand(MCOperand::CreateImm(bit));
- if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(dst));
-
- return Success;
-}
Removed: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.h (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.h (removed)
@@ -1,40 +0,0 @@
-//===- ARM64Disassembler.h - Disassembler for ARM64 -------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ARM64DISASSEMBLER_H
-#define ARM64DISASSEMBLER_H
-
-#include "llvm/MC/MCDisassembler.h"
-
-namespace llvm {
-
-class MCInst;
-class MemoryObject;
-class raw_ostream;
-
-class ARM64Disassembler : public MCDisassembler {
-public:
- ARM64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
- : MCDisassembler(STI, Ctx) {}
-
- ~ARM64Disassembler() {}
-
- /// getInstruction - See MCDisassembler.
- MCDisassembler::DecodeStatus
- getInstruction(MCInst &instr, uint64_t &size, const MemoryObject ®ion,
- uint64_t address, raw_ostream &vStream,
- raw_ostream &cStream) const override;
-};
-
-} // namespace llvm
-
-#endif
Removed: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.cpp (removed)
@@ -1,226 +0,0 @@
-//===- ARM64ExternalSymbolizer.cpp - Symbolizer for ARM64 -------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "ARM64ExternalSymbolizer.h"
-#include "ARM64Subtarget.h"
-#include "MCTargetDesc/ARM64AddressingModes.h"
-#include "Utils/ARM64BaseInfo.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/Support/Format.h"
-#include "llvm/Support/raw_ostream.h"
-
-using namespace llvm;
-
-#define DEBUG_TYPE "arm64-disassembler"
-
-static MCSymbolRefExpr::VariantKind
-getVariant(uint64_t LLVMDisassembler_VariantKind) {
- switch (LLVMDisassembler_VariantKind) {
- case LLVMDisassembler_VariantKind_None:
- return MCSymbolRefExpr::VK_None;
- case LLVMDisassembler_VariantKind_ARM64_PAGE:
- return MCSymbolRefExpr::VK_PAGE;
- case LLVMDisassembler_VariantKind_ARM64_PAGEOFF:
- return MCSymbolRefExpr::VK_PAGEOFF;
- case LLVMDisassembler_VariantKind_ARM64_GOTPAGE:
- return MCSymbolRefExpr::VK_GOTPAGE;
- case LLVMDisassembler_VariantKind_ARM64_GOTPAGEOFF:
- return MCSymbolRefExpr::VK_GOTPAGEOFF;
- case LLVMDisassembler_VariantKind_ARM64_TLVP:
- case LLVMDisassembler_VariantKind_ARM64_TLVOFF:
- default:
- assert(0 && "bad LLVMDisassembler_VariantKind");
- return MCSymbolRefExpr::VK_None;
- }
-}
-
-/// tryAddingSymbolicOperand - tryAddingSymbolicOperand trys to add a symbolic
-/// operand in place of the immediate Value in the MCInst. The immediate
-/// Value has not had any PC adjustment made by the caller. If the instruction
-/// is a branch that adds the PC to the immediate Value then isBranch is
-/// Success, else Fail. If GetOpInfo is non-null, then it is called to get any
-/// symbolic information at the Address for this instrution. If that returns
-/// non-zero then the symbolic information it returns is used to create an
-/// MCExpr and that is added as an operand to the MCInst. If GetOpInfo()
-/// returns zero and isBranch is Success then a symbol look up for
-/// Address + Value is done and if a symbol is found an MCExpr is created with
-/// that, else an MCExpr with Address + Value is created. If GetOpInfo()
-/// returns zero and isBranch is Fail then the the Opcode of the MCInst is
-/// tested and for ADRP an other instructions that help to load of pointers
-/// a symbol look up is done to see it is returns a specific reference type
-/// to add to the comment stream. This function returns Success if it adds
-/// an operand to the MCInst and Fail otherwise.
-bool ARM64ExternalSymbolizer::tryAddingSymbolicOperand(
- MCInst &MI,
- raw_ostream &CommentStream,
- int64_t Value,
- uint64_t Address,
- bool IsBranch,
- uint64_t Offset,
- uint64_t InstSize) {
- // FIXME: This method shares a lot of code with
- // MCExternalSymbolizer::tryAddingSymbolicOperand. It may be possible
- // refactor the MCExternalSymbolizer interface to allow more of this
- // implementation to be shared.
- //
- struct LLVMOpInfo1 SymbolicOp;
- memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
- SymbolicOp.Value = Value;
- uint64_t ReferenceType;
- const char *ReferenceName;
- if (!GetOpInfo ||
- !GetOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
- if (IsBranch) {
- ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
- const char *Name = SymbolLookUp(DisInfo, Address + Value, &ReferenceType,
- Address, &ReferenceName);
- if (Name) {
- SymbolicOp.AddSymbol.Name = Name;
- SymbolicOp.AddSymbol.Present = true;
- SymbolicOp.Value = 0;
- } else {
- SymbolicOp.Value = Address + Value;
- }
- if (ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
- CommentStream << "symbol stub for: " << ReferenceName;
- else if (ReferenceType ==
- LLVMDisassembler_ReferenceType_Out_Objc_Message)
- CommentStream << "Objc message: " << ReferenceName;
- } else if (MI.getOpcode() == ARM64::ADRP) {
- ReferenceType = LLVMDisassembler_ReferenceType_In_ARM64_ADRP;
- // otool expects the fully encoded ADRP instruction to be passed in as
- // the value here, so reconstruct it:
- const MCRegisterInfo &MCRI = *Ctx.getRegisterInfo();
- uint32_t EncodedInst = 0x90000000;
- EncodedInst |= (Value & 0x3) << 29; // immlo
- EncodedInst |= ((Value >> 2) & 0x7FFFF) << 5; // immhi
- EncodedInst |= MCRI.getEncodingValue(MI.getOperand(0).getReg()); // reg
- SymbolLookUp(DisInfo, EncodedInst, &ReferenceType, Address,
- &ReferenceName);
- CommentStream << format("0x%llx",
- 0xfffffffffffff000LL & (Address + Value));
- } else if (MI.getOpcode() == ARM64::ADDXri ||
- MI.getOpcode() == ARM64::LDRXui ||
- MI.getOpcode() == ARM64::LDRXl ||
- MI.getOpcode() == ARM64::ADR) {
- if (MI.getOpcode() == ARM64::ADDXri)
- ReferenceType = LLVMDisassembler_ReferenceType_In_ARM64_ADDXri;
- else if (MI.getOpcode() == ARM64::LDRXui)
- ReferenceType = LLVMDisassembler_ReferenceType_In_ARM64_LDRXui;
- if (MI.getOpcode() == ARM64::LDRXl) {
- ReferenceType = LLVMDisassembler_ReferenceType_In_ARM64_LDRXl;
- SymbolLookUp(DisInfo, Address + Value, &ReferenceType, Address,
- &ReferenceName);
- } else if (MI.getOpcode() == ARM64::ADR) {
- ReferenceType = LLVMDisassembler_ReferenceType_In_ARM64_ADR;
- SymbolLookUp(DisInfo, Address + Value, &ReferenceType, Address,
- &ReferenceName);
- } else {
- const MCRegisterInfo &MCRI = *Ctx.getRegisterInfo();
- // otool expects the fully encoded ADD/LDR instruction to be passed in
- // as the value here, so reconstruct it:
- unsigned EncodedInst =
- MI.getOpcode() == ARM64::ADDXri ? 0x91000000: 0xF9400000;
- EncodedInst |= Value << 10; // imm12 [+ shift:2 for ADD]
- EncodedInst |=
- MCRI.getEncodingValue(MI.getOperand(1).getReg()) << 5; // Rn
- EncodedInst |= MCRI.getEncodingValue(MI.getOperand(0).getReg()); // Rd
-
- SymbolLookUp(DisInfo, EncodedInst, &ReferenceType, Address,
- &ReferenceName);
- }
- if (ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr)
- CommentStream << "literal pool symbol address: " << ReferenceName;
- else if (ReferenceType ==
- LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
- CommentStream << "literal pool for: \"" << ReferenceName << "\"";
- else if (ReferenceType ==
- LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref)
- CommentStream << "Objc cfstring ref: @\"" << ReferenceName << "\"";
- else if (ReferenceType ==
- LLVMDisassembler_ReferenceType_Out_Objc_Message)
- CommentStream << "Objc message: " << ReferenceName;
- else if (ReferenceType ==
- LLVMDisassembler_ReferenceType_Out_Objc_Message_Ref)
- CommentStream << "Objc message ref: " << ReferenceName;
- else if (ReferenceType ==
- LLVMDisassembler_ReferenceType_Out_Objc_Selector_Ref)
- CommentStream << "Objc selector ref: " << ReferenceName;
- else if (ReferenceType ==
- LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref)
- CommentStream << "Objc class ref: " << ReferenceName;
- // For these instructions, the SymbolLookUp() above is just to get the
- // ReferenceType and ReferenceName. We want to make sure not to
- // fall through so we don't build an MCExpr to leave the disassembly
- // of the immediate values of these instructions to the InstPrinter.
- return false;
- } else {
- return false;
- }
- }
-
- const MCExpr *Add = nullptr;
- if (SymbolicOp.AddSymbol.Present) {
- if (SymbolicOp.AddSymbol.Name) {
- StringRef Name(SymbolicOp.AddSymbol.Name);
- MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
- MCSymbolRefExpr::VariantKind Variant = getVariant(SymbolicOp.VariantKind);
- if (Variant != MCSymbolRefExpr::VK_None)
- Add = MCSymbolRefExpr::Create(Sym, Variant, Ctx);
- else
- Add = MCSymbolRefExpr::Create(Sym, Ctx);
- } else {
- Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, Ctx);
- }
- }
-
- const MCExpr *Sub = nullptr;
- if (SymbolicOp.SubtractSymbol.Present) {
- if (SymbolicOp.SubtractSymbol.Name) {
- StringRef Name(SymbolicOp.SubtractSymbol.Name);
- MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
- Sub = MCSymbolRefExpr::Create(Sym, Ctx);
- } else {
- Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, Ctx);
- }
- }
-
- const MCExpr *Off = nullptr;
- if (SymbolicOp.Value != 0)
- Off = MCConstantExpr::Create(SymbolicOp.Value, Ctx);
-
- const MCExpr *Expr;
- if (Sub) {
- const MCExpr *LHS;
- if (Add)
- LHS = MCBinaryExpr::CreateSub(Add, Sub, Ctx);
- else
- LHS = MCUnaryExpr::CreateMinus(Sub, Ctx);
- if (Off)
- Expr = MCBinaryExpr::CreateAdd(LHS, Off, Ctx);
- else
- Expr = LHS;
- } else if (Add) {
- if (Off)
- Expr = MCBinaryExpr::CreateAdd(Add, Off, Ctx);
- else
- Expr = Add;
- } else {
- if (Off)
- Expr = Off;
- else
- Expr = MCConstantExpr::Create(0, Ctx);
- }
-
- MI.addOperand(MCOperand::CreateExpr(Expr));
-
- return true;
-}
Removed: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.h (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.h (removed)
@@ -1,37 +0,0 @@
-//===- ARM64ExternalSymbolizer.h - Symbolizer for ARM64 ---------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Symbolize ARM64 assembly code during disassembly using callbacks.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ARM64EXTERNALSYMBOLIZER_H
-#define ARM64EXTERNALSYMBOLIZER_H
-
-#include "llvm/MC/MCExternalSymbolizer.h"
-
-namespace llvm {
-
-class ARM64ExternalSymbolizer : public MCExternalSymbolizer {
-public:
- ARM64ExternalSymbolizer(MCContext &Ctx,
- std::unique_ptr<MCRelocationInfo> RelInfo,
- LLVMOpInfoCallback GetOpInfo,
- LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo)
- : MCExternalSymbolizer(Ctx, std::move(RelInfo), GetOpInfo, SymbolLookUp,
- DisInfo) {}
-
- bool tryAddingSymbolicOperand(MCInst &MI, raw_ostream &CommentStream,
- int64_t Value, uint64_t Address, bool IsBranch,
- uint64_t Offset, uint64_t InstSize) override;
-};
-
-} // namespace llvm
-
-#endif
Removed: llvm/trunk/lib/Target/ARM64/Disassembler/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/CMakeLists.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/CMakeLists.txt (removed)
@@ -1,14 +0,0 @@
-include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
-
-add_llvm_library(LLVMARM64Disassembler
- ARM64Disassembler.cpp
- ARM64ExternalSymbolizer.cpp
- )
-# workaround for hanging compilation on MSVC8, 9 and 10
-#if( MSVC_VERSION EQUAL 1400 OR MSVC_VERSION EQUAL 1500 OR MSVC_VERSION EQUAL 1600 )
-#set_property(
-# SOURCE ARMDisassembler.cpp
-# PROPERTY COMPILE_FLAGS "/Od"
-# )
-#endif()
-add_dependencies(LLVMARM64Disassembler ARM64CommonTableGen)
Removed: llvm/trunk/lib/Target/ARM64/Disassembler/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/LLVMBuild.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/LLVMBuild.txt (removed)
@@ -1,23 +0,0 @@
-;===- ./lib/Target/ARM64/Disassembler/LLVMBuild.txt ------------*- Conf -*--===;
-;
-; The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-; http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = ARM64Disassembler
-parent = ARM64
-required_libraries = ARM64Info ARM64Utils MC Support
-add_to_library_groups = ARM64
Removed: llvm/trunk/lib/Target/ARM64/Disassembler/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/Makefile?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/Makefile (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/Makefile (removed)
@@ -1,16 +0,0 @@
-##===- lib/Target/ARM64/Disassembler/Makefile --------------*- Makefile -*-===##
-#
-# The LLVM Compiler Infrastructure
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-##===----------------------------------------------------------------------===##
-
-LEVEL = ../../../..
-LIBRARYNAME = LLVMARM64Disassembler
-
-# Hack: we need to include 'main' arm target directory to grab private headers
-CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
-
-include $(LEVEL)/Makefile.common
Removed: llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp (removed)
@@ -1,1312 +0,0 @@
-//===-- ARM64InstPrinter.cpp - Convert ARM64 MCInst to assembly syntax ----===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This class prints an ARM64 MCInst to a .s file.
-//
-//===----------------------------------------------------------------------===//
-
-#include "ARM64InstPrinter.h"
-#include "MCTargetDesc/ARM64AddressingModes.h"
-#include "Utils/ARM64BaseInfo.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/StringExtras.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Support/Format.h"
-#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-#define DEBUG_TYPE "asm-printer"
-
-#define GET_INSTRUCTION_NAME
-#define PRINT_ALIAS_INSTR
-#include "ARM64GenAsmWriter.inc"
-#define GET_INSTRUCTION_NAME
-#define PRINT_ALIAS_INSTR
-#include "ARM64GenAsmWriter1.inc"
-
-ARM64InstPrinter::ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
- const MCRegisterInfo &MRI,
- const MCSubtargetInfo &STI)
- : MCInstPrinter(MAI, MII, MRI) {
- // Initialize the set of available features.
- setAvailableFeatures(STI.getFeatureBits());
-}
-
-ARM64AppleInstPrinter::ARM64AppleInstPrinter(const MCAsmInfo &MAI,
- const MCInstrInfo &MII,
- const MCRegisterInfo &MRI,
- const MCSubtargetInfo &STI)
- : ARM64InstPrinter(MAI, MII, MRI, STI) {}
-
-void ARM64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
- // This is for .cfi directives.
- OS << getRegisterName(RegNo);
-}
-
-void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
- StringRef Annot) {
- // Check for special encodings and print the canonical alias instead.
-
- unsigned Opcode = MI->getOpcode();
-
- if (Opcode == ARM64::SYSxt)
- if (printSysAlias(MI, O)) {
- printAnnotation(O, Annot);
- return;
- }
-
- // SBFM/UBFM should print to a nicer aliased form if possible.
- if (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri ||
- Opcode == ARM64::UBFMXri || Opcode == ARM64::UBFMWri) {
- const MCOperand &Op0 = MI->getOperand(0);
- const MCOperand &Op1 = MI->getOperand(1);
- const MCOperand &Op2 = MI->getOperand(2);
- const MCOperand &Op3 = MI->getOperand(3);
-
- bool IsSigned = (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri);
- bool Is64Bit = (Opcode == ARM64::SBFMXri || Opcode == ARM64::UBFMXri);
- if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
- const char *AsmMnemonic = nullptr;
-
- switch (Op3.getImm()) {
- default:
- break;
- case 7:
- if (IsSigned)
- AsmMnemonic = "sxtb";
- else if (!Is64Bit)
- AsmMnemonic = "uxtb";
- break;
- case 15:
- if (IsSigned)
- AsmMnemonic = "sxth";
- else if (!Is64Bit)
- AsmMnemonic = "uxth";
- break;
- case 31:
- // *xtw is only valid for signed 64-bit operations.
- if (Is64Bit && IsSigned)
- AsmMnemonic = "sxtw";
- break;
- }
-
- if (AsmMnemonic) {
- O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
- << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
- printAnnotation(O, Annot);
- return;
- }
- }
-
- // All immediate shifts are aliases, implemented using the Bitfield
- // instruction. In all cases the immediate shift amount shift must be in
- // the range 0 to (reg.size -1).
- if (Op2.isImm() && Op3.isImm()) {
- const char *AsmMnemonic = nullptr;
- int shift = 0;
- int64_t immr = Op2.getImm();
- int64_t imms = Op3.getImm();
- if (Opcode == ARM64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
- AsmMnemonic = "lsl";
- shift = 31 - imms;
- } else if (Opcode == ARM64::UBFMXri && imms != 0x3f &&
- ((imms + 1 == immr))) {
- AsmMnemonic = "lsl";
- shift = 63 - imms;
- } else if (Opcode == ARM64::UBFMWri && imms == 0x1f) {
- AsmMnemonic = "lsr";
- shift = immr;
- } else if (Opcode == ARM64::UBFMXri && imms == 0x3f) {
- AsmMnemonic = "lsr";
- shift = immr;
- } else if (Opcode == ARM64::SBFMWri && imms == 0x1f) {
- AsmMnemonic = "asr";
- shift = immr;
- } else if (Opcode == ARM64::SBFMXri && imms == 0x3f) {
- AsmMnemonic = "asr";
- shift = immr;
- }
- if (AsmMnemonic) {
- O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
- << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
- printAnnotation(O, Annot);
- return;
- }
- }
-
- // SBFIZ/UBFIZ aliases
- if (Op2.getImm() > Op3.getImm()) {
- O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
- << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
- << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
- printAnnotation(O, Annot);
- return;
- }
-
- // Otherwise SBFX/UBFX is the preferred form
- O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
- << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
- << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
- printAnnotation(O, Annot);
- return;
- }
-
- if (Opcode == ARM64::BFMXri || Opcode == ARM64::BFMWri) {
- const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
- const MCOperand &Op2 = MI->getOperand(2);
- int ImmR = MI->getOperand(3).getImm();
- int ImmS = MI->getOperand(4).getImm();
-
- // BFI alias
- if (ImmS < ImmR) {
- int BitWidth = Opcode == ARM64::BFMXri ? 64 : 32;
- int LSB = (BitWidth - ImmR) % BitWidth;
- int Width = ImmS + 1;
- O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
- << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
- printAnnotation(O, Annot);
- return;
- }
-
- int LSB = ImmR;
- int Width = ImmS - ImmR + 1;
- // Otherwise BFXIL the preferred form
- O << "\tbfxil\t"
- << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
- << ", #" << LSB << ", #" << Width;
- printAnnotation(O, Annot);
- return;
- }
-
- // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
- // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
- // printed.
- if ((Opcode == ARM64::MOVZXi || Opcode == ARM64::MOVZWi ||
- Opcode == ARM64::MOVNXi || Opcode == ARM64::MOVNWi) &&
- MI->getOperand(1).isExpr()) {
- if (Opcode == ARM64::MOVZXi || Opcode == ARM64::MOVZWi)
- O << "\tmovz\t";
- else
- O << "\tmovn\t";
-
- O << getRegisterName(MI->getOperand(0).getReg()) << ", #"
- << *MI->getOperand(1).getExpr();
- return;
- }
-
- if ((Opcode == ARM64::MOVKXi || Opcode == ARM64::MOVKWi) &&
- MI->getOperand(2).isExpr()) {
- O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
- << *MI->getOperand(2).getExpr();
- return;
- }
-
- if (!printAliasInstr(MI, O))
- printInstruction(MI, O);
-
- printAnnotation(O, Annot);
-}
-
-static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
- bool &IsTbx) {
- switch (Opcode) {
- case ARM64::TBXv8i8One:
- case ARM64::TBXv8i8Two:
- case ARM64::TBXv8i8Three:
- case ARM64::TBXv8i8Four:
- IsTbx = true;
- Layout = ".8b";
- return true;
- case ARM64::TBLv8i8One:
- case ARM64::TBLv8i8Two:
- case ARM64::TBLv8i8Three:
- case ARM64::TBLv8i8Four:
- IsTbx = false;
- Layout = ".8b";
- return true;
- case ARM64::TBXv16i8One:
- case ARM64::TBXv16i8Two:
- case ARM64::TBXv16i8Three:
- case ARM64::TBXv16i8Four:
- IsTbx = true;
- Layout = ".16b";
- return true;
- case ARM64::TBLv16i8One:
- case ARM64::TBLv16i8Two:
- case ARM64::TBLv16i8Three:
- case ARM64::TBLv16i8Four:
- IsTbx = false;
- Layout = ".16b";
- return true;
- default:
- return false;
- }
-}
-
-struct LdStNInstrDesc {
- unsigned Opcode;
- const char *Mnemonic;
- const char *Layout;
- int ListOperand;
- bool HasLane;
- int NaturalOffset;
-};
-
-static LdStNInstrDesc LdStNInstInfo[] = {
- { ARM64::LD1i8, "ld1", ".b", 1, true, 0 },
- { ARM64::LD1i16, "ld1", ".h", 1, true, 0 },
- { ARM64::LD1i32, "ld1", ".s", 1, true, 0 },
- { ARM64::LD1i64, "ld1", ".d", 1, true, 0 },
- { ARM64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
- { ARM64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
- { ARM64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
- { ARM64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
- { ARM64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
- { ARM64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
- { ARM64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
- { ARM64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
- { ARM64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
- { ARM64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
- { ARM64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
- { ARM64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
- { ARM64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
- { ARM64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
- { ARM64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
- { ARM64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
- { ARM64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
- { ARM64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
- { ARM64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
- { ARM64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
- { ARM64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
- { ARM64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
- { ARM64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
- { ARM64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
- { ARM64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
- { ARM64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
- { ARM64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
- { ARM64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
- { ARM64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
- { ARM64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
- { ARM64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
- { ARM64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
- { ARM64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
- { ARM64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
- { ARM64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
- { ARM64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
- { ARM64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
- { ARM64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
- { ARM64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
- { ARM64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
- { ARM64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
- { ARM64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
- { ARM64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
- { ARM64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
- { ARM64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
- { ARM64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
- { ARM64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
- { ARM64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
- { ARM64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
- { ARM64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
- { ARM64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
- { ARM64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
- { ARM64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
- { ARM64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
- { ARM64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
- { ARM64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
- { ARM64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
- { ARM64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
- { ARM64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
- { ARM64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
- { ARM64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
- { ARM64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
- { ARM64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
- { ARM64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
- { ARM64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
- { ARM64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
- { ARM64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
- { ARM64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
- { ARM64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
- { ARM64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
- { ARM64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
- { ARM64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
- { ARM64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
- { ARM64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
- { ARM64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
- { ARM64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
- { ARM64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
- { ARM64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
- { ARM64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
- { ARM64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
- { ARM64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
- { ARM64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
- { ARM64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
- { ARM64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
- { ARM64::LD2i8, "ld2", ".b", 1, true, 0 },
- { ARM64::LD2i16, "ld2", ".h", 1, true, 0 },
- { ARM64::LD2i32, "ld2", ".s", 1, true, 0 },
- { ARM64::LD2i64, "ld2", ".d", 1, true, 0 },
- { ARM64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
- { ARM64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
- { ARM64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
- { ARM64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
- { ARM64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
- { ARM64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
- { ARM64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
- { ARM64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
- { ARM64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
- { ARM64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
- { ARM64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
- { ARM64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
- { ARM64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
- { ARM64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
- { ARM64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
- { ARM64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
- { ARM64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
- { ARM64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
- { ARM64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
- { ARM64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
- { ARM64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
- { ARM64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
- { ARM64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
- { ARM64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
- { ARM64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
- { ARM64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
- { ARM64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
- { ARM64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
- { ARM64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
- { ARM64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
- { ARM64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
- { ARM64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
- { ARM64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
- { ARM64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
- { ARM64::LD3i8, "ld3", ".b", 1, true, 0 },
- { ARM64::LD3i16, "ld3", ".h", 1, true, 0 },
- { ARM64::LD3i32, "ld3", ".s", 1, true, 0 },
- { ARM64::LD3i64, "ld3", ".d", 1, true, 0 },
- { ARM64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
- { ARM64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
- { ARM64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
- { ARM64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
- { ARM64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
- { ARM64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
- { ARM64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
- { ARM64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
- { ARM64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
- { ARM64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
- { ARM64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
- { ARM64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
- { ARM64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
- { ARM64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
- { ARM64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
- { ARM64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
- { ARM64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
- { ARM64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
- { ARM64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
- { ARM64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
- { ARM64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
- { ARM64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
- { ARM64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
- { ARM64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
- { ARM64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
- { ARM64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
- { ARM64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
- { ARM64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
- { ARM64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
- { ARM64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
- { ARM64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
- { ARM64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
- { ARM64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
- { ARM64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
- { ARM64::LD4i8, "ld4", ".b", 1, true, 0 },
- { ARM64::LD4i16, "ld4", ".h", 1, true, 0 },
- { ARM64::LD4i32, "ld4", ".s", 1, true, 0 },
- { ARM64::LD4i64, "ld4", ".d", 1, true, 0 },
- { ARM64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
- { ARM64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
- { ARM64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
- { ARM64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
- { ARM64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
- { ARM64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
- { ARM64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
- { ARM64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
- { ARM64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
- { ARM64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
- { ARM64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
- { ARM64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
- { ARM64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
- { ARM64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
- { ARM64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
- { ARM64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
- { ARM64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
- { ARM64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
- { ARM64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
- { ARM64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
- { ARM64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
- { ARM64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
- { ARM64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
- { ARM64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
- { ARM64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
- { ARM64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
- { ARM64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
- { ARM64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
- { ARM64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
- { ARM64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
- { ARM64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
- { ARM64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
- { ARM64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
- { ARM64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
- { ARM64::ST1i8, "st1", ".b", 0, true, 0 },
- { ARM64::ST1i16, "st1", ".h", 0, true, 0 },
- { ARM64::ST1i32, "st1", ".s", 0, true, 0 },
- { ARM64::ST1i64, "st1", ".d", 0, true, 0 },
- { ARM64::ST1i8_POST, "st1", ".b", 1, true, 1 },
- { ARM64::ST1i16_POST, "st1", ".h", 1, true, 2 },
- { ARM64::ST1i32_POST, "st1", ".s", 1, true, 4 },
- { ARM64::ST1i64_POST, "st1", ".d", 1, true, 8 },
- { ARM64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
- { ARM64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
- { ARM64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
- { ARM64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
- { ARM64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
- { ARM64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
- { ARM64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
- { ARM64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
- { ARM64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
- { ARM64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
- { ARM64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
- { ARM64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
- { ARM64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
- { ARM64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
- { ARM64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
- { ARM64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
- { ARM64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
- { ARM64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
- { ARM64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
- { ARM64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
- { ARM64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
- { ARM64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
- { ARM64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
- { ARM64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
- { ARM64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
- { ARM64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
- { ARM64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
- { ARM64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
- { ARM64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
- { ARM64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
- { ARM64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
- { ARM64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
- { ARM64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
- { ARM64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
- { ARM64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
- { ARM64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
- { ARM64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
- { ARM64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
- { ARM64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
- { ARM64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
- { ARM64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
- { ARM64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
- { ARM64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
- { ARM64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
- { ARM64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
- { ARM64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
- { ARM64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
- { ARM64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
- { ARM64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
- { ARM64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
- { ARM64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
- { ARM64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
- { ARM64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
- { ARM64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
- { ARM64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
- { ARM64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
- { ARM64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
- { ARM64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
- { ARM64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
- { ARM64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
- { ARM64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
- { ARM64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
- { ARM64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
- { ARM64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
- { ARM64::ST2i8, "st2", ".b", 0, true, 0 },
- { ARM64::ST2i16, "st2", ".h", 0, true, 0 },
- { ARM64::ST2i32, "st2", ".s", 0, true, 0 },
- { ARM64::ST2i64, "st2", ".d", 0, true, 0 },
- { ARM64::ST2i8_POST, "st2", ".b", 1, true, 2 },
- { ARM64::ST2i16_POST, "st2", ".h", 1, true, 4 },
- { ARM64::ST2i32_POST, "st2", ".s", 1, true, 8 },
- { ARM64::ST2i64_POST, "st2", ".d", 1, true, 16 },
- { ARM64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
- { ARM64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
- { ARM64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
- { ARM64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
- { ARM64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
- { ARM64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
- { ARM64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
- { ARM64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
- { ARM64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
- { ARM64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
- { ARM64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
- { ARM64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
- { ARM64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
- { ARM64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
- { ARM64::ST3i8, "st3", ".b", 0, true, 0 },
- { ARM64::ST3i16, "st3", ".h", 0, true, 0 },
- { ARM64::ST3i32, "st3", ".s", 0, true, 0 },
- { ARM64::ST3i64, "st3", ".d", 0, true, 0 },
- { ARM64::ST3i8_POST, "st3", ".b", 1, true, 3 },
- { ARM64::ST3i16_POST, "st3", ".h", 1, true, 6 },
- { ARM64::ST3i32_POST, "st3", ".s", 1, true, 12 },
- { ARM64::ST3i64_POST, "st3", ".d", 1, true, 24 },
- { ARM64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
- { ARM64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
- { ARM64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
- { ARM64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
- { ARM64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
- { ARM64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
- { ARM64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
- { ARM64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
- { ARM64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
- { ARM64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
- { ARM64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
- { ARM64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
- { ARM64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
- { ARM64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
- { ARM64::ST4i8, "st4", ".b", 0, true, 0 },
- { ARM64::ST4i16, "st4", ".h", 0, true, 0 },
- { ARM64::ST4i32, "st4", ".s", 0, true, 0 },
- { ARM64::ST4i64, "st4", ".d", 0, true, 0 },
- { ARM64::ST4i8_POST, "st4", ".b", 1, true, 4 },
- { ARM64::ST4i16_POST, "st4", ".h", 1, true, 8 },
- { ARM64::ST4i32_POST, "st4", ".s", 1, true, 16 },
- { ARM64::ST4i64_POST, "st4", ".d", 1, true, 32 },
- { ARM64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
- { ARM64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
- { ARM64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
- { ARM64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
- { ARM64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
- { ARM64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
- { ARM64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
- { ARM64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
- { ARM64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
- { ARM64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
- { ARM64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
- { ARM64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
- { ARM64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
- { ARM64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
-};
-
-static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
- unsigned Idx;
- for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
- if (LdStNInstInfo[Idx].Opcode == Opcode)
- return &LdStNInstInfo[Idx];
-
- return nullptr;
-}
-
-void ARM64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
- StringRef Annot) {
- unsigned Opcode = MI->getOpcode();
- StringRef Layout, Mnemonic;
-
- bool IsTbx;
- if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
- O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
- << getRegisterName(MI->getOperand(0).getReg(), ARM64::vreg) << ", ";
-
- unsigned ListOpNum = IsTbx ? 2 : 1;
- printVectorList(MI, ListOpNum, O, "");
-
- O << ", "
- << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), ARM64::vreg);
- printAnnotation(O, Annot);
- return;
- }
-
- if (LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
- O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
-
- // Now onto the operands: first a vector list with possible lane
- // specifier. E.g. { v0 }[2]
- int OpNum = LdStDesc->ListOperand;
- printVectorList(MI, OpNum++, O, "");
-
- if (LdStDesc->HasLane)
- O << '[' << MI->getOperand(OpNum++).getImm() << ']';
-
- // Next the address: [xN]
- unsigned AddrReg = MI->getOperand(OpNum++).getReg();
- O << ", [" << getRegisterName(AddrReg) << ']';
-
- // Finally, there might be a post-indexed offset.
- if (LdStDesc->NaturalOffset != 0) {
- unsigned Reg = MI->getOperand(OpNum++).getReg();
- if (Reg != ARM64::XZR)
- O << ", " << getRegisterName(Reg);
- else {
- assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
- O << ", #" << LdStDesc->NaturalOffset;
- }
- }
-
- printAnnotation(O, Annot);
- return;
- }
-
- ARM64InstPrinter::printInst(MI, O, Annot);
-}
-
-bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
-#ifndef NDEBUG
- unsigned Opcode = MI->getOpcode();
- assert(Opcode == ARM64::SYSxt && "Invalid opcode for SYS alias!");
-#endif
-
- const char *Asm = nullptr;
- const MCOperand &Op1 = MI->getOperand(0);
- const MCOperand &Cn = MI->getOperand(1);
- const MCOperand &Cm = MI->getOperand(2);
- const MCOperand &Op2 = MI->getOperand(3);
-
- unsigned Op1Val = Op1.getImm();
- unsigned CnVal = Cn.getImm();
- unsigned CmVal = Cm.getImm();
- unsigned Op2Val = Op2.getImm();
-
- if (CnVal == 7) {
- switch (CmVal) {
- default:
- break;
-
- // IC aliases
- case 1:
- if (Op1Val == 0 && Op2Val == 0)
- Asm = "ic\tialluis";
- break;
- case 5:
- if (Op1Val == 0 && Op2Val == 0)
- Asm = "ic\tiallu";
- else if (Op1Val == 3 && Op2Val == 1)
- Asm = "ic\tivau";
- break;
-
- // DC aliases
- case 4:
- if (Op1Val == 3 && Op2Val == 1)
- Asm = "dc\tzva";
- break;
- case 6:
- if (Op1Val == 0 && Op2Val == 1)
- Asm = "dc\tivac";
- if (Op1Val == 0 && Op2Val == 2)
- Asm = "dc\tisw";
- break;
- case 10:
- if (Op1Val == 3 && Op2Val == 1)
- Asm = "dc\tcvac";
- else if (Op1Val == 0 && Op2Val == 2)
- Asm = "dc\tcsw";
- break;
- case 11:
- if (Op1Val == 3 && Op2Val == 1)
- Asm = "dc\tcvau";
- break;
- case 14:
- if (Op1Val == 3 && Op2Val == 1)
- Asm = "dc\tcivac";
- else if (Op1Val == 0 && Op2Val == 2)
- Asm = "dc\tcisw";
- break;
-
- // AT aliases
- case 8:
- switch (Op1Val) {
- default:
- break;
- case 0:
- switch (Op2Val) {
- default:
- break;
- case 0: Asm = "at\ts1e1r"; break;
- case 1: Asm = "at\ts1e1w"; break;
- case 2: Asm = "at\ts1e0r"; break;
- case 3: Asm = "at\ts1e0w"; break;
- }
- break;
- case 4:
- switch (Op2Val) {
- default:
- break;
- case 0: Asm = "at\ts1e2r"; break;
- case 1: Asm = "at\ts1e2w"; break;
- case 4: Asm = "at\ts12e1r"; break;
- case 5: Asm = "at\ts12e1w"; break;
- case 6: Asm = "at\ts12e0r"; break;
- case 7: Asm = "at\ts12e0w"; break;
- }
- break;
- case 6:
- switch (Op2Val) {
- default:
- break;
- case 0: Asm = "at\ts1e3r"; break;
- case 1: Asm = "at\ts1e3w"; break;
- }
- break;
- }
- break;
- }
- } else if (CnVal == 8) {
- // TLBI aliases
- switch (CmVal) {
- default:
- break;
- case 3:
- switch (Op1Val) {
- default:
- break;
- case 0:
- switch (Op2Val) {
- default:
- break;
- case 0: Asm = "tlbi\tvmalle1is"; break;
- case 1: Asm = "tlbi\tvae1is"; break;
- case 2: Asm = "tlbi\taside1is"; break;
- case 3: Asm = "tlbi\tvaae1is"; break;
- case 5: Asm = "tlbi\tvale1is"; break;
- case 7: Asm = "tlbi\tvaale1is"; break;
- }
- break;
- case 4:
- switch (Op2Val) {
- default:
- break;
- case 0: Asm = "tlbi\talle2is"; break;
- case 1: Asm = "tlbi\tvae2is"; break;
- case 4: Asm = "tlbi\talle1is"; break;
- case 5: Asm = "tlbi\tvale2is"; break;
- case 6: Asm = "tlbi\tvmalls12e1is"; break;
- }
- break;
- case 6:
- switch (Op2Val) {
- default:
- break;
- case 0: Asm = "tlbi\talle3is"; break;
- case 1: Asm = "tlbi\tvae3is"; break;
- case 5: Asm = "tlbi\tvale3is"; break;
- }
- break;
- }
- break;
- case 0:
- switch (Op1Val) {
- default:
- break;
- case 4:
- switch (Op2Val) {
- default:
- break;
- case 1: Asm = "tlbi\tipas2e1is"; break;
- case 5: Asm = "tlbi\tipas2le1is"; break;
- }
- break;
- }
- break;
- case 4:
- switch (Op1Val) {
- default:
- break;
- case 4:
- switch (Op2Val) {
- default:
- break;
- case 1: Asm = "tlbi\tipas2e1"; break;
- case 5: Asm = "tlbi\tipas2le1"; break;
- }
- break;
- }
- break;
- case 7:
- switch (Op1Val) {
- default:
- break;
- case 0:
- switch (Op2Val) {
- default:
- break;
- case 0: Asm = "tlbi\tvmalle1"; break;
- case 1: Asm = "tlbi\tvae1"; break;
- case 2: Asm = "tlbi\taside1"; break;
- case 3: Asm = "tlbi\tvaae1"; break;
- case 5: Asm = "tlbi\tvale1"; break;
- case 7: Asm = "tlbi\tvaale1"; break;
- }
- break;
- case 4:
- switch (Op2Val) {
- default:
- break;
- case 0: Asm = "tlbi\talle2"; break;
- case 1: Asm = "tlbi\tvae2"; break;
- case 4: Asm = "tlbi\talle1"; break;
- case 5: Asm = "tlbi\tvale2"; break;
- case 6: Asm = "tlbi\tvmalls12e1"; break;
- }
- break;
- case 6:
- switch (Op2Val) {
- default:
- break;
- case 0: Asm = "tlbi\talle3"; break;
- case 1: Asm = "tlbi\tvae3"; break;
- case 5: Asm = "tlbi\tvale3"; break;
- }
- break;
- }
- break;
- }
- }
-
- if (Asm) {
- unsigned Reg = MI->getOperand(4).getReg();
-
- O << '\t' << Asm;
- if (StringRef(Asm).lower().find("all") == StringRef::npos)
- O << ", " << getRegisterName(Reg);
- }
-
- return Asm != nullptr;
-}
-
-void ARM64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- const MCOperand &Op = MI->getOperand(OpNo);
- if (Op.isReg()) {
- unsigned Reg = Op.getReg();
- O << getRegisterName(Reg);
- } else if (Op.isImm()) {
- O << '#' << Op.getImm();
- } else {
- assert(Op.isExpr() && "unknown operand kind in printOperand");
- O << *Op.getExpr();
- }
-}
-
-void ARM64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- const MCOperand &Op = MI->getOperand(OpNo);
- O << format("#%#llx", Op.getImm());
-}
-
-void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
- unsigned Imm, raw_ostream &O) {
- const MCOperand &Op = MI->getOperand(OpNo);
- if (Op.isReg()) {
- unsigned Reg = Op.getReg();
- if (Reg == ARM64::XZR)
- O << "#" << Imm;
- else
- O << getRegisterName(Reg);
- } else
- assert(0 && "unknown operand kind in printPostIncOperand64");
-}
-
-void ARM64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- const MCOperand &Op = MI->getOperand(OpNo);
- assert(Op.isReg() && "Non-register vreg operand!");
- unsigned Reg = Op.getReg();
- O << getRegisterName(Reg, ARM64::vreg);
-}
-
-void ARM64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- const MCOperand &Op = MI->getOperand(OpNo);
- assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
- O << "c" << Op.getImm();
-}
-
-void ARM64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- const MCOperand &MO = MI->getOperand(OpNum);
- if (MO.isImm()) {
- unsigned Val = (MO.getImm() & 0xfff);
- assert(Val == MO.getImm() && "Add/sub immediate out of range!");
- unsigned Shift =
- ARM64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
- O << '#' << Val;
- if (Shift != 0)
- printShifter(MI, OpNum + 1, O);
-
- if (CommentStream)
- *CommentStream << '=' << (Val << Shift) << '\n';
- } else {
- assert(MO.isExpr() && "Unexpected operand type!");
- O << *MO.getExpr();
- printShifter(MI, OpNum + 1, O);
- }
-}
-
-void ARM64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- uint64_t Val = MI->getOperand(OpNum).getImm();
- O << "#0x";
- O.write_hex(ARM64_AM::decodeLogicalImmediate(Val, 32));
-}
-
-void ARM64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- uint64_t Val = MI->getOperand(OpNum).getImm();
- O << "#0x";
- O.write_hex(ARM64_AM::decodeLogicalImmediate(Val, 64));
-}
-
-void ARM64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- unsigned Val = MI->getOperand(OpNum).getImm();
- // LSL #0 should not be printed.
- if (ARM64_AM::getShiftType(Val) == ARM64_AM::LSL &&
- ARM64_AM::getShiftValue(Val) == 0)
- return;
- O << ", " << ARM64_AM::getShiftExtendName(ARM64_AM::getShiftType(Val)) << " #"
- << ARM64_AM::getShiftValue(Val);
-}
-
-void ARM64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- O << getRegisterName(MI->getOperand(OpNum).getReg());
- printShifter(MI, OpNum + 1, O);
-}
-
-void ARM64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- O << getRegisterName(MI->getOperand(OpNum).getReg());
- printArithExtend(MI, OpNum + 1, O);
-}
-
-void ARM64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- unsigned Val = MI->getOperand(OpNum).getImm();
- ARM64_AM::ShiftExtendType ExtType = ARM64_AM::getArithExtendType(Val);
- unsigned ShiftVal = ARM64_AM::getArithShiftValue(Val);
-
- // If the destination or first source register operand is [W]SP, print
- // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
- // all.
- if (ExtType == ARM64_AM::UXTW || ExtType == ARM64_AM::UXTX) {
- unsigned Dest = MI->getOperand(0).getReg();
- unsigned Src1 = MI->getOperand(1).getReg();
- if ( ((Dest == ARM64::SP || Src1 == ARM64::SP) &&
- ExtType == ARM64_AM::UXTX) ||
- ((Dest == ARM64::WSP || Src1 == ARM64::WSP) &&
- ExtType == ARM64_AM::UXTW) ) {
- if (ShiftVal != 0)
- O << ", lsl #" << ShiftVal;
- return;
- }
- }
- O << ", " << ARM64_AM::getShiftExtendName(ExtType);
- if (ShiftVal != 0)
- O << " #" << ShiftVal;
-}
-
-void ARM64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
- raw_ostream &O, char SrcRegKind,
- unsigned Width) {
- unsigned SignExtend = MI->getOperand(OpNum).getImm();
- unsigned DoShift = MI->getOperand(OpNum + 1).getImm();
-
- // sxtw, sxtx, uxtw or lsl (== uxtx)
- bool IsLSL = !SignExtend && SrcRegKind == 'x';
- if (IsLSL)
- O << "lsl";
- else
- O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
-
- if (DoShift || IsLSL)
- O << " #" << Log2_32(Width / 8);
-}
-
-void ARM64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
- O << ARM64CC::getCondCodeName(CC);
-}
-
-void ARM64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
- O << ARM64CC::getCondCodeName(ARM64CC::getInvertedCondCode(CC));
-}
-
-void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
-}
-
-template<int Scale>
-void ARM64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- O << '#' << Scale * MI->getOperand(OpNum).getImm();
-}
-
-void ARM64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
- unsigned Scale, raw_ostream &O) {
- const MCOperand MO = MI->getOperand(OpNum);
- if (MO.isImm()) {
- O << "#" << (MO.getImm() * Scale);
- } else {
- assert(MO.isExpr() && "Unexpected operand type!");
- O << *MO.getExpr();
- }
-}
-
-void ARM64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
- unsigned Scale, raw_ostream &O) {
- const MCOperand MO1 = MI->getOperand(OpNum + 1);
- O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
- if (MO1.isImm()) {
- O << ", #" << (MO1.getImm() * Scale);
- } else {
- assert(MO1.isExpr() && "Unexpected operand type!");
- O << ", " << *MO1.getExpr();
- }
- O << ']';
-}
-
-void ARM64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- unsigned prfop = MI->getOperand(OpNum).getImm();
- bool Valid;
- StringRef Name = ARM64PRFM::PRFMMapper().toString(prfop, Valid);
- if (Valid)
- O << Name;
- else
- O << '#' << prfop;
-}
-
-void ARM64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- const MCOperand &MO = MI->getOperand(OpNum);
- float FPImm = MO.isFPImm() ? MO.getFPImm() : ARM64_AM::getFPImmFloat(MO.getImm());
-
- // 8 decimal places are enough to perfectly represent permitted floats.
- O << format("#%.8f", FPImm);
-}
-
-static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
- while (Stride--) {
- switch (Reg) {
- default:
- assert(0 && "Vector register expected!");
- case ARM64::Q0: Reg = ARM64::Q1; break;
- case ARM64::Q1: Reg = ARM64::Q2; break;
- case ARM64::Q2: Reg = ARM64::Q3; break;
- case ARM64::Q3: Reg = ARM64::Q4; break;
- case ARM64::Q4: Reg = ARM64::Q5; break;
- case ARM64::Q5: Reg = ARM64::Q6; break;
- case ARM64::Q6: Reg = ARM64::Q7; break;
- case ARM64::Q7: Reg = ARM64::Q8; break;
- case ARM64::Q8: Reg = ARM64::Q9; break;
- case ARM64::Q9: Reg = ARM64::Q10; break;
- case ARM64::Q10: Reg = ARM64::Q11; break;
- case ARM64::Q11: Reg = ARM64::Q12; break;
- case ARM64::Q12: Reg = ARM64::Q13; break;
- case ARM64::Q13: Reg = ARM64::Q14; break;
- case ARM64::Q14: Reg = ARM64::Q15; break;
- case ARM64::Q15: Reg = ARM64::Q16; break;
- case ARM64::Q16: Reg = ARM64::Q17; break;
- case ARM64::Q17: Reg = ARM64::Q18; break;
- case ARM64::Q18: Reg = ARM64::Q19; break;
- case ARM64::Q19: Reg = ARM64::Q20; break;
- case ARM64::Q20: Reg = ARM64::Q21; break;
- case ARM64::Q21: Reg = ARM64::Q22; break;
- case ARM64::Q22: Reg = ARM64::Q23; break;
- case ARM64::Q23: Reg = ARM64::Q24; break;
- case ARM64::Q24: Reg = ARM64::Q25; break;
- case ARM64::Q25: Reg = ARM64::Q26; break;
- case ARM64::Q26: Reg = ARM64::Q27; break;
- case ARM64::Q27: Reg = ARM64::Q28; break;
- case ARM64::Q28: Reg = ARM64::Q29; break;
- case ARM64::Q29: Reg = ARM64::Q30; break;
- case ARM64::Q30: Reg = ARM64::Q31; break;
- // Vector lists can wrap around.
- case ARM64::Q31:
- Reg = ARM64::Q0;
- break;
- }
- }
- return Reg;
-}
-
-void ARM64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
- raw_ostream &O, StringRef LayoutSuffix) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
-
- O << "{ ";
-
- // Work out how many registers there are in the list (if there is an actual
- // list).
- unsigned NumRegs = 1;
- if (MRI.getRegClass(ARM64::DDRegClassID).contains(Reg) ||
- MRI.getRegClass(ARM64::QQRegClassID).contains(Reg))
- NumRegs = 2;
- else if (MRI.getRegClass(ARM64::DDDRegClassID).contains(Reg) ||
- MRI.getRegClass(ARM64::QQQRegClassID).contains(Reg))
- NumRegs = 3;
- else if (MRI.getRegClass(ARM64::DDDDRegClassID).contains(Reg) ||
- MRI.getRegClass(ARM64::QQQQRegClassID).contains(Reg))
- NumRegs = 4;
-
- // Now forget about the list and find out what the first register is.
- if (unsigned FirstReg = MRI.getSubReg(Reg, ARM64::dsub0))
- Reg = FirstReg;
- else if (unsigned FirstReg = MRI.getSubReg(Reg, ARM64::qsub0))
- Reg = FirstReg;
-
- // If it's a D-reg, we need to promote it to the equivalent Q-reg before
- // printing (otherwise getRegisterName fails).
- if (MRI.getRegClass(ARM64::FPR64RegClassID).contains(Reg)) {
- const MCRegisterClass &FPR128RC = MRI.getRegClass(ARM64::FPR128RegClassID);
- Reg = MRI.getMatchingSuperReg(Reg, ARM64::dsub, &FPR128RC);
- }
-
- for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
- O << getRegisterName(Reg, ARM64::vreg) << LayoutSuffix;
- if (i + 1 != NumRegs)
- O << ", ";
- }
-
- O << " }";
-}
-
-void ARM64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
- unsigned OpNum,
- raw_ostream &O) {
- printVectorList(MI, OpNum, O, "");
-}
-
-template <unsigned NumLanes, char LaneKind>
-void ARM64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- std::string Suffix(".");
- if (NumLanes)
- Suffix += itostr(NumLanes) + LaneKind;
- else
- Suffix += LaneKind;
-
- printVectorList(MI, OpNum, O, Suffix);
-}
-
-void ARM64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- O << "[" << MI->getOperand(OpNum).getImm() << "]";
-}
-
-void ARM64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- const MCOperand &Op = MI->getOperand(OpNum);
-
- // If the label has already been resolved to an immediate offset (say, when
- // we're running the disassembler), just print the immediate.
- if (Op.isImm()) {
- O << "#" << (Op.getImm() << 2);
- return;
- }
-
- // If the branch target is simply an address then print it in hex.
- const MCConstantExpr *BranchTarget =
- dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
- int64_t Address;
- if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
- O << "0x";
- O.write_hex(Address);
- } else {
- // Otherwise, just print the expression.
- O << *MI->getOperand(OpNum).getExpr();
- }
-}
-
-void ARM64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
- const MCOperand &Op = MI->getOperand(OpNum);
-
- // If the label has already been resolved to an immediate offset (say, when
- // we're running the disassembler), just print the immediate.
- if (Op.isImm()) {
- O << "#" << (Op.getImm() << 12);
- return;
- }
-
- // Otherwise, just print the expression.
- O << *MI->getOperand(OpNum).getExpr();
-}
-
-void ARM64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- unsigned Val = MI->getOperand(OpNo).getImm();
- unsigned Opcode = MI->getOpcode();
-
- bool Valid;
- StringRef Name;
- if (Opcode == ARM64::ISB)
- Name = ARM64ISB::ISBMapper().toString(Val, Valid);
- else
- Name = ARM64DB::DBarrierMapper().toString(Val, Valid);
- if (Valid)
- O << Name;
- else
- O << "#" << Val;
-}
-
-void ARM64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- unsigned Val = MI->getOperand(OpNo).getImm();
-
- bool Valid;
- auto Mapper = ARM64SysReg::MRSMapper(getAvailableFeatures());
- std::string Name = Mapper.toString(Val, Valid);
-
- if (Valid)
- O << StringRef(Name).upper();
-}
-
-void ARM64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- unsigned Val = MI->getOperand(OpNo).getImm();
-
- bool Valid;
- auto Mapper = ARM64SysReg::MSRMapper(getAvailableFeatures());
- std::string Name = Mapper.toString(Val, Valid);
-
- if (Valid)
- O << StringRef(Name).upper();
-}
-
-void ARM64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- unsigned Val = MI->getOperand(OpNo).getImm();
-
- bool Valid;
- StringRef Name = ARM64PState::PStateMapper().toString(Val, Valid);
- if (Valid)
- O << StringRef(Name.str()).upper();
- else
- O << "#" << Val;
-}
-
-void ARM64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- unsigned RawVal = MI->getOperand(OpNo).getImm();
- uint64_t Val = ARM64_AM::decodeAdvSIMDModImmType10(RawVal);
- O << format("#%#016llx", Val);
-}
Removed: llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h (removed)
@@ -1,140 +0,0 @@
-//===-- ARM64InstPrinter.h - Convert ARM64 MCInst to assembly syntax ------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This class prints an ARM64 MCInst to a .s file.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ARM64INSTPRINTER_H
-#define ARM64INSTPRINTER_H
-
-#include "MCTargetDesc/ARM64MCTargetDesc.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/MC/MCInstPrinter.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-
-namespace llvm {
-
-class MCOperand;
-
-class ARM64InstPrinter : public MCInstPrinter {
-public:
- ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
- const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
-
- void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
- void printRegName(raw_ostream &OS, unsigned RegNo) const override;
-
- // Autogenerated by tblgen.
- virtual void printInstruction(const MCInst *MI, raw_ostream &O);
- virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
- virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
- unsigned PrintMethodIdx, raw_ostream &O);
- virtual StringRef getRegName(unsigned RegNo) const {
- return getRegisterName(RegNo);
- }
- static const char *getRegisterName(unsigned RegNo,
- unsigned AltIdx = ARM64::NoRegAltName);
-
-protected:
- bool printSysAlias(const MCInst *MI, raw_ostream &O);
- // Operand printers
- void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
- raw_ostream &O);
- template<int Amount>
- void printPostIncOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
- printPostIncOperand(MI, OpNo, Amount, O);
- }
-
- void printVRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- void printSysCROperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- void printAddSubImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printLogicalImm32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printLogicalImm64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printShifter(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printShiftedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printArithExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-
- void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O,
- char SrcRegKind, unsigned Width);
- template <char SrcRegKind, unsigned Width>
- void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
- printMemExtend(MI, OpNum, O, SrcRegKind, Width);
- }
-
- void printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printInverseCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printAlignedLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale,
- raw_ostream &O);
- void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
- raw_ostream &O);
-
- template<int Scale>
- void printUImm12Offset(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
- printUImm12Offset(MI, OpNum, Scale, O);
- }
-
- template<int BitWidth>
- void printAMIndexedWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
- printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
- }
-
- void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-
- template<int Scale>
- void printImmScale(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-
- void printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-
- void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-
- void printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O,
- StringRef LayoutSuffix);
-
- /// Print a list of vector registers where the type suffix is implicit
- /// (i.e. attached to the instruction rather than the registers).
- void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
- raw_ostream &O);
-
- template <unsigned NumLanes, char LaneKind>
- void printTypedVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-
- void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printAdrpLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printBarrierOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printSystemPStateField(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-};
-
-class ARM64AppleInstPrinter : public ARM64InstPrinter {
-public:
- ARM64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
- const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
-
- void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
-
- void printInstruction(const MCInst *MI, raw_ostream &O) override;
- bool printAliasInstr(const MCInst *MI, raw_ostream &O) override;
- virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
- unsigned PrintMethodIdx, raw_ostream &O);
- StringRef getRegName(unsigned RegNo) const override {
- return getRegisterName(RegNo);
- }
- static const char *getRegisterName(unsigned RegNo,
- unsigned AltIdx = ARM64::NoRegAltName);
-};
-}
-
-#endif
Removed: llvm/trunk/lib/Target/ARM64/InstPrinter/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/CMakeLists.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/InstPrinter/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM64/InstPrinter/CMakeLists.txt (removed)
@@ -1,7 +0,0 @@
-include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
-
-add_llvm_library(LLVMARM64AsmPrinter
- ARM64InstPrinter.cpp
- )
-
-add_dependencies(LLVMARM64AsmPrinter ARM64CommonTableGen)
Removed: llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt (removed)
@@ -1,24 +0,0 @@
-;===- ./lib/Target/ARM64/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===;
-;
-; The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-; http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = ARM64AsmPrinter
-parent = ARM64
-required_libraries = ARM64Utils MC Support
-add_to_library_groups = ARM64
-
Removed: llvm/trunk/lib/Target/ARM64/InstPrinter/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/Makefile?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/InstPrinter/Makefile (original)
+++ llvm/trunk/lib/Target/ARM64/InstPrinter/Makefile (removed)
@@ -1,15 +0,0 @@
-##===- lib/Target/ARM64/AsmPrinter/Makefile ----------------*- Makefile -*-===##
-#
-# The LLVM Compiler Infrastructure
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-##===----------------------------------------------------------------------===##
-LEVEL = ../../../..
-LIBRARYNAME = LLVMARM64AsmPrinter
-
-# Hack: we need to include 'main' arm target directory to grab private headers
-CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
-
-include $(LEVEL)/Makefile.common
Removed: llvm/trunk/lib/Target/ARM64/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/LLVMBuild.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/ARM64/LLVMBuild.txt (removed)
@@ -1,35 +0,0 @@
-;===- ./lib/Target/ARM64/LLVMBuild.txt -------------------------*- Conf -*--===;
-;
-; The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-; http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[common]
-subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils
-
-[component_0]
-type = TargetGroup
-name = ARM64
-parent = Target
-has_asmparser = 1
-has_asmprinter = 1
-has_disassembler = 1
-has_jit = 1
-
-[component_1]
-type = Library
-name = ARM64CodeGen
-parent = ARM64
-required_libraries = ARM64AsmPrinter ARM64Desc ARM64Info ARM64Utils Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target
-add_to_library_groups = ARM64
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h (removed)
@@ -1,738 +0,0 @@
-//===- ARM64AddressingModes.h - ARM64 Addressing Modes ----------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the ARM64 addressing mode implementation stuff.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_ARM64_ARM64ADDRESSINGMODES_H
-#define LLVM_TARGET_ARM64_ARM64ADDRESSINGMODES_H
-
-#include "llvm/ADT/APFloat.h"
-#include "llvm/ADT/APInt.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MathExtras.h"
-#include <cassert>
-
-namespace llvm {
-
-/// ARM64_AM - ARM64 Addressing Mode Stuff
-namespace ARM64_AM {
-
-//===----------------------------------------------------------------------===//
-// Shifts
-//
-
-enum ShiftExtendType {
- InvalidShiftExtend = -1,
- LSL = 0,
- LSR,
- ASR,
- ROR,
- MSL,
-
- UXTB,
- UXTH,
- UXTW,
- UXTX,
-
- SXTB,
- SXTH,
- SXTW,
- SXTX,
-};
-
-/// getShiftName - Get the string encoding for the shift type.
-static inline const char *getShiftExtendName(ARM64_AM::ShiftExtendType ST) {
- switch (ST) {
- default: assert(false && "unhandled shift type!");
- case ARM64_AM::LSL: return "lsl";
- case ARM64_AM::LSR: return "lsr";
- case ARM64_AM::ASR: return "asr";
- case ARM64_AM::ROR: return "ror";
- case ARM64_AM::MSL: return "msl";
- case ARM64_AM::UXTB: return "uxtb";
- case ARM64_AM::UXTH: return "uxth";
- case ARM64_AM::UXTW: return "uxtw";
- case ARM64_AM::UXTX: return "uxtx";
- case ARM64_AM::SXTB: return "sxtb";
- case ARM64_AM::SXTH: return "sxth";
- case ARM64_AM::SXTW: return "sxtw";
- case ARM64_AM::SXTX: return "sxtx";
- }
- return nullptr;
-}
-
-/// getShiftType - Extract the shift type.
-static inline ARM64_AM::ShiftExtendType getShiftType(unsigned Imm) {
- switch ((Imm >> 6) & 0x7) {
- default: return ARM64_AM::InvalidShiftExtend;
- case 0: return ARM64_AM::LSL;
- case 1: return ARM64_AM::LSR;
- case 2: return ARM64_AM::ASR;
- case 3: return ARM64_AM::ROR;
- case 4: return ARM64_AM::MSL;
- }
-}
-
-/// getShiftValue - Extract the shift value.
-static inline unsigned getShiftValue(unsigned Imm) {
- return Imm & 0x3f;
-}
-
-/// getShifterImm - Encode the shift type and amount:
-/// imm: 6-bit shift amount
-/// shifter: 000 ==> lsl
-/// 001 ==> lsr
-/// 010 ==> asr
-/// 011 ==> ror
-/// 100 ==> msl
-/// {8-6} = shifter
-/// {5-0} = imm
-static inline unsigned getShifterImm(ARM64_AM::ShiftExtendType ST,
- unsigned Imm) {
- assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
- unsigned STEnc = 0;
- switch (ST) {
- default: llvm_unreachable("Invalid shift requested");
- case ARM64_AM::LSL: STEnc = 0; break;
- case ARM64_AM::LSR: STEnc = 1; break;
- case ARM64_AM::ASR: STEnc = 2; break;
- case ARM64_AM::ROR: STEnc = 3; break;
- case ARM64_AM::MSL: STEnc = 4; break;
- }
- return (STEnc << 6) | (Imm & 0x3f);
-}
-
-//===----------------------------------------------------------------------===//
-// Extends
-//
-
-/// getArithShiftValue - get the arithmetic shift value.
-static inline unsigned getArithShiftValue(unsigned Imm) {
- return Imm & 0x7;
-}
-
-/// getExtendType - Extract the extend type for operands of arithmetic ops.
-static inline ARM64_AM::ShiftExtendType getExtendType(unsigned Imm) {
- assert((Imm & 0x7) == Imm && "invalid immediate!");
- switch (Imm) {
- default: llvm_unreachable("Compiler bug!");
- case 0: return ARM64_AM::UXTB;
- case 1: return ARM64_AM::UXTH;
- case 2: return ARM64_AM::UXTW;
- case 3: return ARM64_AM::UXTX;
- case 4: return ARM64_AM::SXTB;
- case 5: return ARM64_AM::SXTH;
- case 6: return ARM64_AM::SXTW;
- case 7: return ARM64_AM::SXTX;
- }
-}
-
-static inline ARM64_AM::ShiftExtendType getArithExtendType(unsigned Imm) {
- return getExtendType((Imm >> 3) & 0x7);
-}
-
-/// Mapping from extend bits to required operation:
-/// shifter: 000 ==> uxtb
-/// 001 ==> uxth
-/// 010 ==> uxtw
-/// 011 ==> uxtx
-/// 100 ==> sxtb
-/// 101 ==> sxth
-/// 110 ==> sxtw
-/// 111 ==> sxtx
-inline unsigned getExtendEncoding(ARM64_AM::ShiftExtendType ET) {
- switch (ET) {
- default: llvm_unreachable("Invalid extend type requested");
- case ARM64_AM::UXTB: return 0; break;
- case ARM64_AM::UXTH: return 1; break;
- case ARM64_AM::UXTW: return 2; break;
- case ARM64_AM::UXTX: return 3; break;
- case ARM64_AM::SXTB: return 4; break;
- case ARM64_AM::SXTH: return 5; break;
- case ARM64_AM::SXTW: return 6; break;
- case ARM64_AM::SXTX: return 7; break;
- }
-}
-
-/// getArithExtendImm - Encode the extend type and shift amount for an
-/// arithmetic instruction:
-/// imm: 3-bit extend amount
-/// {5-3} = shifter
-/// {2-0} = imm3
-static inline unsigned getArithExtendImm(ARM64_AM::ShiftExtendType ET,
- unsigned Imm) {
- assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
- return (getExtendEncoding(ET) << 3) | (Imm & 0x7);
-}
-
-/// getMemDoShift - Extract the "do shift" flag value for load/store
-/// instructions.
-static inline bool getMemDoShift(unsigned Imm) {
- return (Imm & 0x1) != 0;
-}
-
-/// getExtendType - Extract the extend type for the offset operand of
-/// loads/stores.
-static inline ARM64_AM::ShiftExtendType getMemExtendType(unsigned Imm) {
- return getExtendType((Imm >> 1) & 0x7);
-}
-
-/// getExtendImm - Encode the extend type and amount for a load/store inst:
-/// doshift: should the offset be scaled by the access size
-/// shifter: 000 ==> uxtb
-/// 001 ==> uxth
-/// 010 ==> uxtw
-/// 011 ==> uxtx
-/// 100 ==> sxtb
-/// 101 ==> sxth
-/// 110 ==> sxtw
-/// 111 ==> sxtx
-/// {3-1} = shifter
-/// {0} = doshift
-static inline unsigned getMemExtendImm(ARM64_AM::ShiftExtendType ET,
- bool DoShift) {
- return (getExtendEncoding(ET) << 1) | unsigned(DoShift);
-}
-
-static inline uint64_t ror(uint64_t elt, unsigned size) {
- return ((elt & 1) << (size-1)) | (elt >> 1);
-}
-
-/// processLogicalImmediate - Determine if an immediate value can be encoded
-/// as the immediate operand of a logical instruction for the given register
-/// size. If so, return true with "encoding" set to the encoded value in
-/// the form N:immr:imms.
-static inline bool processLogicalImmediate(uint64_t imm, unsigned regSize,
- uint64_t &encoding) {
- if (imm == 0ULL || imm == ~0ULL ||
- (regSize != 64 && (imm >> regSize != 0 || imm == ~0U)))
- return false;
-
- unsigned size = 2;
- uint64_t eltVal = imm;
-
- // First, determine the element size.
- while (size < regSize) {
- unsigned numElts = regSize / size;
- unsigned mask = (1ULL << size) - 1;
- uint64_t lowestEltVal = imm & mask;
-
- bool allMatched = true;
- for (unsigned i = 1; i < numElts; ++i) {
- uint64_t currEltVal = (imm >> (i*size)) & mask;
- if (currEltVal != lowestEltVal) {
- allMatched = false;
- break;
- }
- }
-
- if (allMatched) {
- eltVal = lowestEltVal;
- break;
- }
-
- size *= 2;
- }
-
- // Second, determine the rotation to make the element be: 0^m 1^n.
- for (unsigned i = 0; i < size; ++i) {
- eltVal = ror(eltVal, size);
- uint32_t clz = countLeadingZeros(eltVal) - (64 - size);
- uint32_t cto = CountTrailingOnes_64(eltVal);
-
- if (clz + cto == size) {
- // Encode in immr the number of RORs it would take to get *from* this
- // element value to our target value, where i+1 is the number of RORs
- // to go the opposite direction.
- unsigned immr = size - (i + 1);
-
- // If size has a 1 in the n'th bit, create a value that has zeroes in
- // bits [0, n] and ones above that.
- uint64_t nimms = ~(size-1) << 1;
-
- // Or the CTO value into the low bits, which must be below the Nth bit
- // bit mentioned above.
- nimms |= (cto-1);
-
- // Extract the seventh bit and toggle it to create the N field.
- unsigned N = ((nimms >> 6) & 1) ^ 1;
-
- encoding = (N << 12) | (immr << 6) | (nimms & 0x3f);
- return true;
- }
- }
-
- return false;
-}
-
-/// isLogicalImmediate - Return true if the immediate is valid for a logical
-/// immediate instruction of the given register size. Return false otherwise.
-static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) {
- uint64_t encoding;
- return processLogicalImmediate(imm, regSize, encoding);
-}
-
-/// encodeLogicalImmediate - Return the encoded immediate value for a logical
-/// immediate instruction of the given register size.
-static inline uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize) {
- uint64_t encoding = 0;
- bool res = processLogicalImmediate(imm, regSize, encoding);
- assert(res && "invalid logical immediate");
- (void)res;
- return encoding;
-}
-
-/// decodeLogicalImmediate - Decode a logical immediate value in the form
-/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
-/// integer value it represents with regSize bits.
-static inline uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize) {
- // Extract the N, imms, and immr fields.
- unsigned N = (val >> 12) & 1;
- unsigned immr = (val >> 6) & 0x3f;
- unsigned imms = val & 0x3f;
-
- assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
- int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
- assert(len >= 0 && "undefined logical immediate encoding");
- unsigned size = (1 << len);
- unsigned R = immr & (size - 1);
- unsigned S = imms & (size - 1);
- assert(S != size - 1 && "undefined logical immediate encoding");
- uint64_t pattern = (1ULL << (S + 1)) - 1;
- for (unsigned i = 0; i < R; ++i)
- pattern = ror(pattern, size);
-
- // Replicate the pattern to fill the regSize.
- while (size != regSize) {
- pattern |= (pattern << size);
- size *= 2;
- }
- return pattern;
-}
-
-/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
-/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
-/// is a valid encoding for an integer value with regSize bits.
-static inline bool isValidDecodeLogicalImmediate(uint64_t val,
- unsigned regSize) {
- // Extract the N and imms fields needed for checking.
- unsigned N = (val >> 12) & 1;
- unsigned imms = val & 0x3f;
-
- if (regSize == 32 && N != 0) // undefined logical immediate encoding
- return false;
- int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
- if (len < 0) // undefined logical immediate encoding
- return false;
- unsigned size = (1 << len);
- unsigned S = imms & (size - 1);
- if (S == size - 1) // undefined logical immediate encoding
- return false;
-
- return true;
-}
-
-//===----------------------------------------------------------------------===//
-// Floating-point Immediates
-//
-static inline float getFPImmFloat(unsigned Imm) {
- // We expect an 8-bit binary encoding of a floating-point number here.
- union {
- uint32_t I;
- float F;
- } FPUnion;
-
- uint8_t Sign = (Imm >> 7) & 0x1;
- uint8_t Exp = (Imm >> 4) & 0x7;
- uint8_t Mantissa = Imm & 0xf;
-
- // 8-bit FP iEEEE Float Encoding
- // abcd efgh aBbbbbbc defgh000 00000000 00000000
- //
- // where B = NOT(b);
-
- FPUnion.I = 0;
- FPUnion.I |= Sign << 31;
- FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
- FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
- FPUnion.I |= (Exp & 0x3) << 23;
- FPUnion.I |= Mantissa << 19;
- return FPUnion.F;
-}
-
-/// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
-/// floating-point value. If the value cannot be represented as an 8-bit
-/// floating-point value, then return -1.
-static inline int getFP32Imm(const APInt &Imm) {
- uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
- int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
- int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
-
- // We can handle 4 bits of mantissa.
- // mantissa = (16+UInt(e:f:g:h))/16.
- if (Mantissa & 0x7ffff)
- return -1;
- Mantissa >>= 19;
- if ((Mantissa & 0xf) != Mantissa)
- return -1;
-
- // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
- if (Exp < -3 || Exp > 4)
- return -1;
- Exp = ((Exp+3) & 0x7) ^ 4;
-
- return ((int)Sign << 7) | (Exp << 4) | Mantissa;
-}
-
-static inline int getFP32Imm(const APFloat &FPImm) {
- return getFP32Imm(FPImm.bitcastToAPInt());
-}
-
-/// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
-/// floating-point value. If the value cannot be represented as an 8-bit
-/// floating-point value, then return -1.
-static inline int getFP64Imm(const APInt &Imm) {
- uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
- int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
- uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
-
- // We can handle 4 bits of mantissa.
- // mantissa = (16+UInt(e:f:g:h))/16.
- if (Mantissa & 0xffffffffffffULL)
- return -1;
- Mantissa >>= 48;
- if ((Mantissa & 0xf) != Mantissa)
- return -1;
-
- // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
- if (Exp < -3 || Exp > 4)
- return -1;
- Exp = ((Exp+3) & 0x7) ^ 4;
-
- return ((int)Sign << 7) | (Exp << 4) | Mantissa;
-}
-
-static inline int getFP64Imm(const APFloat &FPImm) {
- return getFP64Imm(FPImm.bitcastToAPInt());
-}
-
-//===--------------------------------------------------------------------===//
-// AdvSIMD Modified Immediates
-//===--------------------------------------------------------------------===//
-
-// 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
-static inline bool isAdvSIMDModImmType1(uint64_t Imm) {
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- ((Imm & 0xffffff00ffffff00ULL) == 0);
-}
-
-static inline uint8_t encodeAdvSIMDModImmType1(uint64_t Imm) {
- return (Imm & 0xffULL);
-}
-
-static inline uint64_t decodeAdvSIMDModImmType1(uint8_t Imm) {
- uint64_t EncVal = Imm;
- return (EncVal << 32) | EncVal;
-}
-
-// 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
-static inline bool isAdvSIMDModImmType2(uint64_t Imm) {
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- ((Imm & 0xffff00ffffff00ffULL) == 0);
-}
-
-static inline uint8_t encodeAdvSIMDModImmType2(uint64_t Imm) {
- return (Imm & 0xff00ULL) >> 8;
-}
-
-static inline uint64_t decodeAdvSIMDModImmType2(uint8_t Imm) {
- uint64_t EncVal = Imm;
- return (EncVal << 40) | (EncVal << 8);
-}
-
-// 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
-static inline bool isAdvSIMDModImmType3(uint64_t Imm) {
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- ((Imm & 0xff00ffffff00ffffULL) == 0);
-}
-
-static inline uint8_t encodeAdvSIMDModImmType3(uint64_t Imm) {
- return (Imm & 0xff0000ULL) >> 16;
-}
-
-static inline uint64_t decodeAdvSIMDModImmType3(uint8_t Imm) {
- uint64_t EncVal = Imm;
- return (EncVal << 48) | (EncVal << 16);
-}
-
-// abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
-static inline bool isAdvSIMDModImmType4(uint64_t Imm) {
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- ((Imm & 0x00ffffff00ffffffULL) == 0);
-}
-
-static inline uint8_t encodeAdvSIMDModImmType4(uint64_t Imm) {
- return (Imm & 0xff000000ULL) >> 24;
-}
-
-static inline uint64_t decodeAdvSIMDModImmType4(uint8_t Imm) {
- uint64_t EncVal = Imm;
- return (EncVal << 56) | (EncVal << 24);
-}
-
-// 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
-static inline bool isAdvSIMDModImmType5(uint64_t Imm) {
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
- ((Imm & 0xff00ff00ff00ff00ULL) == 0);
-}
-
-static inline uint8_t encodeAdvSIMDModImmType5(uint64_t Imm) {
- return (Imm & 0xffULL);
-}
-
-static inline uint64_t decodeAdvSIMDModImmType5(uint8_t Imm) {
- uint64_t EncVal = Imm;
- return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;
-}
-
-// abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
-static inline bool isAdvSIMDModImmType6(uint64_t Imm) {
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
- ((Imm & 0x00ff00ff00ff00ffULL) == 0);
-}
-
-static inline uint8_t encodeAdvSIMDModImmType6(uint64_t Imm) {
- return (Imm & 0xff00ULL) >> 8;
-}
-
-static inline uint64_t decodeAdvSIMDModImmType6(uint8_t Imm) {
- uint64_t EncVal = Imm;
- return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);
-}
-
-// 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
-static inline bool isAdvSIMDModImmType7(uint64_t Imm) {
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
-}
-
-static inline uint8_t encodeAdvSIMDModImmType7(uint64_t Imm) {
- return (Imm & 0xff00ULL) >> 8;
-}
-
-static inline uint64_t decodeAdvSIMDModImmType7(uint8_t Imm) {
- uint64_t EncVal = Imm;
- return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;
-}
-
-// 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
-static inline bool isAdvSIMDModImmType8(uint64_t Imm) {
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
-}
-
-static inline uint64_t decodeAdvSIMDModImmType8(uint8_t Imm) {
- uint64_t EncVal = Imm;
- return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;
-}
-
-static inline uint8_t encodeAdvSIMDModImmType8(uint64_t Imm) {
- return (Imm & 0x00ff0000ULL) >> 16;
-}
-
-// abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
-static inline bool isAdvSIMDModImmType9(uint64_t Imm) {
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- ((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
- ((Imm >> 56) == (Imm & 0x000000ffULL));
-}
-
-static inline uint8_t encodeAdvSIMDModImmType9(uint64_t Imm) {
- return (Imm & 0xffULL);
-}
-
-static inline uint64_t decodeAdvSIMDModImmType9(uint8_t Imm) {
- uint64_t EncVal = Imm;
- EncVal |= (EncVal << 8);
- EncVal |= (EncVal << 16);
- EncVal |= (EncVal << 32);
- return EncVal;
-}
-
-// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
-// cmode: 1110, op: 1
-static inline bool isAdvSIMDModImmType10(uint64_t Imm) {
- uint64_t ByteA = Imm & 0xff00000000000000ULL;
- uint64_t ByteB = Imm & 0x00ff000000000000ULL;
- uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
- uint64_t ByteD = Imm & 0x000000ff00000000ULL;
- uint64_t ByteE = Imm & 0x00000000ff000000ULL;
- uint64_t ByteF = Imm & 0x0000000000ff0000ULL;
- uint64_t ByteG = Imm & 0x000000000000ff00ULL;
- uint64_t ByteH = Imm & 0x00000000000000ffULL;
-
- return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
- (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
- (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
- (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
- (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
- (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
- (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
- (ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
-}
-
-static inline uint8_t encodeAdvSIMDModImmType10(uint64_t Imm) {
- uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0;
- uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0;
- uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0;
- uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0;
- uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0;
- uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0;
- uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0;
- uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
-
- uint8_t EncVal = BitA;
- EncVal <<= 1;
- EncVal |= BitB;
- EncVal <<= 1;
- EncVal |= BitC;
- EncVal <<= 1;
- EncVal |= BitD;
- EncVal <<= 1;
- EncVal |= BitE;
- EncVal <<= 1;
- EncVal |= BitF;
- EncVal <<= 1;
- EncVal |= BitG;
- EncVal <<= 1;
- EncVal |= BitH;
- return EncVal;
-}
-
-static inline uint64_t decodeAdvSIMDModImmType10(uint8_t Imm) {
- uint64_t EncVal = 0;
- if (Imm & 0x80) EncVal |= 0xff00000000000000ULL;
- if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL;
- if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL;
- if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL;
- if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL;
- if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL;
- if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL;
- if (Imm & 0x01) EncVal |= 0x00000000000000ffULL;
- return EncVal;
-}
-
-// aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
-static inline bool isAdvSIMDModImmType11(uint64_t Imm) {
- uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
- return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
- (BString == 0x1f || BString == 0x20) &&
- ((Imm & 0x0007ffff0007ffffULL) == 0);
-}
-
-static inline uint8_t encodeAdvSIMDModImmType11(uint64_t Imm) {
- uint8_t BitA = (Imm & 0x80000000ULL) != 0;
- uint8_t BitB = (Imm & 0x20000000ULL) != 0;
- uint8_t BitC = (Imm & 0x01000000ULL) != 0;
- uint8_t BitD = (Imm & 0x00800000ULL) != 0;
- uint8_t BitE = (Imm & 0x00400000ULL) != 0;
- uint8_t BitF = (Imm & 0x00200000ULL) != 0;
- uint8_t BitG = (Imm & 0x00100000ULL) != 0;
- uint8_t BitH = (Imm & 0x00080000ULL) != 0;
-
- uint8_t EncVal = BitA;
- EncVal <<= 1;
- EncVal |= BitB;
- EncVal <<= 1;
- EncVal |= BitC;
- EncVal <<= 1;
- EncVal |= BitD;
- EncVal <<= 1;
- EncVal |= BitE;
- EncVal <<= 1;
- EncVal |= BitF;
- EncVal <<= 1;
- EncVal |= BitG;
- EncVal <<= 1;
- EncVal |= BitH;
- return EncVal;
-}
-
-static inline uint64_t decodeAdvSIMDModImmType11(uint8_t Imm) {
- uint64_t EncVal = 0;
- if (Imm & 0x80) EncVal |= 0x80000000ULL;
- if (Imm & 0x40) EncVal |= 0x3e000000ULL;
- else EncVal |= 0x40000000ULL;
- if (Imm & 0x20) EncVal |= 0x01000000ULL;
- if (Imm & 0x10) EncVal |= 0x00800000ULL;
- if (Imm & 0x08) EncVal |= 0x00400000ULL;
- if (Imm & 0x04) EncVal |= 0x00200000ULL;
- if (Imm & 0x02) EncVal |= 0x00100000ULL;
- if (Imm & 0x01) EncVal |= 0x00080000ULL;
- return (EncVal << 32) | EncVal;
-}
-
-// aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
-static inline bool isAdvSIMDModImmType12(uint64_t Imm) {
- uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
- return ((BString == 0xff || BString == 0x100) &&
- ((Imm & 0x0000ffffffffffffULL) == 0));
-}
-
-static inline uint8_t encodeAdvSIMDModImmType12(uint64_t Imm) {
- uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0;
- uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0;
- uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0;
- uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0;
- uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0;
- uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0;
- uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0;
- uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0;
-
- uint8_t EncVal = BitA;
- EncVal <<= 1;
- EncVal |= BitB;
- EncVal <<= 1;
- EncVal |= BitC;
- EncVal <<= 1;
- EncVal |= BitD;
- EncVal <<= 1;
- EncVal |= BitE;
- EncVal <<= 1;
- EncVal |= BitF;
- EncVal <<= 1;
- EncVal |= BitG;
- EncVal <<= 1;
- EncVal |= BitH;
- return EncVal;
-}
-
-static inline uint64_t decodeAdvSIMDModImmType12(uint8_t Imm) {
- uint64_t EncVal = 0;
- if (Imm & 0x80) EncVal |= 0x8000000000000000ULL;
- if (Imm & 0x40) EncVal |= 0x3fc0000000000000ULL;
- else EncVal |= 0x4000000000000000ULL;
- if (Imm & 0x20) EncVal |= 0x0020000000000000ULL;
- if (Imm & 0x10) EncVal |= 0x0010000000000000ULL;
- if (Imm & 0x08) EncVal |= 0x0008000000000000ULL;
- if (Imm & 0x04) EncVal |= 0x0004000000000000ULL;
- if (Imm & 0x02) EncVal |= 0x0002000000000000ULL;
- if (Imm & 0x01) EncVal |= 0x0001000000000000ULL;
- return (EncVal << 32) | EncVal;
-}
-
-} // end namespace ARM64_AM
-
-} // end namespace llvm
-
-#endif
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp (removed)
@@ -1,564 +0,0 @@
-//===-- ARM64AsmBackend.cpp - ARM64 Assembler Backend ---------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "ARM64.h"
-#include "ARM64RegisterInfo.h"
-#include "MCTargetDesc/ARM64FixupKinds.h"
-#include "llvm/ADT/Triple.h"
-#include "llvm/MC/MCAsmBackend.h"
-#include "llvm/MC/MCDirectives.h"
-#include "llvm/MC/MCFixupKindInfo.h"
-#include "llvm/MC/MCObjectWriter.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/MCSectionELF.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MachO.h"
-using namespace llvm;
-
-namespace {
-
-class ARM64AsmBackend : public MCAsmBackend {
- static const unsigned PCRelFlagVal =
- MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel;
-
-public:
- ARM64AsmBackend(const Target &T) : MCAsmBackend() {}
-
- unsigned getNumFixupKinds() const override {
- return ARM64::NumTargetFixupKinds;
- }
-
- const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
- const static MCFixupKindInfo Infos[ARM64::NumTargetFixupKinds] = {
- // This table *must* be in the order that the fixup_* kinds are defined in
- // ARM64FixupKinds.h.
- //
- // Name Offset (bits) Size (bits) Flags
- { "fixup_arm64_pcrel_adr_imm21", 0, 32, PCRelFlagVal },
- { "fixup_arm64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal },
- { "fixup_arm64_add_imm12", 10, 12, 0 },
- { "fixup_arm64_ldst_imm12_scale1", 10, 12, 0 },
- { "fixup_arm64_ldst_imm12_scale2", 10, 12, 0 },
- { "fixup_arm64_ldst_imm12_scale4", 10, 12, 0 },
- { "fixup_arm64_ldst_imm12_scale8", 10, 12, 0 },
- { "fixup_arm64_ldst_imm12_scale16", 10, 12, 0 },
- { "fixup_arm64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal },
- { "fixup_arm64_movw", 5, 16, 0 },
- { "fixup_arm64_pcrel_branch14", 5, 14, PCRelFlagVal },
- { "fixup_arm64_pcrel_branch19", 5, 19, PCRelFlagVal },
- { "fixup_arm64_pcrel_branch26", 0, 26, PCRelFlagVal },
- { "fixup_arm64_pcrel_call26", 0, 26, PCRelFlagVal },
- { "fixup_arm64_tlsdesc_call", 0, 0, 0 }
- };
-
- if (Kind < FirstTargetFixupKind)
- return MCAsmBackend::getFixupKindInfo(Kind);
-
- assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
- "Invalid kind!");
- return Infos[Kind - FirstTargetFixupKind];
- }
-
- void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
- uint64_t Value, bool IsPCRel) const override;
-
- bool mayNeedRelaxation(const MCInst &Inst) const override;
- bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
- const MCRelaxableFragment *DF,
- const MCAsmLayout &Layout) const override;
- void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
-
- void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
-
- unsigned getPointerSize() const { return 8; }
-};
-
-} // end anonymous namespace
-
-/// \brief The number of bytes the fixup may change.
-static unsigned getFixupKindNumBytes(unsigned Kind) {
- switch (Kind) {
- default:
- assert(0 && "Unknown fixup kind!");
-
- case ARM64::fixup_arm64_tlsdesc_call:
- return 0;
-
- case FK_Data_1:
- return 1;
-
- case FK_Data_2:
- case ARM64::fixup_arm64_movw:
- return 2;
-
- case ARM64::fixup_arm64_pcrel_branch14:
- case ARM64::fixup_arm64_add_imm12:
- case ARM64::fixup_arm64_ldst_imm12_scale1:
- case ARM64::fixup_arm64_ldst_imm12_scale2:
- case ARM64::fixup_arm64_ldst_imm12_scale4:
- case ARM64::fixup_arm64_ldst_imm12_scale8:
- case ARM64::fixup_arm64_ldst_imm12_scale16:
- case ARM64::fixup_arm64_ldr_pcrel_imm19:
- case ARM64::fixup_arm64_pcrel_branch19:
- return 3;
-
- case ARM64::fixup_arm64_pcrel_adr_imm21:
- case ARM64::fixup_arm64_pcrel_adrp_imm21:
- case ARM64::fixup_arm64_pcrel_branch26:
- case ARM64::fixup_arm64_pcrel_call26:
- case FK_Data_4:
- return 4;
-
- case FK_Data_8:
- return 8;
- }
-}
-
-static unsigned AdrImmBits(unsigned Value) {
- unsigned lo2 = Value & 0x3;
- unsigned hi19 = (Value & 0x1ffffc) >> 2;
- return (hi19 << 5) | (lo2 << 29);
-}
-
-static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
- int64_t SignedValue = static_cast<int64_t>(Value);
- switch (Kind) {
- default:
- assert(false && "Unknown fixup kind!");
- case ARM64::fixup_arm64_pcrel_adr_imm21:
- if (SignedValue > 2097151 || SignedValue < -2097152)
- report_fatal_error("fixup value out of range");
- return AdrImmBits(Value & 0x1fffffULL);
- case ARM64::fixup_arm64_pcrel_adrp_imm21:
- return AdrImmBits((Value & 0x1fffff000ULL) >> 12);
- case ARM64::fixup_arm64_ldr_pcrel_imm19:
- case ARM64::fixup_arm64_pcrel_branch19:
- // Signed 21-bit immediate
- if (SignedValue > 2097151 || SignedValue < -2097152)
- report_fatal_error("fixup value out of range");
- // Low two bits are not encoded.
- return (Value >> 2) & 0x7ffff;
- case ARM64::fixup_arm64_add_imm12:
- case ARM64::fixup_arm64_ldst_imm12_scale1:
- // Unsigned 12-bit immediate
- if (Value >= 0x1000)
- report_fatal_error("invalid imm12 fixup value");
- return Value;
- case ARM64::fixup_arm64_ldst_imm12_scale2:
- // Unsigned 12-bit immediate which gets multiplied by 2
- if (Value & 1 || Value >= 0x2000)
- report_fatal_error("invalid imm12 fixup value");
- return Value >> 1;
- case ARM64::fixup_arm64_ldst_imm12_scale4:
- // Unsigned 12-bit immediate which gets multiplied by 4
- if (Value & 3 || Value >= 0x4000)
- report_fatal_error("invalid imm12 fixup value");
- return Value >> 2;
- case ARM64::fixup_arm64_ldst_imm12_scale8:
- // Unsigned 12-bit immediate which gets multiplied by 8
- if (Value & 7 || Value >= 0x8000)
- report_fatal_error("invalid imm12 fixup value");
- return Value >> 3;
- case ARM64::fixup_arm64_ldst_imm12_scale16:
- // Unsigned 12-bit immediate which gets multiplied by 16
- if (Value & 15 || Value >= 0x10000)
- report_fatal_error("invalid imm12 fixup value");
- return Value >> 4;
- case ARM64::fixup_arm64_movw:
- report_fatal_error("no resolvable MOVZ/MOVK fixups supported yet");
- return Value;
- case ARM64::fixup_arm64_pcrel_branch14:
- // Signed 16-bit immediate
- if (SignedValue > 32767 || SignedValue < -32768)
- report_fatal_error("fixup value out of range");
- // Low two bits are not encoded (4-byte alignment assumed).
- if (Value & 0x3)
- report_fatal_error("fixup not sufficiently aligned");
- return (Value >> 2) & 0x3fff;
- case ARM64::fixup_arm64_pcrel_branch26:
- case ARM64::fixup_arm64_pcrel_call26:
- // Signed 28-bit immediate
- if (SignedValue > 134217727 || SignedValue < -134217728)
- report_fatal_error("fixup value out of range");
- // Low two bits are not encoded (4-byte alignment assumed).
- if (Value & 0x3)
- report_fatal_error("fixup not sufficiently aligned");
- return (Value >> 2) & 0x3ffffff;
- case FK_Data_1:
- case FK_Data_2:
- case FK_Data_4:
- case FK_Data_8:
- return Value;
- }
-}
-
-void ARM64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
- unsigned DataSize, uint64_t Value,
- bool IsPCRel) const {
- unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
- if (!Value)
- return; // Doesn't change encoding.
- MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
- // Apply any target-specific value adjustments.
- Value = adjustFixupValue(Fixup.getKind(), Value);
-
- // Shift the value into position.
- Value <<= Info.TargetOffset;
-
- unsigned Offset = Fixup.getOffset();
- assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
-
- // For each byte of the fragment that the fixup touches, mask in the
- // bits from the fixup value.
- for (unsigned i = 0; i != NumBytes; ++i)
- Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
-}
-
-bool ARM64AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
- return false;
-}
-
-bool ARM64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
- const MCRelaxableFragment *DF,
- const MCAsmLayout &Layout) const {
- // FIXME: This isn't correct for ARM64. Just moving the "generic" logic
- // into the targets for now.
- //
- // Relax if the value is too big for a (signed) i8.
- return int64_t(Value) != int64_t(int8_t(Value));
-}
-
-void ARM64AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
- assert(false && "ARM64AsmBackend::relaxInstruction() unimplemented");
-}
-
-bool ARM64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
- // If the count is not 4-byte aligned, we must be writing data into the text
- // section (otherwise we have unaligned instructions, and thus have far
- // bigger problems), so just write zeros instead.
- if ((Count & 3) != 0) {
- for (uint64_t i = 0, e = (Count & 3); i != e; ++i)
- OW->Write8(0);
- }
-
- // We are properly aligned, so write NOPs as requested.
- Count /= 4;
- for (uint64_t i = 0; i != Count; ++i)
- OW->Write32(0xd503201f);
- return true;
-}
-
-namespace {
-
-namespace CU {
-
-/// \brief Compact unwind encoding values.
-enum CompactUnwindEncodings {
- /// \brief A "frameless" leaf function, where no non-volatile registers are
- /// saved. The return remains in LR throughout the function.
- UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,
-
- /// \brief No compact unwind encoding available. Instead the low 23-bits of
- /// the compact unwind encoding is the offset of the DWARF FDE in the
- /// __eh_frame section. This mode is never used in object files. It is only
- /// generated by the linker in final linked images, which have only DWARF info
- /// for a function.
- UNWIND_ARM64_MODE_DWARF = 0x03000000,
-
- /// \brief This is a standard arm64 prologue where FP/LR are immediately
- /// pushed on the stack, then SP is copied to FP. If there are any
- /// non-volatile register saved, they are copied into the stack fame in pairs
- /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the
- /// five X pairs and four D pairs can be saved, but the memory layout must be
- /// in register number order.
- UNWIND_ARM64_MODE_FRAME = 0x04000000,
-
- /// \brief Frame register pair encodings.
- UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,
- UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,
- UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,
- UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,
- UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,
- UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,
- UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,
- UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
- UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
-};
-
-} // end CU namespace
-
-// FIXME: This should be in a separate file.
-class DarwinARM64AsmBackend : public ARM64AsmBackend {
- const MCRegisterInfo &MRI;
-
- /// \brief Encode compact unwind stack adjustment for frameless functions.
- /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
- /// The stack size always needs to be 16 byte aligned.
- uint32_t encodeStackAdjustment(uint32_t StackSize) const {
- return (StackSize / 16) << 12;
- }
-
-public:
- DarwinARM64AsmBackend(const Target &T, const MCRegisterInfo &MRI)
- : ARM64AsmBackend(T), MRI(MRI) {}
-
- MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
- return createARM64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64,
- MachO::CPU_SUBTYPE_ARM64_ALL);
- }
-
- bool doesSectionRequireSymbols(const MCSection &Section) const override {
- // Any section for which the linker breaks things into atoms needs to
- // preserve symbols, including assembler local symbols, to identify
- // those atoms. These sections are:
- // Sections of type:
- //
- // S_CSTRING_LITERALS (e.g. __cstring)
- // S_LITERAL_POINTERS (e.g. objc selector pointers)
- // S_16BYTE_LITERALS, S_8BYTE_LITERALS, S_4BYTE_LITERALS
- //
- // Sections named:
- //
- // __TEXT,__eh_frame
- // __TEXT,__ustring
- // __DATA,__cfstring
- // __DATA,__objc_classrefs
- // __DATA,__objc_catlist
- //
- // FIXME: It would be better if the compiler used actual linker local
- // symbols for each of these sections rather than preserving what
- // are ostensibly assembler local symbols.
- const MCSectionMachO &SMO = static_cast<const MCSectionMachO &>(Section);
- return (SMO.getType() == MachO::S_CSTRING_LITERALS ||
- SMO.getType() == MachO::S_4BYTE_LITERALS ||
- SMO.getType() == MachO::S_8BYTE_LITERALS ||
- SMO.getType() == MachO::S_16BYTE_LITERALS ||
- SMO.getType() == MachO::S_LITERAL_POINTERS ||
- (SMO.getSegmentName() == "__TEXT" &&
- (SMO.getSectionName() == "__eh_frame" ||
- SMO.getSectionName() == "__ustring")) ||
- (SMO.getSegmentName() == "__DATA" &&
- (SMO.getSectionName() == "__cfstring" ||
- SMO.getSectionName() == "__objc_classrefs" ||
- SMO.getSectionName() == "__objc_catlist")));
- }
-
- /// \brief Generate the compact unwind encoding from the CFI directives.
- uint32_t generateCompactUnwindEncoding(
- ArrayRef<MCCFIInstruction> Instrs) const override {
- if (Instrs.empty())
- return CU::UNWIND_ARM64_MODE_FRAMELESS;
-
- bool HasFP = false;
- unsigned StackSize = 0;
-
- uint32_t CompactUnwindEncoding = 0;
- for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
- const MCCFIInstruction &Inst = Instrs[i];
-
- switch (Inst.getOperation()) {
- default:
- // Cannot handle this directive: bail out.
- return CU::UNWIND_ARM64_MODE_DWARF;
- case MCCFIInstruction::OpDefCfa: {
- // Defines a frame pointer.
- assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) ==
- ARM64::FP &&
- "Invalid frame pointer!");
- assert(i + 2 < e && "Insufficient CFI instructions to define a frame!");
-
- const MCCFIInstruction &LRPush = Instrs[++i];
- assert(LRPush.getOperation() == MCCFIInstruction::OpOffset &&
- "Link register not pushed!");
- const MCCFIInstruction &FPPush = Instrs[++i];
- assert(FPPush.getOperation() == MCCFIInstruction::OpOffset &&
- "Frame pointer not pushed!");
-
- unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
- unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
-
- LRReg = getXRegFromWReg(LRReg);
- FPReg = getXRegFromWReg(FPReg);
-
- assert(LRReg == ARM64::LR && FPReg == ARM64::FP &&
- "Pushing invalid registers for frame!");
-
- // Indicate that the function has a frame.
- CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
- HasFP = true;
- break;
- }
- case MCCFIInstruction::OpDefCfaOffset: {
- assert(StackSize == 0 && "We already have the CFA offset!");
- StackSize = std::abs(Inst.getOffset());
- break;
- }
- case MCCFIInstruction::OpOffset: {
- // Registers are saved in pairs. We expect there to be two consecutive
- // `.cfi_offset' instructions with the appropriate registers specified.
- unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
- if (i + 1 == e)
- return CU::UNWIND_ARM64_MODE_DWARF;
-
- const MCCFIInstruction &Inst2 = Instrs[++i];
- if (Inst2.getOperation() != MCCFIInstruction::OpOffset)
- return CU::UNWIND_ARM64_MODE_DWARF;
- unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
-
- // N.B. The encodings must be in register number order, and the X
- // registers before the D registers.
-
- // X19/X20 pair = 0x00000001,
- // X21/X22 pair = 0x00000002,
- // X23/X24 pair = 0x00000004,
- // X25/X26 pair = 0x00000008,
- // X27/X28 pair = 0x00000010
- Reg1 = getXRegFromWReg(Reg1);
- Reg2 = getXRegFromWReg(Reg2);
-
- if (Reg1 == ARM64::X19 && Reg2 == ARM64::X20 &&
- (CompactUnwindEncoding & 0xF1E) == 0)
- CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;
- else if (Reg1 == ARM64::X21 && Reg2 == ARM64::X22 &&
- (CompactUnwindEncoding & 0xF1C) == 0)
- CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;
- else if (Reg1 == ARM64::X23 && Reg2 == ARM64::X24 &&
- (CompactUnwindEncoding & 0xF18) == 0)
- CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;
- else if (Reg1 == ARM64::X25 && Reg2 == ARM64::X26 &&
- (CompactUnwindEncoding & 0xF10) == 0)
- CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;
- else if (Reg1 == ARM64::X27 && Reg2 == ARM64::X28 &&
- (CompactUnwindEncoding & 0xF00) == 0)
- CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;
- else {
- Reg1 = getDRegFromBReg(Reg1);
- Reg2 = getDRegFromBReg(Reg2);
-
- // D8/D9 pair = 0x00000100,
- // D10/D11 pair = 0x00000200,
- // D12/D13 pair = 0x00000400,
- // D14/D15 pair = 0x00000800
- if (Reg1 == ARM64::D8 && Reg2 == ARM64::D9 &&
- (CompactUnwindEncoding & 0xE00) == 0)
- CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;
- else if (Reg1 == ARM64::D10 && Reg2 == ARM64::D11 &&
- (CompactUnwindEncoding & 0xC00) == 0)
- CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;
- else if (Reg1 == ARM64::D12 && Reg2 == ARM64::D13 &&
- (CompactUnwindEncoding & 0x800) == 0)
- CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;
- else if (Reg1 == ARM64::D14 && Reg2 == ARM64::D15)
- CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;
- else
- // A pair was pushed which we cannot handle.
- return CU::UNWIND_ARM64_MODE_DWARF;
- }
-
- break;
- }
- }
- }
-
- if (!HasFP) {
- // With compact unwind info we can only represent stack adjustments of up
- // to 65520 bytes.
- if (StackSize > 65520)
- return CU::UNWIND_ARM64_MODE_DWARF;
-
- CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;
- CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
- }
-
- return CompactUnwindEncoding;
- }
-};
-
-} // end anonymous namespace
-
-namespace {
-
-class ELFARM64AsmBackend : public ARM64AsmBackend {
-public:
- uint8_t OSABI;
- bool IsLittleEndian;
-
- ELFARM64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian)
- : ARM64AsmBackend(T), OSABI(OSABI), IsLittleEndian(IsLittleEndian) {}
-
- MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
- return createARM64ELFObjectWriter(OS, OSABI, IsLittleEndian);
- }
-
- void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
- const MCFixup &Fixup, const MCFragment *DF,
- const MCValue &Target, uint64_t &Value,
- bool &IsResolved) override;
-
- void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
- uint64_t Value, bool IsPCRel) const override;
-};
-
-void ELFARM64AsmBackend::processFixupValue(const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFixup &Fixup,
- const MCFragment *DF,
- const MCValue &Target,
- uint64_t &Value, bool &IsResolved) {
- // The ADRP instruction adds some multiple of 0x1000 to the current PC &
- // ~0xfff. This means that the required offset to reach a symbol can vary by
- // up to one step depending on where the ADRP is in memory. For example:
- //
- // ADRP x0, there
- // there:
- //
- // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
- // we'll need that as an offset. At any other address "there" will be in the
- // same page as the ADRP and the instruction should encode 0x0. Assuming the
- // section isn't 0x1000-aligned, we therefore need to delegate this decision
- // to the linker -- a relocation!
- if ((uint32_t)Fixup.getKind() == ARM64::fixup_arm64_pcrel_adrp_imm21)
- IsResolved = false;
-}
-
-void ELFARM64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
- unsigned DataSize, uint64_t Value,
- bool IsPCRel) const {
- // store fixups in .eh_frame section in big endian order
- if (!IsLittleEndian && Fixup.getKind() == FK_Data_4) {
- const MCSection *Sec = Fixup.getValue()->FindAssociatedSection();
- const MCSectionELF *SecELF = static_cast<const MCSectionELF *>(Sec);
- if (SecELF->getSectionName() == ".eh_frame")
- Value = ByteSwap_32(unsigned(Value));
- }
- ARM64AsmBackend::applyFixup (Fixup, Data, DataSize, Value, IsPCRel);
-}
-}
-
-MCAsmBackend *llvm::createARM64leAsmBackend(const Target &T,
- const MCRegisterInfo &MRI,
- StringRef TT, StringRef CPU) {
- Triple TheTriple(TT);
-
- if (TheTriple.isOSDarwin())
- return new DarwinARM64AsmBackend(T, MRI);
-
- assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target");
- return new ELFARM64AsmBackend(T, TheTriple.getOS(), /*IsLittleEndian=*/true);
-}
-
-MCAsmBackend *llvm::createARM64beAsmBackend(const Target &T,
- const MCRegisterInfo &MRI,
- StringRef TT, StringRef CPU) {
- Triple TheTriple(TT);
-
- assert(TheTriple.isOSBinFormatELF() && "Big endian is only supported for ELF targets!");
- return new ELFARM64AsmBackend(T, TheTriple.getOS(), /*IsLittleEndian=*/false);
-}
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp (removed)
@@ -1,255 +0,0 @@
-//===-- ARM64ELFObjectWriter.cpp - ARM64 ELF Writer -----------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file handles ELF-specific object emission, converting LLVM's internal
-// fixups into the appropriate relocations.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCTargetDesc/ARM64FixupKinds.h"
-#include "MCTargetDesc/ARM64MCExpr.h"
-#include "MCTargetDesc/ARM64MCTargetDesc.h"
-#include "llvm/MC/MCELFObjectWriter.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/Support/ErrorHandling.h"
-
-using namespace llvm;
-
-namespace {
-class ARM64ELFObjectWriter : public MCELFObjectTargetWriter {
-public:
- ARM64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian);
-
- virtual ~ARM64ELFObjectWriter();
-
-protected:
- unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
- bool IsPCRel) const override;
-
-private:
-};
-}
-
-ARM64ELFObjectWriter::ARM64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian)
- : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
- /*HasRelocationAddend*/ true) {}
-
-ARM64ELFObjectWriter::~ARM64ELFObjectWriter() {}
-
-unsigned ARM64ELFObjectWriter::GetRelocType(const MCValue &Target,
- const MCFixup &Fixup,
- bool IsPCRel) const {
- ARM64MCExpr::VariantKind RefKind =
- static_cast<ARM64MCExpr::VariantKind>(Target.getRefKind());
- ARM64MCExpr::VariantKind SymLoc = ARM64MCExpr::getSymbolLoc(RefKind);
- bool IsNC = ARM64MCExpr::isNotChecked(RefKind);
-
- assert((!Target.getSymA() ||
- Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
- "Should only be expression-level modifiers here");
-
- assert((!Target.getSymB() ||
- Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
- "Should only be expression-level modifiers here");
-
- if (IsPCRel) {
- switch ((unsigned)Fixup.getKind()) {
- case FK_Data_2:
- return ELF::R_AARCH64_PREL16;
- case FK_Data_4:
- return ELF::R_AARCH64_PREL32;
- case FK_Data_8:
- return ELF::R_AARCH64_PREL64;
- case ARM64::fixup_arm64_pcrel_adr_imm21:
- assert(SymLoc == ARM64MCExpr::VK_NONE && "unexpected ADR relocation");
- return ELF::R_AARCH64_ADR_PREL_LO21;
- case ARM64::fixup_arm64_pcrel_adrp_imm21:
- if (SymLoc == ARM64MCExpr::VK_ABS && !IsNC)
- return ELF::R_AARCH64_ADR_PREL_PG_HI21;
- if (SymLoc == ARM64MCExpr::VK_GOT && !IsNC)
- return ELF::R_AARCH64_ADR_GOT_PAGE;
- if (SymLoc == ARM64MCExpr::VK_GOTTPREL && !IsNC)
- return ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21;
- if (SymLoc == ARM64MCExpr::VK_TLSDESC && !IsNC)
- return ELF::R_AARCH64_TLSDESC_ADR_PAGE;
- llvm_unreachable("invalid symbol kind for ADRP relocation");
- case ARM64::fixup_arm64_pcrel_branch26:
- return ELF::R_AARCH64_JUMP26;
- case ARM64::fixup_arm64_pcrel_call26:
- return ELF::R_AARCH64_CALL26;
- case ARM64::fixup_arm64_ldr_pcrel_imm19:
- if (SymLoc == ARM64MCExpr::VK_GOTTPREL)
- return ELF::R_AARCH64_TLSIE_LD_GOTTPREL_PREL19;
- return ELF::R_AARCH64_LD_PREL_LO19;
- case ARM64::fixup_arm64_pcrel_branch14:
- return ELF::R_AARCH64_TSTBR14;
- case ARM64::fixup_arm64_pcrel_branch19:
- return ELF::R_AARCH64_CONDBR19;
- default:
- llvm_unreachable("Unsupported pc-relative fixup kind");
- }
- } else {
- switch ((unsigned)Fixup.getKind()) {
- case FK_Data_2:
- return ELF::R_AARCH64_ABS16;
- case FK_Data_4:
- return ELF::R_AARCH64_ABS32;
- case FK_Data_8:
- return ELF::R_AARCH64_ABS64;
- case ARM64::fixup_arm64_add_imm12:
- if (RefKind == ARM64MCExpr::VK_DTPREL_HI12)
- return ELF::R_AARCH64_TLSLD_ADD_DTPREL_HI12;
- if (RefKind == ARM64MCExpr::VK_TPREL_HI12)
- return ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12;
- if (RefKind == ARM64MCExpr::VK_DTPREL_LO12_NC)
- return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC;
- if (RefKind == ARM64MCExpr::VK_DTPREL_LO12)
- return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12;
- if (RefKind == ARM64MCExpr::VK_TPREL_LO12_NC)
- return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC;
- if (RefKind == ARM64MCExpr::VK_TPREL_LO12)
- return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12;
- if (RefKind == ARM64MCExpr::VK_TLSDESC_LO12)
- return ELF::R_AARCH64_TLSDESC_ADD_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
- return ELF::R_AARCH64_ADD_ABS_LO12_NC;
-
- report_fatal_error("invalid fixup for add (uimm12) instruction");
- return 0;
- case ARM64::fixup_arm64_ldst_imm12_scale1:
- if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
- return ELF::R_AARCH64_LDST8_ABS_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
- return ELF::R_AARCH64_TLSLD_LDST8_DTPREL_LO12;
- if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
- return ELF::R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
- return ELF::R_AARCH64_TLSLE_LDST8_TPREL_LO12;
- if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
- return ELF::R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC;
-
- report_fatal_error("invalid fixup for 8-bit load/store instruction");
- return 0;
- case ARM64::fixup_arm64_ldst_imm12_scale2:
- if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
- return ELF::R_AARCH64_LDST16_ABS_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
- return ELF::R_AARCH64_TLSLD_LDST16_DTPREL_LO12;
- if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
- return ELF::R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
- return ELF::R_AARCH64_TLSLE_LDST16_TPREL_LO12;
- if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
- return ELF::R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC;
-
- report_fatal_error("invalid fixup for 16-bit load/store instruction");
- return 0;
- case ARM64::fixup_arm64_ldst_imm12_scale4:
- if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
- return ELF::R_AARCH64_LDST32_ABS_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
- return ELF::R_AARCH64_TLSLD_LDST32_DTPREL_LO12;
- if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
- return ELF::R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
- return ELF::R_AARCH64_TLSLE_LDST32_TPREL_LO12;
- if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
- return ELF::R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC;
-
- report_fatal_error("invalid fixup for 32-bit load/store instruction");
- return 0;
- case ARM64::fixup_arm64_ldst_imm12_scale8:
- if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
- return ELF::R_AARCH64_LDST64_ABS_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_GOT && IsNC)
- return ELF::R_AARCH64_LD64_GOT_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
- return ELF::R_AARCH64_TLSLD_LDST64_DTPREL_LO12;
- if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
- return ELF::R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
- return ELF::R_AARCH64_TLSLE_LDST64_TPREL_LO12;
- if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
- return ELF::R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_GOTTPREL && IsNC)
- return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
- if (SymLoc == ARM64MCExpr::VK_TLSDESC && IsNC)
- return ELF::R_AARCH64_TLSDESC_LD64_LO12_NC;
-
- report_fatal_error("invalid fixup for 64-bit load/store instruction");
- return 0;
- case ARM64::fixup_arm64_ldst_imm12_scale16:
- if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
- return ELF::R_AARCH64_LDST128_ABS_LO12_NC;
-
- report_fatal_error("invalid fixup for 128-bit load/store instruction");
- return 0;
- case ARM64::fixup_arm64_movw:
- if (RefKind == ARM64MCExpr::VK_ABS_G3)
- return ELF::R_AARCH64_MOVW_UABS_G3;
- if (RefKind == ARM64MCExpr::VK_ABS_G2)
- return ELF::R_AARCH64_MOVW_UABS_G2;
- if (RefKind == ARM64MCExpr::VK_ABS_G2_S)
- return ELF::R_AARCH64_MOVW_SABS_G2;
- if (RefKind == ARM64MCExpr::VK_ABS_G2_NC)
- return ELF::R_AARCH64_MOVW_UABS_G2_NC;
- if (RefKind == ARM64MCExpr::VK_ABS_G1)
- return ELF::R_AARCH64_MOVW_UABS_G1;
- if (RefKind == ARM64MCExpr::VK_ABS_G1_S)
- return ELF::R_AARCH64_MOVW_SABS_G1;
- if (RefKind == ARM64MCExpr::VK_ABS_G1_NC)
- return ELF::R_AARCH64_MOVW_UABS_G1_NC;
- if (RefKind == ARM64MCExpr::VK_ABS_G0)
- return ELF::R_AARCH64_MOVW_UABS_G0;
- if (RefKind == ARM64MCExpr::VK_ABS_G0_S)
- return ELF::R_AARCH64_MOVW_SABS_G0;
- if (RefKind == ARM64MCExpr::VK_ABS_G0_NC)
- return ELF::R_AARCH64_MOVW_UABS_G0_NC;
- if (RefKind == ARM64MCExpr::VK_DTPREL_G2)
- return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
- if (RefKind == ARM64MCExpr::VK_DTPREL_G1)
- return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1;
- if (RefKind == ARM64MCExpr::VK_DTPREL_G1_NC)
- return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
- if (RefKind == ARM64MCExpr::VK_DTPREL_G0)
- return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G0;
- if (RefKind == ARM64MCExpr::VK_DTPREL_G0_NC)
- return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC;
- if (RefKind == ARM64MCExpr::VK_TPREL_G2)
- return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
- if (RefKind == ARM64MCExpr::VK_TPREL_G1)
- return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1;
- if (RefKind == ARM64MCExpr::VK_TPREL_G1_NC)
- return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
- if (RefKind == ARM64MCExpr::VK_TPREL_G0)
- return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0;
- if (RefKind == ARM64MCExpr::VK_TPREL_G0_NC)
- return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC;
- if (RefKind == ARM64MCExpr::VK_GOTTPREL_G1)
- return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
- if (RefKind == ARM64MCExpr::VK_GOTTPREL_G0_NC)
- return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
- report_fatal_error("invalid fixup for movz/movk instruction");
- return 0;
- case ARM64::fixup_arm64_tlsdesc_call:
- return ELF::R_AARCH64_TLSDESC_CALL;
- default:
- llvm_unreachable("Unknown ELF relocation type");
- }
- }
-
- llvm_unreachable("Unimplemented fixup -> relocation");
-}
-
-MCObjectWriter *llvm::createARM64ELFObjectWriter(raw_ostream &OS,
- uint8_t OSABI,
- bool IsLittleEndian) {
- MCELFObjectTargetWriter *MOTW = new ARM64ELFObjectWriter(OSABI, IsLittleEndian);
- return createELFObjectWriter(MOTW, OS, IsLittleEndian);
-}
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp (removed)
@@ -1,160 +0,0 @@
-//===- lib/MC/ARM64ELFStreamer.cpp - ELF Object Output for ARM64 ----------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file assembles .s files and emits AArch64 ELF .o object files. Different
-// from generic ELF streamer in emitting mapping symbols ($x and $d) to delimit
-// regions of data and code.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/MC/MCELFStreamer.h"
-#include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/MC/MCAsmBackend.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCELF.h"
-#include "llvm/MC/MCELFStreamer.h"
-#include "llvm/MC/MCELFSymbolFlags.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCObjectStreamer.h"
-#include "llvm/MC/MCSection.h"
-#include "llvm/MC/MCSectionELF.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ELF.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-
-using namespace llvm;
-
-namespace {
-
-/// Extend the generic ELFStreamer class so that it can emit mapping symbols at
-/// the appropriate points in the object files. These symbols are defined in the
-/// AArch64 ELF ABI:
-/// infocenter.arm.com/help/topic/com.arm.doc.ihi0056a/IHI0056A_aaelf64.pdf
-///
-/// In brief: $x or $d should be emitted at the start of each contiguous region
-/// of A64 code or data in a section. In practice, this emission does not rely
-/// on explicit assembler directives but on inherent properties of the
-/// directives doing the emission (e.g. ".byte" is data, "add x0, x0, x0" an
-/// instruction).
-///
-/// As a result this system is orthogonal to the DataRegion infrastructure used
-/// by MachO. Beware!
-class ARM64ELFStreamer : public MCELFStreamer {
-public:
- ARM64ELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS,
- MCCodeEmitter *Emitter)
- : MCELFStreamer(Context, TAB, OS, Emitter), MappingSymbolCounter(0),
- LastEMS(EMS_None) {}
-
- ~ARM64ELFStreamer() {}
-
- void ChangeSection(const MCSection *Section,
- const MCExpr *Subsection) override {
- // We have to keep track of the mapping symbol state of any sections we
- // use. Each one should start off as EMS_None, which is provided as the
- // default constructor by DenseMap::lookup.
- LastMappingSymbols[getPreviousSection().first] = LastEMS;
- LastEMS = LastMappingSymbols.lookup(Section);
-
- MCELFStreamer::ChangeSection(Section, Subsection);
- }
-
- /// This function is the one used to emit instruction data into the ELF
- /// streamer. We override it to add the appropriate mapping symbol if
- /// necessary.
- void EmitInstruction(const MCInst &Inst,
- const MCSubtargetInfo &STI) override {
- EmitA64MappingSymbol();
- MCELFStreamer::EmitInstruction(Inst, STI);
- }
-
- /// This is one of the functions used to emit data into an ELF section, so the
- /// ARM64 streamer overrides it to add the appropriate mapping symbol ($d)
- /// if necessary.
- void EmitBytes(StringRef Data) override {
- EmitDataMappingSymbol();
- MCELFStreamer::EmitBytes(Data);
- }
-
- /// This is one of the functions used to emit data into an ELF section, so the
- /// ARM64 streamer overrides it to add the appropriate mapping symbol ($d)
- /// if necessary.
- void EmitValueImpl(const MCExpr *Value, unsigned Size,
- const SMLoc &Loc) override {
- EmitDataMappingSymbol();
- MCELFStreamer::EmitValueImpl(Value, Size);
- }
-
-private:
- enum ElfMappingSymbol {
- EMS_None,
- EMS_A64,
- EMS_Data
- };
-
- void EmitDataMappingSymbol() {
- if (LastEMS == EMS_Data)
- return;
- EmitMappingSymbol("$d");
- LastEMS = EMS_Data;
- }
-
- void EmitA64MappingSymbol() {
- if (LastEMS == EMS_A64)
- return;
- EmitMappingSymbol("$x");
- LastEMS = EMS_A64;
- }
-
- void EmitMappingSymbol(StringRef Name) {
- MCSymbol *Start = getContext().CreateTempSymbol();
- EmitLabel(Start);
-
- MCSymbol *Symbol = getContext().GetOrCreateSymbol(
- Name + "." + Twine(MappingSymbolCounter++));
-
- MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol);
- MCELF::SetType(SD, ELF::STT_NOTYPE);
- MCELF::SetBinding(SD, ELF::STB_LOCAL);
- SD.setExternal(false);
- Symbol->setSection(*getCurrentSection().first);
-
- const MCExpr *Value = MCSymbolRefExpr::Create(Start, getContext());
- Symbol->setVariableValue(Value);
- }
-
- int64_t MappingSymbolCounter;
-
- DenseMap<const MCSection *, ElfMappingSymbol> LastMappingSymbols;
- ElfMappingSymbol LastEMS;
-
- /// @}
-};
-}
-
-namespace llvm {
-MCELFStreamer *createARM64ELFStreamer(MCContext &Context, MCAsmBackend &TAB,
- raw_ostream &OS, MCCodeEmitter *Emitter,
- bool RelaxAll, bool NoExecStack) {
- ARM64ELFStreamer *S = new ARM64ELFStreamer(Context, TAB, OS, Emitter);
- if (RelaxAll)
- S->getAssembler().setRelaxAll(true);
- if (NoExecStack)
- S->getAssembler().setNoExecStack(true);
- return S;
-}
-}
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.h (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.h (removed)
@@ -1,26 +0,0 @@
-//===-- ARM64ELFStreamer.h - ELF Streamer for ARM64 -------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements ELF streamer information for the ARM64 backend.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_AARCH64_ELF_STREAMER_H
-#define LLVM_AARCH64_ELF_STREAMER_H
-
-#include "llvm/MC/MCELFStreamer.h"
-
-namespace llvm {
-
-MCELFStreamer *createARM64ELFStreamer(MCContext &Context, MCAsmBackend &TAB,
- raw_ostream &OS, MCCodeEmitter *Emitter,
- bool RelaxAll, bool NoExecStack);
-}
-
-#endif // ARM64_ELF_STREAMER_H
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64FixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64FixupKinds.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64FixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64FixupKinds.h (removed)
@@ -1,76 +0,0 @@
-//===-- ARM64FixupKinds.h - ARM64 Specific Fixup Entries --------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_ARM64FIXUPKINDS_H
-#define LLVM_ARM64FIXUPKINDS_H
-
-#include "llvm/MC/MCFixup.h"
-
-namespace llvm {
-namespace ARM64 {
-
-enum Fixups {
- // fixup_arm64_pcrel_adr_imm21 - A 21-bit pc-relative immediate inserted into
- // an ADR instruction.
- fixup_arm64_pcrel_adr_imm21 = FirstTargetFixupKind,
-
- // fixup_arm64_pcrel_adrp_imm21 - A 21-bit pc-relative immediate inserted into
- // an ADRP instruction.
- fixup_arm64_pcrel_adrp_imm21,
-
- // fixup_arm64_imm12 - 12-bit fixup for add/sub instructions.
- // No alignment adjustment. All value bits are encoded.
- fixup_arm64_add_imm12,
-
- // fixup_arm64_ldst_imm12_* - unsigned 12-bit fixups for load and
- // store instructions.
- fixup_arm64_ldst_imm12_scale1,
- fixup_arm64_ldst_imm12_scale2,
- fixup_arm64_ldst_imm12_scale4,
- fixup_arm64_ldst_imm12_scale8,
- fixup_arm64_ldst_imm12_scale16,
-
- // fixup_arm64_ldr_pcrel_imm19 - The high 19 bits of a 21-bit pc-relative
- // immediate. Same encoding as fixup_arm64_pcrel_adrhi, except this is used by
- // pc-relative loads and generates relocations directly when necessary.
- fixup_arm64_ldr_pcrel_imm19,
-
- // FIXME: comment
- fixup_arm64_movw,
-
- // fixup_arm64_pcrel_imm14 - The high 14 bits of a 21-bit pc-relative
- // immediate.
- fixup_arm64_pcrel_branch14,
-
- // fixup_arm64_pcrel_branch19 - The high 19 bits of a 21-bit pc-relative
- // immediate. Same encoding as fixup_arm64_pcrel_adrhi, except this is use by
- // b.cc and generates relocations directly when necessary.
- fixup_arm64_pcrel_branch19,
-
- // fixup_arm64_pcrel_branch26 - The high 26 bits of a 28-bit pc-relative
- // immediate.
- fixup_arm64_pcrel_branch26,
-
- // fixup_arm64_pcrel_call26 - The high 26 bits of a 28-bit pc-relative
- // immediate. Distinguished from branch26 only on ELF.
- fixup_arm64_pcrel_call26,
-
- // fixup_arm64_tlsdesc_call - zero-space placeholder for the ELF
- // R_AARCH64_TLSDESC_CALL relocation.
- fixup_arm64_tlsdesc_call,
-
- // Marker
- LastTargetFixupKind,
- NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
-};
-
-} // end namespace ARM64
-} // end namespace llvm
-
-#endif
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.cpp (removed)
@@ -1,99 +0,0 @@
-//===-- ARM64MCAsmInfo.cpp - ARM64 asm properties -----------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the declarations of the ARM64MCAsmInfo properties.
-//
-//===----------------------------------------------------------------------===//
-
-#include "ARM64MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/Support/CommandLine.h"
-using namespace llvm;
-
-enum AsmWriterVariantTy {
- Default = -1,
- Generic = 0,
- Apple = 1
-};
-
-static cl::opt<AsmWriterVariantTy> AsmWriterVariant(
- "arm64-neon-syntax", cl::init(Default),
- cl::desc("Choose style of NEON code to emit from ARM64 backend:"),
- cl::values(clEnumValN(Generic, "generic", "Emit generic NEON assembly"),
- clEnumValN(Apple, "apple", "Emit Apple-style NEON assembly"),
- clEnumValEnd));
-
-ARM64MCAsmInfoDarwin::ARM64MCAsmInfoDarwin() {
- // We prefer NEON instructions to be printed in the short form.
- AssemblerDialect = AsmWriterVariant == Default ? 1 : AsmWriterVariant;
-
- PrivateGlobalPrefix = "L";
- SeparatorString = "%%";
- CommentString = ";";
- PointerSize = CalleeSaveStackSlotSize = 8;
-
- AlignmentIsInBytes = false;
- UsesELFSectionDirectiveForBSS = true;
- SupportsDebugInformation = true;
- UseDataRegionDirectives = true;
-
- ExceptionsType = ExceptionHandling::DwarfCFI;
-}
-
-const MCExpr *ARM64MCAsmInfoDarwin::getExprForPersonalitySymbol(
- const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const {
- // On Darwin, we can reference dwarf symbols with foo at GOT-., which
- // is an indirect pc-relative reference. The default implementation
- // won't reference using the GOT, so we need this target-specific
- // version.
- MCContext &Context = Streamer.getContext();
- const MCExpr *Res =
- MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_GOT, Context);
- MCSymbol *PCSym = Context.CreateTempSymbol();
- Streamer.EmitLabel(PCSym);
- const MCExpr *PC = MCSymbolRefExpr::Create(PCSym, Context);
- return MCBinaryExpr::CreateSub(Res, PC, Context);
-}
-
-ARM64MCAsmInfoELF::ARM64MCAsmInfoELF(StringRef TT) {
- Triple T(TT);
- if (T.getArch() == Triple::arm64_be)
- IsLittleEndian = false;
-
- // We prefer NEON instructions to be printed in the short form.
- AssemblerDialect = AsmWriterVariant == Default ? 0 : AsmWriterVariant;
-
- PointerSize = 8;
-
- // ".comm align is in bytes but .align is pow-2."
- AlignmentIsInBytes = false;
-
- CommentString = "//";
- PrivateGlobalPrefix = ".L";
- Code32Directive = ".code\t32";
-
- Data16bitsDirective = "\t.hword\t";
- Data32bitsDirective = "\t.word\t";
- Data64bitsDirective = "\t.xword\t";
-
- UseDataRegionDirectives = false;
-
- WeakRefDirective = "\t.weak\t";
-
- HasLEB128 = true;
- SupportsDebugInformation = true;
-
- // Exceptions handling
- ExceptionsType = ExceptionHandling::DwarfCFI;
-
- UseIntegratedAssembler = true;
-}
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h (removed)
@@ -1,36 +0,0 @@
-//=====-- ARM64MCAsmInfo.h - ARM64 asm properties -----------*- C++ -*--====//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the declaration of the ARM64MCAsmInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ARM64TARGETASMINFO_H
-#define ARM64TARGETASMINFO_H
-
-#include "llvm/MC/MCAsmInfoDarwin.h"
-
-namespace llvm {
-class Target;
-class StringRef;
-class MCStreamer;
-struct ARM64MCAsmInfoDarwin : public MCAsmInfoDarwin {
- explicit ARM64MCAsmInfoDarwin();
- const MCExpr *
- getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
- MCStreamer &Streamer) const override;
-};
-
-struct ARM64MCAsmInfoELF : public MCAsmInfo {
- explicit ARM64MCAsmInfoELF(StringRef TT);
-};
-
-} // namespace llvm
-
-#endif
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp (removed)
@@ -1,658 +0,0 @@
-//===-- ARM64/ARM64MCCodeEmitter.cpp - Convert ARM64 code to machine code -===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the ARM64MCCodeEmitter class.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCTargetDesc/ARM64AddressingModes.h"
-#include "MCTargetDesc/ARM64FixupKinds.h"
-#include "MCTargetDesc/ARM64MCExpr.h"
-#include "Utils/ARM64BaseInfo.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-#define DEBUG_TYPE "mccodeemitter"
-
-STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
-STATISTIC(MCNumFixups, "Number of MC fixups created.");
-
-namespace {
-
-class ARM64MCCodeEmitter : public MCCodeEmitter {
- MCContext &Ctx;
-
- ARM64MCCodeEmitter(const ARM64MCCodeEmitter &); // DO NOT IMPLEMENT
- void operator=(const ARM64MCCodeEmitter &); // DO NOT IMPLEMENT
-public:
- ARM64MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
- MCContext &ctx)
- : Ctx(ctx) {}
-
- ~ARM64MCCodeEmitter() {}
-
- // getBinaryCodeForInstr - TableGen'erated function for getting the
- // binary encoding for an instruction.
- uint64_t getBinaryCodeForInstr(const MCInst &MI,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getMachineOpValue - Return binary encoding of operand. If the machine
- /// operand requires relocation, record the relocation and return zero.
- unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getLdStUImm12OpValue - Return encoding info for 12-bit unsigned immediate
- /// attached to a load, store or prfm instruction. If operand requires a
- /// relocation, record it and return zero in that part of the encoding.
- template <uint32_t FixupKind>
- uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
- /// target.
- uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getAddSubImmOpValue - Return encoding for the 12-bit immediate value and
- /// the 2-bit shift field.
- uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getCondBranchTargetOpValue - Return the encoded value for a conditional
- /// branch target.
- uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getLoadLiteralOpValue - Return the encoded value for a load-literal
- /// pc-relative address.
- uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getMemExtendOpValue - Return the encoded value for a reg-extend load/store
- /// instruction: bit 0 is whether a shift is present, bit 1 is whether the
- /// operation is a sign extend (as opposed to a zero extend).
- uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getTestBranchTargetOpValue - Return the encoded value for a test-bit-and-
- /// branch target.
- uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getBranchTargetOpValue - Return the encoded value for an unconditional
- /// branch target.
- uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getMoveWideImmOpValue - Return the encoded value for the immediate operand
- /// of a MOVZ or MOVK instruction.
- uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getVecShifterOpValue - Return the encoded value for the vector shifter.
- uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getMoveVecShifterOpValue - Return the encoded value for the vector move
- /// shifter (MSL).
- uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getFixedPointScaleOpValue - Return the encoded value for the
- // FP-to-fixed-point scale factor.
- uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
- uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- /// getSIMDShift64OpValue - Return the encoded value for the
- // shift-by-immediate AdvSIMD instructions.
- uint32_t getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- uint32_t getSIMDShift64_32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- uint32_t getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- uint32_t getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
- unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
- const MCSubtargetInfo &STI) const;
-
- void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; }
-
- void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
- // Output the constant in little endian byte order.
- for (unsigned i = 0; i != Size; ++i) {
- EmitByte(Val & 255, OS);
- Val >>= 8;
- }
- }
-
- void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const override;
-
- unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
- const MCSubtargetInfo &STI) const;
-
- template<int hasRs, int hasRt2> unsigned
- fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
- const MCSubtargetInfo &STI) const;
-
- unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
- const MCSubtargetInfo &STI) const;
-};
-
-} // end anonymous namespace
-
-MCCodeEmitter *llvm::createARM64MCCodeEmitter(const MCInstrInfo &MCII,
- const MCRegisterInfo &MRI,
- const MCSubtargetInfo &STI,
- MCContext &Ctx) {
- return new ARM64MCCodeEmitter(MCII, STI, Ctx);
-}
-
-/// getMachineOpValue - Return binary encoding of operand. If the machine
-/// operand requires relocation, record the relocation and return zero.
-unsigned
-ARM64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- if (MO.isReg())
- return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
- else {
- assert(MO.isImm() && "did not expect relocated expression");
- return static_cast<unsigned>(MO.getImm());
- }
-
- assert(0 && "Unable to encode MCOperand!");
- return 0;
-}
-
-template<unsigned FixupKind> uint32_t
-ARM64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- uint32_t ImmVal = 0;
-
- if (MO.isImm())
- ImmVal = static_cast<uint32_t>(MO.getImm());
- else {
- assert(MO.isExpr() && "unable to encode load/store imm operand");
- MCFixupKind Kind = MCFixupKind(FixupKind);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
- ++MCNumFixups;
- }
-
- return ImmVal;
-}
-
-/// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
-/// target.
-uint32_t
-ARM64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
-
- // If the destination is an immediate, we have nothing to do.
- if (MO.isImm())
- return MO.getImm();
- assert(MO.isExpr() && "Unexpected target type!");
- const MCExpr *Expr = MO.getExpr();
-
- MCFixupKind Kind = MI.getOpcode() == ARM64::ADR
- ? MCFixupKind(ARM64::fixup_arm64_pcrel_adr_imm21)
- : MCFixupKind(ARM64::fixup_arm64_pcrel_adrp_imm21);
- Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
-
- MCNumFixups += 1;
-
- // All of the information is in the fixup.
- return 0;
-}
-
-/// getAddSubImmOpValue - Return encoding for the 12-bit immediate value and
-/// the 2-bit shift field. The shift field is stored in bits 13-14 of the
-/// return value.
-uint32_t
-ARM64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- // Suboperands are [imm, shifter].
- const MCOperand &MO = MI.getOperand(OpIdx);
- const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
- assert(ARM64_AM::getShiftType(MO1.getImm()) == ARM64_AM::LSL &&
- "unexpected shift type for add/sub immediate");
- unsigned ShiftVal = ARM64_AM::getShiftValue(MO1.getImm());
- assert((ShiftVal == 0 || ShiftVal == 12) &&
- "unexpected shift value for add/sub immediate");
- if (MO.isImm())
- return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12));
- assert(MO.isExpr() && "Unable to encode MCOperand!");
- const MCExpr *Expr = MO.getExpr();
-
- // Encode the 12 bits of the fixup.
- MCFixupKind Kind = MCFixupKind(ARM64::fixup_arm64_add_imm12);
- Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
-
- ++MCNumFixups;
-
- return 0;
-}
-
-/// getCondBranchTargetOpValue - Return the encoded value for a conditional
-/// branch target.
-uint32_t ARM64MCCodeEmitter::getCondBranchTargetOpValue(
- const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
-
- // If the destination is an immediate, we have nothing to do.
- if (MO.isImm())
- return MO.getImm();
- assert(MO.isExpr() && "Unexpected target type!");
-
- MCFixupKind Kind = MCFixupKind(ARM64::fixup_arm64_pcrel_branch19);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
-
- ++MCNumFixups;
-
- // All of the information is in the fixup.
- return 0;
-}
-
-/// getLoadLiteralOpValue - Return the encoded value for a load-literal
-/// pc-relative address.
-uint32_t
-ARM64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
-
- // If the destination is an immediate, we have nothing to do.
- if (MO.isImm())
- return MO.getImm();
- assert(MO.isExpr() && "Unexpected target type!");
-
- MCFixupKind Kind = MCFixupKind(ARM64::fixup_arm64_ldr_pcrel_imm19);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
-
- ++MCNumFixups;
-
- // All of the information is in the fixup.
- return 0;
-}
-
-uint32_t
-ARM64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- unsigned SignExtend = MI.getOperand(OpIdx).getImm();
- unsigned DoShift = MI.getOperand(OpIdx + 1).getImm();
- return (SignExtend << 1) | DoShift;
-}
-
-uint32_t
-ARM64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
-
- if (MO.isImm())
- return MO.getImm();
- assert(MO.isExpr() && "Unexpected movz/movk immediate");
-
- Fixups.push_back(MCFixup::Create(
- 0, MO.getExpr(), MCFixupKind(ARM64::fixup_arm64_movw), MI.getLoc()));
-
- ++MCNumFixups;
-
- return 0;
-}
-
-/// getTestBranchTargetOpValue - Return the encoded value for a test-bit-and-
-/// branch target.
-uint32_t ARM64MCCodeEmitter::getTestBranchTargetOpValue(
- const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
-
- // If the destination is an immediate, we have nothing to do.
- if (MO.isImm())
- return MO.getImm();
- assert(MO.isExpr() && "Unexpected ADR target type!");
-
- MCFixupKind Kind = MCFixupKind(ARM64::fixup_arm64_pcrel_branch14);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
-
- ++MCNumFixups;
-
- // All of the information is in the fixup.
- return 0;
-}
-
-/// getBranchTargetOpValue - Return the encoded value for an unconditional
-/// branch target.
-uint32_t
-ARM64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
-
- // If the destination is an immediate, we have nothing to do.
- if (MO.isImm())
- return MO.getImm();
- assert(MO.isExpr() && "Unexpected ADR target type!");
-
- MCFixupKind Kind = MI.getOpcode() == ARM64::BL
- ? MCFixupKind(ARM64::fixup_arm64_pcrel_call26)
- : MCFixupKind(ARM64::fixup_arm64_pcrel_branch26);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
-
- ++MCNumFixups;
-
- // All of the information is in the fixup.
- return 0;
-}
-
-/// getVecShifterOpValue - Return the encoded value for the vector shifter:
-///
-/// 00 -> 0
-/// 01 -> 8
-/// 10 -> 16
-/// 11 -> 24
-uint32_t
-ARM64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the shift amount!");
-
- switch (MO.getImm()) {
- default:
- break;
- case 0:
- return 0;
- case 8:
- return 1;
- case 16:
- return 2;
- case 24:
- return 3;
- }
-
- assert(false && "Invalid value for vector shift amount!");
- return 0;
-}
-
-uint32_t
-ARM64MCCodeEmitter::getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the shift amount!");
- return 64 - (MO.getImm());
-}
-
-uint32_t
-ARM64MCCodeEmitter::getSIMDShift64_32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the shift amount!");
- return 64 - (MO.getImm() | 32);
-}
-
-uint32_t
-ARM64MCCodeEmitter::getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the shift amount!");
- return 32 - (MO.getImm() | 16);
-}
-
-uint32_t
-ARM64MCCodeEmitter::getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the shift amount!");
- return 16 - (MO.getImm() | 8);
-}
-
-/// getFixedPointScaleOpValue - Return the encoded value for the
-// FP-to-fixed-point scale factor.
-uint32_t ARM64MCCodeEmitter::getFixedPointScaleOpValue(
- const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the scale amount!");
- return 64 - MO.getImm();
-}
-
-uint32_t
-ARM64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the scale amount!");
- return 64 - MO.getImm();
-}
-
-uint32_t
-ARM64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the scale amount!");
- return 32 - MO.getImm();
-}
-
-uint32_t
-ARM64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the scale amount!");
- return 16 - MO.getImm();
-}
-
-uint32_t
-ARM64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the scale amount!");
- return 8 - MO.getImm();
-}
-
-uint32_t
-ARM64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the scale amount!");
- return MO.getImm() - 64;
-}
-
-uint32_t
-ARM64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the scale amount!");
- return MO.getImm() - 32;
-}
-
-uint32_t
-ARM64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the scale amount!");
- return MO.getImm() - 16;
-}
-
-uint32_t
-ARM64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() && "Expected an immediate value for the scale amount!");
- return MO.getImm() - 8;
-}
-
-/// getMoveVecShifterOpValue - Return the encoded value for the vector move
-/// shifter (MSL).
-uint32_t
-ARM64MCCodeEmitter::getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- const MCOperand &MO = MI.getOperand(OpIdx);
- assert(MO.isImm() &&
- "Expected an immediate value for the move shift amount!");
- unsigned ShiftVal = ARM64_AM::getShiftValue(MO.getImm());
- assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!");
- return ShiftVal == 8 ? 0 : 1;
-}
-
-unsigned ARM64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
- const MCSubtargetInfo &STI) const {
- // If one of the signed fixup kinds is applied to a MOVZ instruction, the
- // eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's
- // job to ensure that any bits possibly affected by this are 0. This means we
- // must zero out bit 30 (essentially emitting a MOVN).
- MCOperand UImm16MO = MI.getOperand(1);
-
- // Nothing to do if there's no fixup.
- if (UImm16MO.isImm())
- return EncodedValue;
-
- const ARM64MCExpr *A64E = cast<ARM64MCExpr>(UImm16MO.getExpr());
- switch (A64E->getKind()) {
- case ARM64MCExpr::VK_DTPREL_G2:
- case ARM64MCExpr::VK_DTPREL_G1:
- case ARM64MCExpr::VK_DTPREL_G0:
- case ARM64MCExpr::VK_GOTTPREL_G1:
- case ARM64MCExpr::VK_TPREL_G2:
- case ARM64MCExpr::VK_TPREL_G1:
- case ARM64MCExpr::VK_TPREL_G0:
- return EncodedValue & ~(1u << 30);
- default:
- // Nothing to do for an unsigned fixup.
- return EncodedValue;
- }
-
-
- return EncodedValue & ~(1u << 30);
-}
-
-void ARM64MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- if (MI.getOpcode() == ARM64::TLSDESCCALL) {
- // This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
- // following (BLR) instruction. It doesn't emit any code itself so it
- // doesn't go through the normal TableGenerated channels.
- MCFixupKind Fixup = MCFixupKind(ARM64::fixup_arm64_tlsdesc_call);
- Fixups.push_back(MCFixup::Create(0, MI.getOperand(0).getExpr(), Fixup));
- return;
- }
-
- uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
- EmitConstant(Binary, 4, OS);
- ++MCNumEmitted; // Keep track of the # of mi's emitted.
-}
-
-unsigned
-ARM64MCCodeEmitter::fixMulHigh(const MCInst &MI,
- unsigned EncodedValue,
- const MCSubtargetInfo &STI) const {
- // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
- // (i.e. all bits 1) but is ignored by the processor.
- EncodedValue |= 0x1f << 10;
- return EncodedValue;
-}
-
-template<int hasRs, int hasRt2> unsigned
-ARM64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
- unsigned EncodedValue,
- const MCSubtargetInfo &STI) const {
- if (!hasRs) EncodedValue |= 0x001F0000;
- if (!hasRt2) EncodedValue |= 0x00007C00;
-
- return EncodedValue;
-}
-
-unsigned
-ARM64MCCodeEmitter::fixOneOperandFPComparison(const MCInst &MI,
- unsigned EncodedValue,
- const MCSubtargetInfo &STI) const {
- // The Rm field of FCMP and friends is unused - it should be assembled
- // as 0, but is ignored by the processor.
- EncodedValue &= ~(0x1f << 16);
- return EncodedValue;
-}
-
-#include "ARM64GenMCCodeEmitter.inc"
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp (removed)
@@ -1,174 +0,0 @@
-//===-- ARM64MCExpr.cpp - ARM64 specific MC expression classes --------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the implementation of the assembly expression modifiers
-// accepted by the AArch64 architecture (e.g. ":lo12:", ":gottprel_g1:", ...).
-//
-//===----------------------------------------------------------------------===//
-
-#include "ARM64MCExpr.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCELF.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/Object/ELF.h"
-#include "llvm/Support/ErrorHandling.h"
-
-using namespace llvm;
-
-#define DEBUG_TYPE "aarch64symbolrefexpr"
-
-const ARM64MCExpr *ARM64MCExpr::Create(const MCExpr *Expr, VariantKind Kind,
- MCContext &Ctx) {
- return new (Ctx) ARM64MCExpr(Expr, Kind);
-}
-
-StringRef ARM64MCExpr::getVariantKindName() const {
- switch (static_cast<uint32_t>(getKind())) {
- case VK_CALL: return "";
- case VK_LO12: return ":lo12:";
- case VK_ABS_G3: return ":abs_g3:";
- case VK_ABS_G2: return ":abs_g2:";
- case VK_ABS_G2_S: return ":abs_g2_s:";
- case VK_ABS_G2_NC: return ":abs_g2_nc:";
- case VK_ABS_G1: return ":abs_g1:";
- case VK_ABS_G1_S: return ":abs_g1_s:";
- case VK_ABS_G1_NC: return ":abs_g1_nc:";
- case VK_ABS_G0: return ":abs_g0:";
- case VK_ABS_G0_S: return ":abs_g0_s:";
- case VK_ABS_G0_NC: return ":abs_g0_nc:";
- case VK_DTPREL_G2: return ":dtprel_g2:";
- case VK_DTPREL_G1: return ":dtprel_g1:";
- case VK_DTPREL_G1_NC: return ":dtprel_g1_nc:";
- case VK_DTPREL_G0: return ":dtprel_g0:";
- case VK_DTPREL_G0_NC: return ":dtprel_g0_nc:";
- case VK_DTPREL_HI12: return ":dtprel_hi12:";
- case VK_DTPREL_LO12: return ":dtprel_lo12:";
- case VK_DTPREL_LO12_NC: return ":dtprel_lo12_nc:";
- case VK_TPREL_G2: return ":tprel_g2:";
- case VK_TPREL_G1: return ":tprel_g1:";
- case VK_TPREL_G1_NC: return ":tprel_g1_nc:";
- case VK_TPREL_G0: return ":tprel_g0:";
- case VK_TPREL_G0_NC: return ":tprel_g0_nc:";
- case VK_TPREL_HI12: return ":tprel_hi12:";
- case VK_TPREL_LO12: return ":tprel_lo12:";
- case VK_TPREL_LO12_NC: return ":tprel_lo12_nc:";
- case VK_TLSDESC_LO12: return ":tlsdesc_lo12:";
- case VK_ABS_PAGE: return "";
- case VK_GOT_PAGE: return ":got:";
- case VK_GOT_LO12: return ":got_lo12:";
- case VK_GOTTPREL_PAGE: return ":gottprel:";
- case VK_GOTTPREL_LO12_NC: return ":gottprel_lo12:";
- case VK_GOTTPREL_G1: return ":gottprel_g1:";
- case VK_GOTTPREL_G0_NC: return ":gottprel_g0_nc:";
- case VK_TLSDESC: return "";
- case VK_TLSDESC_PAGE: return ":tlsdesc:";
- default:
- llvm_unreachable("Invalid ELF symbol kind");
- }
-}
-
-void ARM64MCExpr::PrintImpl(raw_ostream &OS) const {
- if (getKind() != VK_NONE)
- OS << getVariantKindName();
- OS << *Expr;
-}
-
-// FIXME: This basically copies MCObjectStreamer::AddValueSymbols. Perhaps
-// that method should be made public?
-// FIXME: really do above: now that two backends are using it.
-static void AddValueSymbolsImpl(const MCExpr *Value, MCAssembler *Asm) {
- switch (Value->getKind()) {
- case MCExpr::Target:
- llvm_unreachable("Can't handle nested target expr!");
- break;
-
- case MCExpr::Constant:
- break;
-
- case MCExpr::Binary: {
- const MCBinaryExpr *BE = cast<MCBinaryExpr>(Value);
- AddValueSymbolsImpl(BE->getLHS(), Asm);
- AddValueSymbolsImpl(BE->getRHS(), Asm);
- break;
- }
-
- case MCExpr::SymbolRef:
- Asm->getOrCreateSymbolData(cast<MCSymbolRefExpr>(Value)->getSymbol());
- break;
-
- case MCExpr::Unary:
- AddValueSymbolsImpl(cast<MCUnaryExpr>(Value)->getSubExpr(), Asm);
- break;
- }
-}
-
-void ARM64MCExpr::AddValueSymbols(MCAssembler *Asm) const {
- AddValueSymbolsImpl(getSubExpr(), Asm);
-}
-
-const MCSection *ARM64MCExpr::FindAssociatedSection() const {
- llvm_unreachable("FIXME: what goes here?");
-}
-
-bool ARM64MCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
- const MCAsmLayout *Layout) const {
- if (!getSubExpr()->EvaluateAsRelocatable(Res, Layout))
- return false;
-
- Res =
- MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());
-
- return true;
-}
-
-static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {
- switch (Expr->getKind()) {
- case MCExpr::Target:
- llvm_unreachable("Can't handle nested target expression");
- break;
- case MCExpr::Constant:
- break;
-
- case MCExpr::Binary: {
- const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
- fixELFSymbolsInTLSFixupsImpl(BE->getLHS(), Asm);
- fixELFSymbolsInTLSFixupsImpl(BE->getRHS(), Asm);
- break;
- }
-
- case MCExpr::SymbolRef: {
- // We're known to be under a TLS fixup, so any symbol should be
- // modified. There should be only one.
- const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
- MCSymbolData &SD = Asm.getOrCreateSymbolData(SymRef.getSymbol());
- MCELF::SetType(SD, ELF::STT_TLS);
- break;
- }
-
- case MCExpr::Unary:
- fixELFSymbolsInTLSFixupsImpl(cast<MCUnaryExpr>(Expr)->getSubExpr(), Asm);
- break;
- }
-}
-
-void ARM64MCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
- switch (getSymbolLoc(Kind)) {
- default:
- return;
- case VK_DTPREL:
- case VK_GOTTPREL:
- case VK_TPREL:
- case VK_TLSDESC:
- break;
- }
-
- fixELFSymbolsInTLSFixupsImpl(getSubExpr(), Asm);
-}
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h (removed)
@@ -1,168 +0,0 @@
-//=---- ARM64MCExpr.h - ARM64 specific MC expression classes ------*- C++ -*-=//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes ARM64-specific MCExprs, used for modifiers like
-// ":lo12:" or ":gottprel_g1:".
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_ARM64MCEXPR_H
-#define LLVM_ARM64MCEXPR_H
-
-#include "llvm/MC/MCExpr.h"
-#include "llvm/Support/ErrorHandling.h"
-
-namespace llvm {
-
-class ARM64MCExpr : public MCTargetExpr {
-public:
- enum VariantKind {
- VK_NONE = 0x000,
-
- // Symbol locations specifying (roughly speaking) what calculation should be
- // performed to construct the final address for the relocated
- // symbol. E.g. direct, via the GOT, ...
- VK_ABS = 0x001,
- VK_SABS = 0x002,
- VK_GOT = 0x003,
- VK_DTPREL = 0x004,
- VK_GOTTPREL = 0x005,
- VK_TPREL = 0x006,
- VK_TLSDESC = 0x007,
- VK_SymLocBits = 0x00f,
-
- // Variants specifying which part of the final address calculation is
- // used. E.g. the low 12 bits for an ADD/LDR, the middle 16 bits for a
- // MOVZ/MOVK.
- VK_PAGE = 0x010,
- VK_PAGEOFF = 0x020,
- VK_HI12 = 0x030,
- VK_G0 = 0x040,
- VK_G1 = 0x050,
- VK_G2 = 0x060,
- VK_G3 = 0x070,
- VK_AddressFragBits = 0x0f0,
-
- // Whether the final relocation is a checked one (where a linker should
- // perform a range-check on the final address) or not. Note that this field
- // is unfortunately sometimes omitted from the assembly syntax. E.g. :lo12:
- // on its own is a non-checked relocation. We side with ELF on being
- // explicit about this!
- VK_NC = 0x100,
-
- // Convenience definitions for referring to specific textual representations
- // of relocation specifiers. Note that this means the "_NC" is sometimes
- // omitted in line with assembly syntax here (VK_LO12 rather than VK_LO12_NC
- // since a user would write ":lo12:").
- VK_CALL = VK_ABS,
- VK_ABS_PAGE = VK_ABS | VK_PAGE,
- VK_ABS_G3 = VK_ABS | VK_G3,
- VK_ABS_G2 = VK_ABS | VK_G2,
- VK_ABS_G2_S = VK_SABS | VK_G2,
- VK_ABS_G2_NC = VK_ABS | VK_G2 | VK_NC,
- VK_ABS_G1 = VK_ABS | VK_G1,
- VK_ABS_G1_S = VK_SABS | VK_G1,
- VK_ABS_G1_NC = VK_ABS | VK_G1 | VK_NC,
- VK_ABS_G0 = VK_ABS | VK_G0,
- VK_ABS_G0_S = VK_SABS | VK_G0,
- VK_ABS_G0_NC = VK_ABS | VK_G0 | VK_NC,
- VK_LO12 = VK_ABS | VK_PAGEOFF | VK_NC,
- VK_GOT_LO12 = VK_GOT | VK_PAGEOFF | VK_NC,
- VK_GOT_PAGE = VK_GOT | VK_PAGE,
- VK_DTPREL_G2 = VK_DTPREL | VK_G2,
- VK_DTPREL_G1 = VK_DTPREL | VK_G1,
- VK_DTPREL_G1_NC = VK_DTPREL | VK_G1 | VK_NC,
- VK_DTPREL_G0 = VK_DTPREL | VK_G0,
- VK_DTPREL_G0_NC = VK_DTPREL | VK_G0 | VK_NC,
- VK_DTPREL_HI12 = VK_DTPREL | VK_HI12,
- VK_DTPREL_LO12 = VK_DTPREL | VK_PAGEOFF,
- VK_DTPREL_LO12_NC = VK_DTPREL | VK_PAGEOFF | VK_NC,
- VK_GOTTPREL_PAGE = VK_GOTTPREL | VK_PAGE,
- VK_GOTTPREL_LO12_NC = VK_GOTTPREL | VK_PAGEOFF | VK_NC,
- VK_GOTTPREL_G1 = VK_GOTTPREL | VK_G1,
- VK_GOTTPREL_G0_NC = VK_GOTTPREL | VK_G0 | VK_NC,
- VK_TPREL_G2 = VK_TPREL | VK_G2,
- VK_TPREL_G1 = VK_TPREL | VK_G1,
- VK_TPREL_G1_NC = VK_TPREL | VK_G1 | VK_NC,
- VK_TPREL_G0 = VK_TPREL | VK_G0,
- VK_TPREL_G0_NC = VK_TPREL | VK_G0 | VK_NC,
- VK_TPREL_HI12 = VK_TPREL | VK_HI12,
- VK_TPREL_LO12 = VK_TPREL | VK_PAGEOFF,
- VK_TPREL_LO12_NC = VK_TPREL | VK_PAGEOFF | VK_NC,
- VK_TLSDESC_LO12 = VK_TLSDESC | VK_PAGEOFF | VK_NC,
- VK_TLSDESC_PAGE = VK_TLSDESC | VK_PAGE,
-
- VK_INVALID = 0xfff
- };
-
-private:
- const MCExpr *Expr;
- const VariantKind Kind;
-
- explicit ARM64MCExpr(const MCExpr *Expr, VariantKind Kind)
- : Expr(Expr), Kind(Kind) {}
-
-public:
- /// @name Construction
- /// @{
-
- static const ARM64MCExpr *Create(const MCExpr *Expr, VariantKind Kind,
- MCContext &Ctx);
-
- /// @}
- /// @name Accessors
- /// @{
-
- /// Get the kind of this expression.
- VariantKind getKind() const { return static_cast<VariantKind>(Kind); }
-
- /// Get the expression this modifier applies to.
- const MCExpr *getSubExpr() const { return Expr; }
-
- /// @}
- /// @name VariantKind information extractors.
- /// @{
-
- static VariantKind getSymbolLoc(VariantKind Kind) {
- return static_cast<VariantKind>(Kind & VK_SymLocBits);
- }
-
- static VariantKind getAddressFrag(VariantKind Kind) {
- return static_cast<VariantKind>(Kind & VK_AddressFragBits);
- }
-
- static bool isNotChecked(VariantKind Kind) { return Kind & VK_NC; }
-
- /// @}
-
- /// Convert the variant kind into an ELF-appropriate modifier
- /// (e.g. ":got:", ":lo12:").
- StringRef getVariantKindName() const;
-
- void PrintImpl(raw_ostream &OS) const override;
-
- void AddValueSymbols(MCAssembler *) const override;
-
- const MCSection *FindAssociatedSection() const override;
-
- bool EvaluateAsRelocatableImpl(MCValue &Res,
- const MCAsmLayout *Layout) const override;
-
- void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
-
- static bool classof(const MCExpr *E) {
- return E->getKind() == MCExpr::Target;
- }
-
- static bool classof(const ARM64MCExpr *) { return true; }
-
-};
-} // end namespace llvm
-
-#endif
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp (removed)
@@ -1,210 +0,0 @@
-//===-- ARM64MCTargetDesc.cpp - ARM64 Target Descriptions -------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides ARM64 specific target descriptions.
-//
-//===----------------------------------------------------------------------===//
-
-#include "ARM64MCTargetDesc.h"
-#include "ARM64ELFStreamer.h"
-#include "ARM64MCAsmInfo.h"
-#include "InstPrinter/ARM64InstPrinter.h"
-#include "llvm/MC/MCCodeGenInfo.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/TargetRegistry.h"
-
-using namespace llvm;
-
-#define GET_INSTRINFO_MC_DESC
-#include "ARM64GenInstrInfo.inc"
-
-#define GET_SUBTARGETINFO_MC_DESC
-#include "ARM64GenSubtargetInfo.inc"
-
-#define GET_REGINFO_MC_DESC
-#include "ARM64GenRegisterInfo.inc"
-
-static MCInstrInfo *createARM64MCInstrInfo() {
- MCInstrInfo *X = new MCInstrInfo();
- InitARM64MCInstrInfo(X);
- return X;
-}
-
-static MCSubtargetInfo *createARM64MCSubtargetInfo(StringRef TT, StringRef CPU,
- StringRef FS) {
- MCSubtargetInfo *X = new MCSubtargetInfo();
-
- if (CPU.empty())
- CPU = "generic";
-
- InitARM64MCSubtargetInfo(X, TT, CPU, FS);
- return X;
-}
-
-static MCRegisterInfo *createARM64MCRegisterInfo(StringRef Triple) {
- MCRegisterInfo *X = new MCRegisterInfo();
- InitARM64MCRegisterInfo(X, ARM64::LR);
- return X;
-}
-
-static MCAsmInfo *createARM64MCAsmInfo(const MCRegisterInfo &MRI,
- StringRef TT) {
- Triple TheTriple(TT);
-
- MCAsmInfo *MAI;
- if (TheTriple.isOSDarwin())
- MAI = new ARM64MCAsmInfoDarwin();
- else {
- assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
- MAI = new ARM64MCAsmInfoELF(TT);
- }
-
- // Initial state of the frame pointer is SP.
- unsigned Reg = MRI.getDwarfRegNum(ARM64::SP, true);
- MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
- MAI->addInitialFrameState(Inst);
-
- return MAI;
-}
-
-static MCCodeGenInfo *createARM64MCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM,
- CodeGenOpt::Level OL) {
- Triple TheTriple(TT);
- assert((TheTriple.isOSBinFormatELF() || TheTriple.isOSBinFormatMachO()) &&
- "Only expect Darwin and ELF targets");
-
- if (CM == CodeModel::Default)
- CM = CodeModel::Small;
- // The default MCJIT memory managers make no guarantees about where they can
- // find an executable page; JITed code needs to be able to refer to globals
- // no matter how far away they are.
- else if (CM == CodeModel::JITDefault)
- CM = CodeModel::Large;
- else if (CM != CodeModel::Small && CM != CodeModel::Large)
- report_fatal_error("Only small and large code models are allowed on ARM64");
-
- // ARM64 Darwin is always PIC.
- if (TheTriple.isOSDarwin())
- RM = Reloc::PIC_;
- // On ELF platforms the default static relocation model has a smart enough
- // linker to cope with referencing external symbols defined in a shared
- // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
- else if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
- RM = Reloc::Static;
-
- MCCodeGenInfo *X = new MCCodeGenInfo();
- X->InitMCCodeGenInfo(RM, CM, OL);
- return X;
-}
-
-static MCInstPrinter *createARM64MCInstPrinter(const Target &T,
- unsigned SyntaxVariant,
- const MCAsmInfo &MAI,
- const MCInstrInfo &MII,
- const MCRegisterInfo &MRI,
- const MCSubtargetInfo &STI) {
- if (SyntaxVariant == 0)
- return new ARM64InstPrinter(MAI, MII, MRI, STI);
- if (SyntaxVariant == 1)
- return new ARM64AppleInstPrinter(MAI, MII, MRI, STI);
-
- return nullptr;
-}
-
-static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
- MCContext &Ctx, MCAsmBackend &TAB,
- raw_ostream &OS, MCCodeEmitter *Emitter,
- const MCSubtargetInfo &STI, bool RelaxAll,
- bool NoExecStack) {
- Triple TheTriple(TT);
-
- if (TheTriple.isOSDarwin())
- return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
- /*LabelSections*/ true);
-
- return createARM64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack);
-}
-
-// Force static initialization.
-extern "C" void LLVMInitializeARM64TargetMC() {
- // Register the MC asm info.
- RegisterMCAsmInfoFn X(TheARM64leTarget, createARM64MCAsmInfo);
- RegisterMCAsmInfoFn Y(TheARM64beTarget, createARM64MCAsmInfo);
- RegisterMCAsmInfoFn Z(TheAArch64leTarget, createARM64MCAsmInfo);
- RegisterMCAsmInfoFn W(TheAArch64beTarget, createARM64MCAsmInfo);
-
- // Register the MC codegen info.
- TargetRegistry::RegisterMCCodeGenInfo(TheARM64leTarget,
- createARM64MCCodeGenInfo);
- TargetRegistry::RegisterMCCodeGenInfo(TheARM64beTarget,
- createARM64MCCodeGenInfo);
- TargetRegistry::RegisterMCCodeGenInfo(TheAArch64leTarget,
- createARM64MCCodeGenInfo);
- TargetRegistry::RegisterMCCodeGenInfo(TheAArch64beTarget,
- createARM64MCCodeGenInfo);
-
- // Register the MC instruction info.
- TargetRegistry::RegisterMCInstrInfo(TheARM64leTarget, createARM64MCInstrInfo);
- TargetRegistry::RegisterMCInstrInfo(TheARM64beTarget, createARM64MCInstrInfo);
- TargetRegistry::RegisterMCInstrInfo(TheAArch64leTarget, createARM64MCInstrInfo);
- TargetRegistry::RegisterMCInstrInfo(TheAArch64beTarget, createARM64MCInstrInfo);
-
- // Register the MC register info.
- TargetRegistry::RegisterMCRegInfo(TheARM64leTarget, createARM64MCRegisterInfo);
- TargetRegistry::RegisterMCRegInfo(TheARM64beTarget, createARM64MCRegisterInfo);
- TargetRegistry::RegisterMCRegInfo(TheAArch64leTarget, createARM64MCRegisterInfo);
- TargetRegistry::RegisterMCRegInfo(TheAArch64beTarget, createARM64MCRegisterInfo);
-
- // Register the MC subtarget info.
- TargetRegistry::RegisterMCSubtargetInfo(TheARM64leTarget,
- createARM64MCSubtargetInfo);
- TargetRegistry::RegisterMCSubtargetInfo(TheARM64beTarget,
- createARM64MCSubtargetInfo);
- TargetRegistry::RegisterMCSubtargetInfo(TheAArch64leTarget,
- createARM64MCSubtargetInfo);
- TargetRegistry::RegisterMCSubtargetInfo(TheAArch64beTarget,
- createARM64MCSubtargetInfo);
-
- // Register the asm backend.
- TargetRegistry::RegisterMCAsmBackend(TheARM64leTarget, createARM64leAsmBackend);
- TargetRegistry::RegisterMCAsmBackend(TheARM64beTarget, createARM64beAsmBackend);
- TargetRegistry::RegisterMCAsmBackend(TheAArch64leTarget, createARM64leAsmBackend);
- TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget, createARM64beAsmBackend);
-
- // Register the MC Code Emitter
- TargetRegistry::RegisterMCCodeEmitter(TheARM64leTarget,
- createARM64MCCodeEmitter);
- TargetRegistry::RegisterMCCodeEmitter(TheARM64beTarget,
- createARM64MCCodeEmitter);
- TargetRegistry::RegisterMCCodeEmitter(TheAArch64leTarget,
- createARM64MCCodeEmitter);
- TargetRegistry::RegisterMCCodeEmitter(TheAArch64beTarget,
- createARM64MCCodeEmitter);
-
- // Register the object streamer.
- TargetRegistry::RegisterMCObjectStreamer(TheARM64leTarget, createMCStreamer);
- TargetRegistry::RegisterMCObjectStreamer(TheARM64beTarget, createMCStreamer);
- TargetRegistry::RegisterMCObjectStreamer(TheAArch64leTarget, createMCStreamer);
- TargetRegistry::RegisterMCObjectStreamer(TheAArch64beTarget, createMCStreamer);
-
- // Register the MCInstPrinter.
- TargetRegistry::RegisterMCInstPrinter(TheARM64leTarget,
- createARM64MCInstPrinter);
- TargetRegistry::RegisterMCInstPrinter(TheARM64beTarget,
- createARM64MCInstPrinter);
- TargetRegistry::RegisterMCInstPrinter(TheAArch64leTarget,
- createARM64MCInstPrinter);
- TargetRegistry::RegisterMCInstPrinter(TheAArch64beTarget,
- createARM64MCInstPrinter);
-}
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h (removed)
@@ -1,68 +0,0 @@
-//===-- ARM64MCTargetDesc.h - ARM64 Target Descriptions ---------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides ARM64 specific target descriptions.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ARM64MCTARGETDESC_H
-#define ARM64MCTARGETDESC_H
-
-#include "llvm/Support/DataTypes.h"
-#include <string>
-
-namespace llvm {
-class MCAsmBackend;
-class MCCodeEmitter;
-class MCContext;
-class MCInstrInfo;
-class MCRegisterInfo;
-class MCObjectWriter;
-class MCSubtargetInfo;
-class StringRef;
-class Target;
-class raw_ostream;
-
-extern Target TheARM64leTarget;
-extern Target TheARM64beTarget;
-extern Target TheAArch64leTarget;
-extern Target TheAArch64beTarget;
-
-MCCodeEmitter *createARM64MCCodeEmitter(const MCInstrInfo &MCII,
- const MCRegisterInfo &MRI,
- const MCSubtargetInfo &STI,
- MCContext &Ctx);
-MCAsmBackend *createARM64leAsmBackend(const Target &T, const MCRegisterInfo &MRI,
- StringRef TT, StringRef CPU);
-MCAsmBackend *createARM64beAsmBackend(const Target &T, const MCRegisterInfo &MRI,
- StringRef TT, StringRef CPU);
-
- MCObjectWriter *createARM64ELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
- bool IsLittleEndian);
-
-MCObjectWriter *createARM64MachObjectWriter(raw_ostream &OS, uint32_t CPUType,
- uint32_t CPUSubtype);
-
-} // End llvm namespace
-
-// Defines symbolic names for ARM64 registers. This defines a mapping from
-// register name to register number.
-//
-#define GET_REGINFO_ENUM
-#include "ARM64GenRegisterInfo.inc"
-
-// Defines symbolic names for the ARM64 instructions.
-//
-#define GET_INSTRINFO_ENUM
-#include "ARM64GenInstrInfo.inc"
-
-#define GET_SUBTARGETINFO_ENUM
-#include "ARM64GenSubtargetInfo.inc"
-
-#endif
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp (removed)
@@ -1,395 +0,0 @@
-//===-- ARMMachObjectWriter.cpp - ARM Mach Object Writer ------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCTargetDesc/ARM64FixupKinds.h"
-#include "MCTargetDesc/ARM64MCTargetDesc.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCAsmLayout.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCFixup.h"
-#include "llvm/MC/MCMachObjectWriter.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MachO.h"
-using namespace llvm;
-
-namespace {
-class ARM64MachObjectWriter : public MCMachObjectTargetWriter {
- bool getARM64FixupKindMachOInfo(const MCFixup &Fixup, unsigned &RelocType,
- const MCSymbolRefExpr *Sym,
- unsigned &Log2Size, const MCAssembler &Asm);
-
-public:
- ARM64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype)
- : MCMachObjectTargetWriter(true /* is64Bit */, CPUType, CPUSubtype,
- /*UseAggressiveSymbolFolding=*/true) {}
-
- void RecordRelocation(MachObjectWriter *Writer, const MCAssembler &Asm,
- const MCAsmLayout &Layout, const MCFragment *Fragment,
- const MCFixup &Fixup, MCValue Target,
- uint64_t &FixedValue) override;
-};
-}
-
-bool ARM64MachObjectWriter::getARM64FixupKindMachOInfo(
- const MCFixup &Fixup, unsigned &RelocType, const MCSymbolRefExpr *Sym,
- unsigned &Log2Size, const MCAssembler &Asm) {
- RelocType = unsigned(MachO::ARM64_RELOC_UNSIGNED);
- Log2Size = ~0U;
-
- switch ((unsigned)Fixup.getKind()) {
- default:
- return false;
-
- case FK_Data_1:
- Log2Size = llvm::Log2_32(1);
- return true;
- case FK_Data_2:
- Log2Size = llvm::Log2_32(2);
- return true;
- case FK_Data_4:
- Log2Size = llvm::Log2_32(4);
- if (Sym->getKind() == MCSymbolRefExpr::VK_GOT)
- RelocType = unsigned(MachO::ARM64_RELOC_POINTER_TO_GOT);
- return true;
- case FK_Data_8:
- Log2Size = llvm::Log2_32(8);
- if (Sym->getKind() == MCSymbolRefExpr::VK_GOT)
- RelocType = unsigned(MachO::ARM64_RELOC_POINTER_TO_GOT);
- return true;
- case ARM64::fixup_arm64_add_imm12:
- case ARM64::fixup_arm64_ldst_imm12_scale1:
- case ARM64::fixup_arm64_ldst_imm12_scale2:
- case ARM64::fixup_arm64_ldst_imm12_scale4:
- case ARM64::fixup_arm64_ldst_imm12_scale8:
- case ARM64::fixup_arm64_ldst_imm12_scale16:
- Log2Size = llvm::Log2_32(4);
- switch (Sym->getKind()) {
- default:
- assert(0 && "Unexpected symbol reference variant kind!");
- case MCSymbolRefExpr::VK_PAGEOFF:
- RelocType = unsigned(MachO::ARM64_RELOC_PAGEOFF12);
- return true;
- case MCSymbolRefExpr::VK_GOTPAGEOFF:
- RelocType = unsigned(MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12);
- return true;
- case MCSymbolRefExpr::VK_TLVPPAGEOFF:
- RelocType = unsigned(MachO::ARM64_RELOC_TLVP_LOAD_PAGEOFF12);
- return true;
- }
- case ARM64::fixup_arm64_pcrel_adrp_imm21:
- Log2Size = llvm::Log2_32(4);
- // This encompasses the relocation for the whole 21-bit value.
- switch (Sym->getKind()) {
- default:
- Asm.getContext().FatalError(Fixup.getLoc(),
- "ADR/ADRP relocations must be GOT relative");
- case MCSymbolRefExpr::VK_PAGE:
- RelocType = unsigned(MachO::ARM64_RELOC_PAGE21);
- return true;
- case MCSymbolRefExpr::VK_GOTPAGE:
- RelocType = unsigned(MachO::ARM64_RELOC_GOT_LOAD_PAGE21);
- return true;
- case MCSymbolRefExpr::VK_TLVPPAGE:
- RelocType = unsigned(MachO::ARM64_RELOC_TLVP_LOAD_PAGE21);
- return true;
- }
- return true;
- case ARM64::fixup_arm64_pcrel_branch26:
- case ARM64::fixup_arm64_pcrel_call26:
- Log2Size = llvm::Log2_32(4);
- RelocType = unsigned(MachO::ARM64_RELOC_BRANCH26);
- return true;
- }
-}
-
-void ARM64MachObjectWriter::RecordRelocation(
- MachObjectWriter *Writer, const MCAssembler &Asm, const MCAsmLayout &Layout,
- const MCFragment *Fragment, const MCFixup &Fixup, MCValue Target,
- uint64_t &FixedValue) {
- unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
-
- // See <reloc.h>.
- uint32_t FixupOffset = Layout.getFragmentOffset(Fragment);
- unsigned Log2Size = 0;
- int64_t Value = 0;
- unsigned Index = 0;
- unsigned IsExtern = 0;
- unsigned Type = 0;
- unsigned Kind = Fixup.getKind();
-
- FixupOffset += Fixup.getOffset();
-
- // ARM64 pcrel relocation addends do not include the section offset.
- if (IsPCRel)
- FixedValue += FixupOffset;
-
- // ADRP fixups use relocations for the whole symbol value and only
- // put the addend in the instruction itself. Clear out any value the
- // generic code figured out from the sybmol definition.
- if (Kind == ARM64::fixup_arm64_pcrel_adrp_imm21)
- FixedValue = 0;
-
- // imm19 relocations are for conditional branches, which require
- // assembler local symbols. If we got here, that's not what we have,
- // so complain loudly.
- if (Kind == ARM64::fixup_arm64_pcrel_branch19) {
- Asm.getContext().FatalError(Fixup.getLoc(),
- "conditional branch requires assembler-local"
- " label. '" +
- Target.getSymA()->getSymbol().getName() +
- "' is external.");
- return;
- }
-
- // 14-bit branch relocations should only target internal labels, and so
- // should never get here.
- if (Kind == ARM64::fixup_arm64_pcrel_branch14) {
- Asm.getContext().FatalError(Fixup.getLoc(),
- "Invalid relocation on conditional branch!");
- return;
- }
-
- if (!getARM64FixupKindMachOInfo(Fixup, Type, Target.getSymA(), Log2Size,
- Asm)) {
- Asm.getContext().FatalError(Fixup.getLoc(), "unknown ARM64 fixup kind!");
- return;
- }
-
- Value = Target.getConstant();
-
- if (Target.isAbsolute()) { // constant
- // FIXME: Should this always be extern?
- // SymbolNum of 0 indicates the absolute section.
- Type = MachO::ARM64_RELOC_UNSIGNED;
- Index = 0;
-
- if (IsPCRel) {
- IsExtern = 1;
- Asm.getContext().FatalError(Fixup.getLoc(),
- "PC relative absolute relocation!");
-
- // FIXME: x86_64 sets the type to a branch reloc here. Should we do
- // something similar?
- }
- } else if (Target.getSymB()) { // A - B + constant
- const MCSymbol *A = &Target.getSymA()->getSymbol();
- const MCSymbolData &A_SD = Asm.getSymbolData(*A);
- const MCSymbolData *A_Base = Asm.getAtom(&A_SD);
-
- const MCSymbol *B = &Target.getSymB()->getSymbol();
- const MCSymbolData &B_SD = Asm.getSymbolData(*B);
- const MCSymbolData *B_Base = Asm.getAtom(&B_SD);
-
- // Check for "_foo at got - .", which comes through here as:
- // Ltmp0:
- // ... _foo at got - Ltmp0
- if (Target.getSymA()->getKind() == MCSymbolRefExpr::VK_GOT &&
- Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None &&
- Layout.getSymbolOffset(&B_SD) ==
- Layout.getFragmentOffset(Fragment) + Fixup.getOffset()) {
- // SymB is the PC, so use a PC-rel pointer-to-GOT relocation.
- Index = A_Base->getIndex();
- IsExtern = 1;
- Type = MachO::ARM64_RELOC_POINTER_TO_GOT;
- IsPCRel = 1;
- MachO::any_relocation_info MRE;
- MRE.r_word0 = FixupOffset;
- MRE.r_word1 = ((Index << 0) | (IsPCRel << 24) | (Log2Size << 25) |
- (IsExtern << 27) | (Type << 28));
- Writer->addRelocation(Fragment->getParent(), MRE);
- return;
- } else if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
- Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None)
- // Otherwise, neither symbol can be modified.
- Asm.getContext().FatalError(Fixup.getLoc(),
- "unsupported relocation of modified symbol");
-
- // We don't support PCrel relocations of differences.
- if (IsPCRel)
- Asm.getContext().FatalError(Fixup.getLoc(),
- "unsupported pc-relative relocation of "
- "difference");
-
- // ARM64 always uses external relocations. If there is no symbol to use as
- // a base address (a local symbol with no preceding non-local symbol),
- // error out.
- //
- // FIXME: We should probably just synthesize an external symbol and use
- // that.
- if (!A_Base)
- Asm.getContext().FatalError(
- Fixup.getLoc(),
- "unsupported relocation of local symbol '" + A->getName() +
- "'. Must have non-local symbol earlier in section.");
- if (!B_Base)
- Asm.getContext().FatalError(
- Fixup.getLoc(),
- "unsupported relocation of local symbol '" + B->getName() +
- "'. Must have non-local symbol earlier in section.");
-
- if (A_Base == B_Base && A_Base)
- Asm.getContext().FatalError(Fixup.getLoc(),
- "unsupported relocation with identical base");
-
- Value += (!A_SD.getFragment() ? 0
- : Writer->getSymbolAddress(&A_SD, Layout)) -
- (!A_Base || !A_Base->getFragment()
- ? 0
- : Writer->getSymbolAddress(A_Base, Layout));
- Value -= (!B_SD.getFragment() ? 0
- : Writer->getSymbolAddress(&B_SD, Layout)) -
- (!B_Base || !B_Base->getFragment()
- ? 0
- : Writer->getSymbolAddress(B_Base, Layout));
-
- Index = A_Base->getIndex();
- IsExtern = 1;
- Type = MachO::ARM64_RELOC_UNSIGNED;
-
- MachO::any_relocation_info MRE;
- MRE.r_word0 = FixupOffset;
- MRE.r_word1 = ((Index << 0) | (IsPCRel << 24) | (Log2Size << 25) |
- (IsExtern << 27) | (Type << 28));
- Writer->addRelocation(Fragment->getParent(), MRE);
-
- Index = B_Base->getIndex();
- IsExtern = 1;
- Type = MachO::ARM64_RELOC_SUBTRACTOR;
- } else { // A + constant
- const MCSymbol *Symbol = &Target.getSymA()->getSymbol();
- const MCSymbolData &SD = Asm.getSymbolData(*Symbol);
- const MCSymbolData *Base = Asm.getAtom(&SD);
- const MCSectionMachO &Section = static_cast<const MCSectionMachO &>(
- Fragment->getParent()->getSection());
-
- // If the symbol is a variable and we weren't able to get a Base for it
- // (i.e., it's not in the symbol table associated with a section) resolve
- // the relocation based its expansion instead.
- if (Symbol->isVariable() && !Base) {
- // If the evaluation is an absolute value, just use that directly
- // to keep things easy.
- int64_t Res;
- if (SD.getSymbol().getVariableValue()->EvaluateAsAbsolute(
- Res, Layout, Writer->getSectionAddressMap())) {
- FixedValue = Res;
- return;
- }
-
- // FIXME: Will the Target we already have ever have any data in it
- // we need to preserve and merge with the new Target? How about
- // the FixedValue?
- if (!Symbol->getVariableValue()->EvaluateAsRelocatable(Target, &Layout))
- Asm.getContext().FatalError(Fixup.getLoc(),
- "unable to resolve variable '" +
- Symbol->getName() + "'");
- return RecordRelocation(Writer, Asm, Layout, Fragment, Fixup, Target,
- FixedValue);
- }
-
- // Relocations inside debug sections always use local relocations when
- // possible. This seems to be done because the debugger doesn't fully
- // understand relocation entries and expects to find values that
- // have already been fixed up.
- if (Symbol->isInSection()) {
- if (Section.hasAttribute(MachO::S_ATTR_DEBUG))
- Base = nullptr;
- }
-
- // ARM64 uses external relocations as much as possible. For debug sections,
- // and for pointer-sized relocations (.quad), we allow section relocations.
- // It's code sections that run into trouble.
- if (Base) {
- Index = Base->getIndex();
- IsExtern = 1;
-
- // Add the local offset, if needed.
- if (Base != &SD)
- Value += Layout.getSymbolOffset(&SD) - Layout.getSymbolOffset(Base);
- } else if (Symbol->isInSection()) {
- // Pointer-sized relocations can use a local relocation. Otherwise,
- // we have to be in a debug info section.
- if (!Section.hasAttribute(MachO::S_ATTR_DEBUG) && Log2Size != 3)
- Asm.getContext().FatalError(
- Fixup.getLoc(),
- "unsupported relocation of local symbol '" + Symbol->getName() +
- "'. Must have non-local symbol earlier in section.");
- // Adjust the relocation to be section-relative.
- // The index is the section ordinal (1-based).
- const MCSectionData &SymSD =
- Asm.getSectionData(SD.getSymbol().getSection());
- Index = SymSD.getOrdinal() + 1;
- IsExtern = 0;
- Value += Writer->getSymbolAddress(&SD, Layout);
-
- if (IsPCRel)
- Value -= Writer->getFragmentAddress(Fragment, Layout) +
- Fixup.getOffset() + (1ULL << Log2Size);
- } else {
- // Resolve constant variables.
- if (SD.getSymbol().isVariable()) {
- int64_t Res;
- if (SD.getSymbol().getVariableValue()->EvaluateAsAbsolute(
- Res, Layout, Writer->getSectionAddressMap())) {
- FixedValue = Res;
- return;
- }
- }
- Asm.getContext().FatalError(Fixup.getLoc(),
- "unsupported relocation of variable '" +
- Symbol->getName() + "'");
- }
- }
-
- // If the relocation kind is Branch26, Page21, or Pageoff12, any addend
- // is represented via an Addend relocation, not encoded directly into
- // the instruction.
- if ((Type == MachO::ARM64_RELOC_BRANCH26 ||
- Type == MachO::ARM64_RELOC_PAGE21 ||
- Type == MachO::ARM64_RELOC_PAGEOFF12) &&
- Value) {
- assert((Value & 0xff000000) == 0 && "Added relocation out of range!");
-
- MachO::any_relocation_info MRE;
- MRE.r_word0 = FixupOffset;
- MRE.r_word1 = ((Index << 0) | (IsPCRel << 24) | (Log2Size << 25) |
- (IsExtern << 27) | (Type << 28));
- Writer->addRelocation(Fragment->getParent(), MRE);
-
- // Now set up the Addend relocation.
- Type = MachO::ARM64_RELOC_ADDEND;
- Index = Value;
- IsPCRel = 0;
- Log2Size = 2;
- IsExtern = 0;
-
- // Put zero into the instruction itself. The addend is in the relocation.
- Value = 0;
- }
-
- // If there's any addend left to handle, encode it in the instruction.
- FixedValue = Value;
-
- // struct relocation_info (8 bytes)
- MachO::any_relocation_info MRE;
- MRE.r_word0 = FixupOffset;
- MRE.r_word1 = ((Index << 0) | (IsPCRel << 24) | (Log2Size << 25) |
- (IsExtern << 27) | (Type << 28));
- Writer->addRelocation(Fragment->getParent(), MRE);
-}
-
-MCObjectWriter *llvm::createARM64MachObjectWriter(raw_ostream &OS,
- uint32_t CPUType,
- uint32_t CPUSubtype) {
- return createMachObjectWriter(new ARM64MachObjectWriter(CPUType, CPUSubtype),
- OS, /*IsLittleEndian=*/true);
-}
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/CMakeLists.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/CMakeLists.txt (removed)
@@ -1,14 +0,0 @@
-add_llvm_library(LLVMARM64Desc
- ARM64AsmBackend.cpp
- ARM64ELFObjectWriter.cpp
- ARM64ELFStreamer.cpp
- ARM64MCAsmInfo.cpp
- ARM64MCCodeEmitter.cpp
- ARM64MCExpr.cpp
- ARM64MCTargetDesc.cpp
- ARM64MachObjectWriter.cpp
-)
-add_dependencies(LLVMARM64Desc ARM64CommonTableGen)
-
-# Hack: we need to include 'main' target directory to grab private headers
-include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..)
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/LLVMBuild.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/LLVMBuild.txt (removed)
@@ -1,24 +0,0 @@
-;===- ./lib/Target/ARM64/MCTargetDesc/LLVMBuild.txt ------------*- Conf -*--===;
-;
-; The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-; http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = ARM64Desc
-parent = ARM64
-required_libraries = ARM64AsmPrinter ARM64Info MC Support
-add_to_library_groups = ARM64
-
Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/Makefile?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/Makefile (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/Makefile (removed)
@@ -1,16 +0,0 @@
-##===- lib/Target/ARM64/TargetDesc/Makefile ----------------*- Makefile -*-===##
-#
-# The LLVM Compiler Infrastructure
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-##===----------------------------------------------------------------------===##
-
-LEVEL = ../../../..
-LIBRARYNAME = LLVMARM64Desc
-
-# Hack: we need to include 'main' target directory to grab private headers
-CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
-
-include $(LEVEL)/Makefile.common
Removed: llvm/trunk/lib/Target/ARM64/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Makefile?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Makefile (original)
+++ llvm/trunk/lib/Target/ARM64/Makefile (removed)
@@ -1,25 +0,0 @@
-##===- lib/Target/ARM64/Makefile ---------------------------*- Makefile -*-===##
-#
-# The LLVM Compiler Infrastructure
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-##===----------------------------------------------------------------------===##
-
-LEVEL = ../../..
-LIBRARYNAME = LLVMARM64CodeGen
-TARGET = ARM64
-
-# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = ARM64GenRegisterInfo.inc ARM64GenInstrInfo.inc \
- ARM64GenAsmWriter.inc ARM64GenAsmWriter1.inc \
- ARM64GenDAGISel.inc \
- ARM64GenCallingConv.inc ARM64GenAsmMatcher.inc \
- ARM64GenSubtargetInfo.inc ARM64GenMCCodeEmitter.inc \
- ARM64GenFastISel.inc ARM64GenDisassemblerTables.inc \
- ARM64GenMCPseudoLowering.inc
-
-DIRS = TargetInfo InstPrinter AsmParser Disassembler MCTargetDesc Utils
-
-include $(LEVEL)/Makefile.common
Removed: llvm/trunk/lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp (removed)
@@ -1,31 +0,0 @@
-//===-- ARM64TargetInfo.cpp - ARM64 Target Implementation -----------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/ADT/Triple.h"
-#include "llvm/Support/TargetRegistry.h"
-using namespace llvm;
-
-namespace llvm {
-Target TheARM64leTarget;
-Target TheARM64beTarget;
-Target TheAArch64leTarget;
-Target TheAArch64beTarget;
-} // end namespace llvm
-
-extern "C" void LLVMInitializeARM64TargetInfo() {
- RegisterTarget<Triple::arm64, /*HasJIT=*/true> X(TheARM64leTarget, "arm64",
- "ARM64 (little endian)");
- RegisterTarget<Triple::arm64_be, /*HasJIT=*/true> Y(TheARM64beTarget, "arm64_be",
- "ARM64 (big endian)");
-
- RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z(
- TheAArch64leTarget, "aarch64", "ARM64 (little endian)");
- RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W(
- TheAArch64beTarget, "aarch64_be", "ARM64 (big endian)");
-}
Removed: llvm/trunk/lib/Target/ARM64/TargetInfo/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/TargetInfo/CMakeLists.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/TargetInfo/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM64/TargetInfo/CMakeLists.txt (removed)
@@ -1,7 +0,0 @@
-include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
-
-add_llvm_library(LLVMARM64Info
- ARM64TargetInfo.cpp
- )
-
-add_dependencies(LLVMARM64Info ARM64CommonTableGen)
Removed: llvm/trunk/lib/Target/ARM64/TargetInfo/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/TargetInfo/LLVMBuild.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/TargetInfo/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/ARM64/TargetInfo/LLVMBuild.txt (removed)
@@ -1,23 +0,0 @@
-;===- ./lib/Target/ARM64/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===;
-;
-; The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-; http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = ARM64Info
-parent = ARM64
-required_libraries = Support
-add_to_library_groups = ARM64
Removed: llvm/trunk/lib/Target/ARM64/TargetInfo/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/TargetInfo/Makefile?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/TargetInfo/Makefile (original)
+++ llvm/trunk/lib/Target/ARM64/TargetInfo/Makefile (removed)
@@ -1,15 +0,0 @@
-##===- lib/Target/ARM64/TargetInfo/Makefile ----------------*- Makefile -*-===##
-#
-# The LLVM Compiler Infrastructure
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-##===----------------------------------------------------------------------===##
-LEVEL = ../../../..
-LIBRARYNAME = LLVMARM64Info
-
-# Hack: we need to include 'main' target directory to grab private headers
-CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
-
-include $(LEVEL)/Makefile.common
Removed: llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp (removed)
@@ -1,901 +0,0 @@
-//===-- ARM64BaseInfo.cpp - ARM64 Base encoding information------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides basic encoding and assembly information for ARM64.
-//
-//===----------------------------------------------------------------------===//
-#include "ARM64BaseInfo.h"
-#include "llvm/ADT/APFloat.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringExtras.h"
-#include "llvm/Support/Regex.h"
-
-using namespace llvm;
-
-StringRef ARM64NamedImmMapper::toString(uint32_t Value, bool &Valid) const {
- for (unsigned i = 0; i < NumPairs; ++i) {
- if (Pairs[i].Value == Value) {
- Valid = true;
- return Pairs[i].Name;
- }
- }
-
- Valid = false;
- return StringRef();
-}
-
-uint32_t ARM64NamedImmMapper::fromString(StringRef Name, bool &Valid) const {
- std::string LowerCaseName = Name.lower();
- for (unsigned i = 0; i < NumPairs; ++i) {
- if (Pairs[i].Name == LowerCaseName) {
- Valid = true;
- return Pairs[i].Value;
- }
- }
-
- Valid = false;
- return -1;
-}
-
-bool ARM64NamedImmMapper::validImm(uint32_t Value) const {
- return Value < TooBigImm;
-}
-
-const ARM64NamedImmMapper::Mapping ARM64AT::ATMapper::ATPairs[] = {
- {"s1e1r", S1E1R},
- {"s1e2r", S1E2R},
- {"s1e3r", S1E3R},
- {"s1e1w", S1E1W},
- {"s1e2w", S1E2W},
- {"s1e3w", S1E3W},
- {"s1e0r", S1E0R},
- {"s1e0w", S1E0W},
- {"s12e1r", S12E1R},
- {"s12e1w", S12E1W},
- {"s12e0r", S12E0R},
- {"s12e0w", S12E0W},
-};
-
-ARM64AT::ATMapper::ATMapper()
- : ARM64NamedImmMapper(ATPairs, 0) {}
-
-const ARM64NamedImmMapper::Mapping ARM64DB::DBarrierMapper::DBarrierPairs[] = {
- {"oshld", OSHLD},
- {"oshst", OSHST},
- {"osh", OSH},
- {"nshld", NSHLD},
- {"nshst", NSHST},
- {"nsh", NSH},
- {"ishld", ISHLD},
- {"ishst", ISHST},
- {"ish", ISH},
- {"ld", LD},
- {"st", ST},
- {"sy", SY}
-};
-
-ARM64DB::DBarrierMapper::DBarrierMapper()
- : ARM64NamedImmMapper(DBarrierPairs, 16u) {}
-
-const ARM64NamedImmMapper::Mapping ARM64DC::DCMapper::DCPairs[] = {
- {"zva", ZVA},
- {"ivac", IVAC},
- {"isw", ISW},
- {"cvac", CVAC},
- {"csw", CSW},
- {"cvau", CVAU},
- {"civac", CIVAC},
- {"cisw", CISW}
-};
-
-ARM64DC::DCMapper::DCMapper()
- : ARM64NamedImmMapper(DCPairs, 0) {}
-
-const ARM64NamedImmMapper::Mapping ARM64IC::ICMapper::ICPairs[] = {
- {"ialluis", IALLUIS},
- {"iallu", IALLU},
- {"ivau", IVAU}
-};
-
-ARM64IC::ICMapper::ICMapper()
- : ARM64NamedImmMapper(ICPairs, 0) {}
-
-const ARM64NamedImmMapper::Mapping ARM64ISB::ISBMapper::ISBPairs[] = {
- {"sy", SY},
-};
-
-ARM64ISB::ISBMapper::ISBMapper()
- : ARM64NamedImmMapper(ISBPairs, 16) {}
-
-const ARM64NamedImmMapper::Mapping ARM64PRFM::PRFMMapper::PRFMPairs[] = {
- {"pldl1keep", PLDL1KEEP},
- {"pldl1strm", PLDL1STRM},
- {"pldl2keep", PLDL2KEEP},
- {"pldl2strm", PLDL2STRM},
- {"pldl3keep", PLDL3KEEP},
- {"pldl3strm", PLDL3STRM},
- {"plil1keep", PLIL1KEEP},
- {"plil1strm", PLIL1STRM},
- {"plil2keep", PLIL2KEEP},
- {"plil2strm", PLIL2STRM},
- {"plil3keep", PLIL3KEEP},
- {"plil3strm", PLIL3STRM},
- {"pstl1keep", PSTL1KEEP},
- {"pstl1strm", PSTL1STRM},
- {"pstl2keep", PSTL2KEEP},
- {"pstl2strm", PSTL2STRM},
- {"pstl3keep", PSTL3KEEP},
- {"pstl3strm", PSTL3STRM}
-};
-
-ARM64PRFM::PRFMMapper::PRFMMapper()
- : ARM64NamedImmMapper(PRFMPairs, 32) {}
-
-const ARM64NamedImmMapper::Mapping ARM64PState::PStateMapper::PStatePairs[] = {
- {"spsel", SPSel},
- {"daifset", DAIFSet},
- {"daifclr", DAIFClr}
-};
-
-ARM64PState::PStateMapper::PStateMapper()
- : ARM64NamedImmMapper(PStatePairs, 0) {}
-
-const ARM64NamedImmMapper::Mapping ARM64SysReg::MRSMapper::MRSPairs[] = {
- {"mdccsr_el0", MDCCSR_EL0},
- {"dbgdtrrx_el0", DBGDTRRX_EL0},
- {"mdrar_el1", MDRAR_EL1},
- {"oslsr_el1", OSLSR_EL1},
- {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1},
- {"pmceid0_el0", PMCEID0_EL0},
- {"pmceid1_el0", PMCEID1_EL0},
- {"midr_el1", MIDR_EL1},
- {"ccsidr_el1", CCSIDR_EL1},
- {"clidr_el1", CLIDR_EL1},
- {"ctr_el0", CTR_EL0},
- {"mpidr_el1", MPIDR_EL1},
- {"revidr_el1", REVIDR_EL1},
- {"aidr_el1", AIDR_EL1},
- {"dczid_el0", DCZID_EL0},
- {"id_pfr0_el1", ID_PFR0_EL1},
- {"id_pfr1_el1", ID_PFR1_EL1},
- {"id_dfr0_el1", ID_DFR0_EL1},
- {"id_afr0_el1", ID_AFR0_EL1},
- {"id_mmfr0_el1", ID_MMFR0_EL1},
- {"id_mmfr1_el1", ID_MMFR1_EL1},
- {"id_mmfr2_el1", ID_MMFR2_EL1},
- {"id_mmfr3_el1", ID_MMFR3_EL1},
- {"id_isar0_el1", ID_ISAR0_EL1},
- {"id_isar1_el1", ID_ISAR1_EL1},
- {"id_isar2_el1", ID_ISAR2_EL1},
- {"id_isar3_el1", ID_ISAR3_EL1},
- {"id_isar4_el1", ID_ISAR4_EL1},
- {"id_isar5_el1", ID_ISAR5_EL1},
- {"id_aa64pfr0_el1", ID_AARM64PFR0_EL1},
- {"id_aa64pfr1_el1", ID_AARM64PFR1_EL1},
- {"id_aa64dfr0_el1", ID_AARM64DFR0_EL1},
- {"id_aa64dfr1_el1", ID_AARM64DFR1_EL1},
- {"id_aa64afr0_el1", ID_AARM64AFR0_EL1},
- {"id_aa64afr1_el1", ID_AARM64AFR1_EL1},
- {"id_aa64isar0_el1", ID_AARM64ISAR0_EL1},
- {"id_aa64isar1_el1", ID_AARM64ISAR1_EL1},
- {"id_aa64mmfr0_el1", ID_AARM64MMFR0_EL1},
- {"id_aa64mmfr1_el1", ID_AARM64MMFR1_EL1},
- {"mvfr0_el1", MVFR0_EL1},
- {"mvfr1_el1", MVFR1_EL1},
- {"mvfr2_el1", MVFR2_EL1},
- {"rvbar_el1", RVBAR_EL1},
- {"rvbar_el2", RVBAR_EL2},
- {"rvbar_el3", RVBAR_EL3},
- {"isr_el1", ISR_EL1},
- {"cntpct_el0", CNTPCT_EL0},
- {"cntvct_el0", CNTVCT_EL0},
-
- // Trace registers
- {"trcstatr", TRCSTATR},
- {"trcidr8", TRCIDR8},
- {"trcidr9", TRCIDR9},
- {"trcidr10", TRCIDR10},
- {"trcidr11", TRCIDR11},
- {"trcidr12", TRCIDR12},
- {"trcidr13", TRCIDR13},
- {"trcidr0", TRCIDR0},
- {"trcidr1", TRCIDR1},
- {"trcidr2", TRCIDR2},
- {"trcidr3", TRCIDR3},
- {"trcidr4", TRCIDR4},
- {"trcidr5", TRCIDR5},
- {"trcidr6", TRCIDR6},
- {"trcidr7", TRCIDR7},
- {"trcoslsr", TRCOSLSR},
- {"trcpdsr", TRCPDSR},
- {"trcdevaff0", TRCDEVAFF0},
- {"trcdevaff1", TRCDEVAFF1},
- {"trclsr", TRCLSR},
- {"trcauthstatus", TRCAUTHSTATUS},
- {"trcdevarch", TRCDEVARCH},
- {"trcdevid", TRCDEVID},
- {"trcdevtype", TRCDEVTYPE},
- {"trcpidr4", TRCPIDR4},
- {"trcpidr5", TRCPIDR5},
- {"trcpidr6", TRCPIDR6},
- {"trcpidr7", TRCPIDR7},
- {"trcpidr0", TRCPIDR0},
- {"trcpidr1", TRCPIDR1},
- {"trcpidr2", TRCPIDR2},
- {"trcpidr3", TRCPIDR3},
- {"trccidr0", TRCCIDR0},
- {"trccidr1", TRCCIDR1},
- {"trccidr2", TRCCIDR2},
- {"trccidr3", TRCCIDR3},
-
- // GICv3 registers
- {"icc_iar1_el1", ICC_IAR1_EL1},
- {"icc_iar0_el1", ICC_IAR0_EL1},
- {"icc_hppir1_el1", ICC_HPPIR1_EL1},
- {"icc_hppir0_el1", ICC_HPPIR0_EL1},
- {"icc_rpr_el1", ICC_RPR_EL1},
- {"ich_vtr_el2", ICH_VTR_EL2},
- {"ich_eisr_el2", ICH_EISR_EL2},
- {"ich_elsr_el2", ICH_ELSR_EL2}
-};
-
-ARM64SysReg::MRSMapper::MRSMapper(uint64_t FeatureBits)
- : SysRegMapper(FeatureBits) {
- InstPairs = &MRSPairs[0];
- NumInstPairs = llvm::array_lengthof(MRSPairs);
-}
-
-const ARM64NamedImmMapper::Mapping ARM64SysReg::MSRMapper::MSRPairs[] = {
- {"dbgdtrtx_el0", DBGDTRTX_EL0},
- {"oslar_el1", OSLAR_EL1},
- {"pmswinc_el0", PMSWINC_EL0},
-
- // Trace registers
- {"trcoslar", TRCOSLAR},
- {"trclar", TRCLAR},
-
- // GICv3 registers
- {"icc_eoir1_el1", ICC_EOIR1_EL1},
- {"icc_eoir0_el1", ICC_EOIR0_EL1},
- {"icc_dir_el1", ICC_DIR_EL1},
- {"icc_sgi1r_el1", ICC_SGI1R_EL1},
- {"icc_asgi1r_el1", ICC_ASGI1R_EL1},
- {"icc_sgi0r_el1", ICC_SGI0R_EL1}
-};
-
-ARM64SysReg::MSRMapper::MSRMapper(uint64_t FeatureBits)
- : SysRegMapper(FeatureBits) {
- InstPairs = &MSRPairs[0];
- NumInstPairs = llvm::array_lengthof(MSRPairs);
-}
-
-
-const ARM64NamedImmMapper::Mapping ARM64SysReg::SysRegMapper::SysRegPairs[] = {
- {"osdtrrx_el1", OSDTRRX_EL1},
- {"osdtrtx_el1", OSDTRTX_EL1},
- {"teecr32_el1", TEECR32_EL1},
- {"mdccint_el1", MDCCINT_EL1},
- {"mdscr_el1", MDSCR_EL1},
- {"dbgdtr_el0", DBGDTR_EL0},
- {"oseccr_el1", OSECCR_EL1},
- {"dbgvcr32_el2", DBGVCR32_EL2},
- {"dbgbvr0_el1", DBGBVR0_EL1},
- {"dbgbvr1_el1", DBGBVR1_EL1},
- {"dbgbvr2_el1", DBGBVR2_EL1},
- {"dbgbvr3_el1", DBGBVR3_EL1},
- {"dbgbvr4_el1", DBGBVR4_EL1},
- {"dbgbvr5_el1", DBGBVR5_EL1},
- {"dbgbvr6_el1", DBGBVR6_EL1},
- {"dbgbvr7_el1", DBGBVR7_EL1},
- {"dbgbvr8_el1", DBGBVR8_EL1},
- {"dbgbvr9_el1", DBGBVR9_EL1},
- {"dbgbvr10_el1", DBGBVR10_EL1},
- {"dbgbvr11_el1", DBGBVR11_EL1},
- {"dbgbvr12_el1", DBGBVR12_EL1},
- {"dbgbvr13_el1", DBGBVR13_EL1},
- {"dbgbvr14_el1", DBGBVR14_EL1},
- {"dbgbvr15_el1", DBGBVR15_EL1},
- {"dbgbcr0_el1", DBGBCR0_EL1},
- {"dbgbcr1_el1", DBGBCR1_EL1},
- {"dbgbcr2_el1", DBGBCR2_EL1},
- {"dbgbcr3_el1", DBGBCR3_EL1},
- {"dbgbcr4_el1", DBGBCR4_EL1},
- {"dbgbcr5_el1", DBGBCR5_EL1},
- {"dbgbcr6_el1", DBGBCR6_EL1},
- {"dbgbcr7_el1", DBGBCR7_EL1},
- {"dbgbcr8_el1", DBGBCR8_EL1},
- {"dbgbcr9_el1", DBGBCR9_EL1},
- {"dbgbcr10_el1", DBGBCR10_EL1},
- {"dbgbcr11_el1", DBGBCR11_EL1},
- {"dbgbcr12_el1", DBGBCR12_EL1},
- {"dbgbcr13_el1", DBGBCR13_EL1},
- {"dbgbcr14_el1", DBGBCR14_EL1},
- {"dbgbcr15_el1", DBGBCR15_EL1},
- {"dbgwvr0_el1", DBGWVR0_EL1},
- {"dbgwvr1_el1", DBGWVR1_EL1},
- {"dbgwvr2_el1", DBGWVR2_EL1},
- {"dbgwvr3_el1", DBGWVR3_EL1},
- {"dbgwvr4_el1", DBGWVR4_EL1},
- {"dbgwvr5_el1", DBGWVR5_EL1},
- {"dbgwvr6_el1", DBGWVR6_EL1},
- {"dbgwvr7_el1", DBGWVR7_EL1},
- {"dbgwvr8_el1", DBGWVR8_EL1},
- {"dbgwvr9_el1", DBGWVR9_EL1},
- {"dbgwvr10_el1", DBGWVR10_EL1},
- {"dbgwvr11_el1", DBGWVR11_EL1},
- {"dbgwvr12_el1", DBGWVR12_EL1},
- {"dbgwvr13_el1", DBGWVR13_EL1},
- {"dbgwvr14_el1", DBGWVR14_EL1},
- {"dbgwvr15_el1", DBGWVR15_EL1},
- {"dbgwcr0_el1", DBGWCR0_EL1},
- {"dbgwcr1_el1", DBGWCR1_EL1},
- {"dbgwcr2_el1", DBGWCR2_EL1},
- {"dbgwcr3_el1", DBGWCR3_EL1},
- {"dbgwcr4_el1", DBGWCR4_EL1},
- {"dbgwcr5_el1", DBGWCR5_EL1},
- {"dbgwcr6_el1", DBGWCR6_EL1},
- {"dbgwcr7_el1", DBGWCR7_EL1},
- {"dbgwcr8_el1", DBGWCR8_EL1},
- {"dbgwcr9_el1", DBGWCR9_EL1},
- {"dbgwcr10_el1", DBGWCR10_EL1},
- {"dbgwcr11_el1", DBGWCR11_EL1},
- {"dbgwcr12_el1", DBGWCR12_EL1},
- {"dbgwcr13_el1", DBGWCR13_EL1},
- {"dbgwcr14_el1", DBGWCR14_EL1},
- {"dbgwcr15_el1", DBGWCR15_EL1},
- {"teehbr32_el1", TEEHBR32_EL1},
- {"osdlr_el1", OSDLR_EL1},
- {"dbgprcr_el1", DBGPRCR_EL1},
- {"dbgclaimset_el1", DBGCLAIMSET_EL1},
- {"dbgclaimclr_el1", DBGCLAIMCLR_EL1},
- {"csselr_el1", CSSELR_EL1},
- {"vpidr_el2", VPIDR_EL2},
- {"vmpidr_el2", VMPIDR_EL2},
- {"sctlr_el1", SCTLR_EL1},
- {"sctlr_el2", SCTLR_EL2},
- {"sctlr_el3", SCTLR_EL3},
- {"actlr_el1", ACTLR_EL1},
- {"actlr_el2", ACTLR_EL2},
- {"actlr_el3", ACTLR_EL3},
- {"cpacr_el1", CPACR_EL1},
- {"hcr_el2", HCR_EL2},
- {"scr_el3", SCR_EL3},
- {"mdcr_el2", MDCR_EL2},
- {"sder32_el3", SDER32_EL3},
- {"cptr_el2", CPTR_EL2},
- {"cptr_el3", CPTR_EL3},
- {"hstr_el2", HSTR_EL2},
- {"hacr_el2", HACR_EL2},
- {"mdcr_el3", MDCR_EL3},
- {"ttbr0_el1", TTBR0_EL1},
- {"ttbr0_el2", TTBR0_EL2},
- {"ttbr0_el3", TTBR0_EL3},
- {"ttbr1_el1", TTBR1_EL1},
- {"tcr_el1", TCR_EL1},
- {"tcr_el2", TCR_EL2},
- {"tcr_el3", TCR_EL3},
- {"vttbr_el2", VTTBR_EL2},
- {"vtcr_el2", VTCR_EL2},
- {"dacr32_el2", DACR32_EL2},
- {"spsr_el1", SPSR_EL1},
- {"spsr_el2", SPSR_EL2},
- {"spsr_el3", SPSR_EL3},
- {"elr_el1", ELR_EL1},
- {"elr_el2", ELR_EL2},
- {"elr_el3", ELR_EL3},
- {"sp_el0", SP_EL0},
- {"sp_el1", SP_EL1},
- {"sp_el2", SP_EL2},
- {"spsel", SPSel},
- {"nzcv", NZCV},
- {"daif", DAIF},
- {"currentel", CurrentEL},
- {"spsr_irq", SPSR_irq},
- {"spsr_abt", SPSR_abt},
- {"spsr_und", SPSR_und},
- {"spsr_fiq", SPSR_fiq},
- {"fpcr", FPCR},
- {"fpsr", FPSR},
- {"dspsr_el0", DSPSR_EL0},
- {"dlr_el0", DLR_EL0},
- {"ifsr32_el2", IFSR32_EL2},
- {"afsr0_el1", AFSR0_EL1},
- {"afsr0_el2", AFSR0_EL2},
- {"afsr0_el3", AFSR0_EL3},
- {"afsr1_el1", AFSR1_EL1},
- {"afsr1_el2", AFSR1_EL2},
- {"afsr1_el3", AFSR1_EL3},
- {"esr_el1", ESR_EL1},
- {"esr_el2", ESR_EL2},
- {"esr_el3", ESR_EL3},
- {"fpexc32_el2", FPEXC32_EL2},
- {"far_el1", FAR_EL1},
- {"far_el2", FAR_EL2},
- {"far_el3", FAR_EL3},
- {"hpfar_el2", HPFAR_EL2},
- {"par_el1", PAR_EL1},
- {"pmcr_el0", PMCR_EL0},
- {"pmcntenset_el0", PMCNTENSET_EL0},
- {"pmcntenclr_el0", PMCNTENCLR_EL0},
- {"pmovsclr_el0", PMOVSCLR_EL0},
- {"pmselr_el0", PMSELR_EL0},
- {"pmccntr_el0", PMCCNTR_EL0},
- {"pmxevtyper_el0", PMXEVTYPER_EL0},
- {"pmxevcntr_el0", PMXEVCNTR_EL0},
- {"pmuserenr_el0", PMUSERENR_EL0},
- {"pmintenset_el1", PMINTENSET_EL1},
- {"pmintenclr_el1", PMINTENCLR_EL1},
- {"pmovsset_el0", PMOVSSET_EL0},
- {"mair_el1", MAIR_EL1},
- {"mair_el2", MAIR_EL2},
- {"mair_el3", MAIR_EL3},
- {"amair_el1", AMAIR_EL1},
- {"amair_el2", AMAIR_EL2},
- {"amair_el3", AMAIR_EL3},
- {"vbar_el1", VBAR_EL1},
- {"vbar_el2", VBAR_EL2},
- {"vbar_el3", VBAR_EL3},
- {"rmr_el1", RMR_EL1},
- {"rmr_el2", RMR_EL2},
- {"rmr_el3", RMR_EL3},
- {"contextidr_el1", CONTEXTIDR_EL1},
- {"tpidr_el0", TPIDR_EL0},
- {"tpidr_el2", TPIDR_EL2},
- {"tpidr_el3", TPIDR_EL3},
- {"tpidrro_el0", TPIDRRO_EL0},
- {"tpidr_el1", TPIDR_EL1},
- {"cntfrq_el0", CNTFRQ_EL0},
- {"cntvoff_el2", CNTVOFF_EL2},
- {"cntkctl_el1", CNTKCTL_EL1},
- {"cnthctl_el2", CNTHCTL_EL2},
- {"cntp_tval_el0", CNTP_TVAL_EL0},
- {"cnthp_tval_el2", CNTHP_TVAL_EL2},
- {"cntps_tval_el1", CNTPS_TVAL_EL1},
- {"cntp_ctl_el0", CNTP_CTL_EL0},
- {"cnthp_ctl_el2", CNTHP_CTL_EL2},
- {"cntps_ctl_el1", CNTPS_CTL_EL1},
- {"cntp_cval_el0", CNTP_CVAL_EL0},
- {"cnthp_cval_el2", CNTHP_CVAL_EL2},
- {"cntps_cval_el1", CNTPS_CVAL_EL1},
- {"cntv_tval_el0", CNTV_TVAL_EL0},
- {"cntv_ctl_el0", CNTV_CTL_EL0},
- {"cntv_cval_el0", CNTV_CVAL_EL0},
- {"pmevcntr0_el0", PMEVCNTR0_EL0},
- {"pmevcntr1_el0", PMEVCNTR1_EL0},
- {"pmevcntr2_el0", PMEVCNTR2_EL0},
- {"pmevcntr3_el0", PMEVCNTR3_EL0},
- {"pmevcntr4_el0", PMEVCNTR4_EL0},
- {"pmevcntr5_el0", PMEVCNTR5_EL0},
- {"pmevcntr6_el0", PMEVCNTR6_EL0},
- {"pmevcntr7_el0", PMEVCNTR7_EL0},
- {"pmevcntr8_el0", PMEVCNTR8_EL0},
- {"pmevcntr9_el0", PMEVCNTR9_EL0},
- {"pmevcntr10_el0", PMEVCNTR10_EL0},
- {"pmevcntr11_el0", PMEVCNTR11_EL0},
- {"pmevcntr12_el0", PMEVCNTR12_EL0},
- {"pmevcntr13_el0", PMEVCNTR13_EL0},
- {"pmevcntr14_el0", PMEVCNTR14_EL0},
- {"pmevcntr15_el0", PMEVCNTR15_EL0},
- {"pmevcntr16_el0", PMEVCNTR16_EL0},
- {"pmevcntr17_el0", PMEVCNTR17_EL0},
- {"pmevcntr18_el0", PMEVCNTR18_EL0},
- {"pmevcntr19_el0", PMEVCNTR19_EL0},
- {"pmevcntr20_el0", PMEVCNTR20_EL0},
- {"pmevcntr21_el0", PMEVCNTR21_EL0},
- {"pmevcntr22_el0", PMEVCNTR22_EL0},
- {"pmevcntr23_el0", PMEVCNTR23_EL0},
- {"pmevcntr24_el0", PMEVCNTR24_EL0},
- {"pmevcntr25_el0", PMEVCNTR25_EL0},
- {"pmevcntr26_el0", PMEVCNTR26_EL0},
- {"pmevcntr27_el0", PMEVCNTR27_EL0},
- {"pmevcntr28_el0", PMEVCNTR28_EL0},
- {"pmevcntr29_el0", PMEVCNTR29_EL0},
- {"pmevcntr30_el0", PMEVCNTR30_EL0},
- {"pmccfiltr_el0", PMCCFILTR_EL0},
- {"pmevtyper0_el0", PMEVTYPER0_EL0},
- {"pmevtyper1_el0", PMEVTYPER1_EL0},
- {"pmevtyper2_el0", PMEVTYPER2_EL0},
- {"pmevtyper3_el0", PMEVTYPER3_EL0},
- {"pmevtyper4_el0", PMEVTYPER4_EL0},
- {"pmevtyper5_el0", PMEVTYPER5_EL0},
- {"pmevtyper6_el0", PMEVTYPER6_EL0},
- {"pmevtyper7_el0", PMEVTYPER7_EL0},
- {"pmevtyper8_el0", PMEVTYPER8_EL0},
- {"pmevtyper9_el0", PMEVTYPER9_EL0},
- {"pmevtyper10_el0", PMEVTYPER10_EL0},
- {"pmevtyper11_el0", PMEVTYPER11_EL0},
- {"pmevtyper12_el0", PMEVTYPER12_EL0},
- {"pmevtyper13_el0", PMEVTYPER13_EL0},
- {"pmevtyper14_el0", PMEVTYPER14_EL0},
- {"pmevtyper15_el0", PMEVTYPER15_EL0},
- {"pmevtyper16_el0", PMEVTYPER16_EL0},
- {"pmevtyper17_el0", PMEVTYPER17_EL0},
- {"pmevtyper18_el0", PMEVTYPER18_EL0},
- {"pmevtyper19_el0", PMEVTYPER19_EL0},
- {"pmevtyper20_el0", PMEVTYPER20_EL0},
- {"pmevtyper21_el0", PMEVTYPER21_EL0},
- {"pmevtyper22_el0", PMEVTYPER22_EL0},
- {"pmevtyper23_el0", PMEVTYPER23_EL0},
- {"pmevtyper24_el0", PMEVTYPER24_EL0},
- {"pmevtyper25_el0", PMEVTYPER25_EL0},
- {"pmevtyper26_el0", PMEVTYPER26_EL0},
- {"pmevtyper27_el0", PMEVTYPER27_EL0},
- {"pmevtyper28_el0", PMEVTYPER28_EL0},
- {"pmevtyper29_el0", PMEVTYPER29_EL0},
- {"pmevtyper30_el0", PMEVTYPER30_EL0},
-
- // Trace registers
- {"trcprgctlr", TRCPRGCTLR},
- {"trcprocselr", TRCPROCSELR},
- {"trcconfigr", TRCCONFIGR},
- {"trcauxctlr", TRCAUXCTLR},
- {"trceventctl0r", TRCEVENTCTL0R},
- {"trceventctl1r", TRCEVENTCTL1R},
- {"trcstallctlr", TRCSTALLCTLR},
- {"trctsctlr", TRCTSCTLR},
- {"trcsyncpr", TRCSYNCPR},
- {"trcccctlr", TRCCCCTLR},
- {"trcbbctlr", TRCBBCTLR},
- {"trctraceidr", TRCTRACEIDR},
- {"trcqctlr", TRCQCTLR},
- {"trcvictlr", TRCVICTLR},
- {"trcviiectlr", TRCVIIECTLR},
- {"trcvissctlr", TRCVISSCTLR},
- {"trcvipcssctlr", TRCVIPCSSCTLR},
- {"trcvdctlr", TRCVDCTLR},
- {"trcvdsacctlr", TRCVDSACCTLR},
- {"trcvdarcctlr", TRCVDARCCTLR},
- {"trcseqevr0", TRCSEQEVR0},
- {"trcseqevr1", TRCSEQEVR1},
- {"trcseqevr2", TRCSEQEVR2},
- {"trcseqrstevr", TRCSEQRSTEVR},
- {"trcseqstr", TRCSEQSTR},
- {"trcextinselr", TRCEXTINSELR},
- {"trccntrldvr0", TRCCNTRLDVR0},
- {"trccntrldvr1", TRCCNTRLDVR1},
- {"trccntrldvr2", TRCCNTRLDVR2},
- {"trccntrldvr3", TRCCNTRLDVR3},
- {"trccntctlr0", TRCCNTCTLR0},
- {"trccntctlr1", TRCCNTCTLR1},
- {"trccntctlr2", TRCCNTCTLR2},
- {"trccntctlr3", TRCCNTCTLR3},
- {"trccntvr0", TRCCNTVR0},
- {"trccntvr1", TRCCNTVR1},
- {"trccntvr2", TRCCNTVR2},
- {"trccntvr3", TRCCNTVR3},
- {"trcimspec0", TRCIMSPEC0},
- {"trcimspec1", TRCIMSPEC1},
- {"trcimspec2", TRCIMSPEC2},
- {"trcimspec3", TRCIMSPEC3},
- {"trcimspec4", TRCIMSPEC4},
- {"trcimspec5", TRCIMSPEC5},
- {"trcimspec6", TRCIMSPEC6},
- {"trcimspec7", TRCIMSPEC7},
- {"trcrsctlr2", TRCRSCTLR2},
- {"trcrsctlr3", TRCRSCTLR3},
- {"trcrsctlr4", TRCRSCTLR4},
- {"trcrsctlr5", TRCRSCTLR5},
- {"trcrsctlr6", TRCRSCTLR6},
- {"trcrsctlr7", TRCRSCTLR7},
- {"trcrsctlr8", TRCRSCTLR8},
- {"trcrsctlr9", TRCRSCTLR9},
- {"trcrsctlr10", TRCRSCTLR10},
- {"trcrsctlr11", TRCRSCTLR11},
- {"trcrsctlr12", TRCRSCTLR12},
- {"trcrsctlr13", TRCRSCTLR13},
- {"trcrsctlr14", TRCRSCTLR14},
- {"trcrsctlr15", TRCRSCTLR15},
- {"trcrsctlr16", TRCRSCTLR16},
- {"trcrsctlr17", TRCRSCTLR17},
- {"trcrsctlr18", TRCRSCTLR18},
- {"trcrsctlr19", TRCRSCTLR19},
- {"trcrsctlr20", TRCRSCTLR20},
- {"trcrsctlr21", TRCRSCTLR21},
- {"trcrsctlr22", TRCRSCTLR22},
- {"trcrsctlr23", TRCRSCTLR23},
- {"trcrsctlr24", TRCRSCTLR24},
- {"trcrsctlr25", TRCRSCTLR25},
- {"trcrsctlr26", TRCRSCTLR26},
- {"trcrsctlr27", TRCRSCTLR27},
- {"trcrsctlr28", TRCRSCTLR28},
- {"trcrsctlr29", TRCRSCTLR29},
- {"trcrsctlr30", TRCRSCTLR30},
- {"trcrsctlr31", TRCRSCTLR31},
- {"trcssccr0", TRCSSCCR0},
- {"trcssccr1", TRCSSCCR1},
- {"trcssccr2", TRCSSCCR2},
- {"trcssccr3", TRCSSCCR3},
- {"trcssccr4", TRCSSCCR4},
- {"trcssccr5", TRCSSCCR5},
- {"trcssccr6", TRCSSCCR6},
- {"trcssccr7", TRCSSCCR7},
- {"trcsscsr0", TRCSSCSR0},
- {"trcsscsr1", TRCSSCSR1},
- {"trcsscsr2", TRCSSCSR2},
- {"trcsscsr3", TRCSSCSR3},
- {"trcsscsr4", TRCSSCSR4},
- {"trcsscsr5", TRCSSCSR5},
- {"trcsscsr6", TRCSSCSR6},
- {"trcsscsr7", TRCSSCSR7},
- {"trcsspcicr0", TRCSSPCICR0},
- {"trcsspcicr1", TRCSSPCICR1},
- {"trcsspcicr2", TRCSSPCICR2},
- {"trcsspcicr3", TRCSSPCICR3},
- {"trcsspcicr4", TRCSSPCICR4},
- {"trcsspcicr5", TRCSSPCICR5},
- {"trcsspcicr6", TRCSSPCICR6},
- {"trcsspcicr7", TRCSSPCICR7},
- {"trcpdcr", TRCPDCR},
- {"trcacvr0", TRCACVR0},
- {"trcacvr1", TRCACVR1},
- {"trcacvr2", TRCACVR2},
- {"trcacvr3", TRCACVR3},
- {"trcacvr4", TRCACVR4},
- {"trcacvr5", TRCACVR5},
- {"trcacvr6", TRCACVR6},
- {"trcacvr7", TRCACVR7},
- {"trcacvr8", TRCACVR8},
- {"trcacvr9", TRCACVR9},
- {"trcacvr10", TRCACVR10},
- {"trcacvr11", TRCACVR11},
- {"trcacvr12", TRCACVR12},
- {"trcacvr13", TRCACVR13},
- {"trcacvr14", TRCACVR14},
- {"trcacvr15", TRCACVR15},
- {"trcacatr0", TRCACATR0},
- {"trcacatr1", TRCACATR1},
- {"trcacatr2", TRCACATR2},
- {"trcacatr3", TRCACATR3},
- {"trcacatr4", TRCACATR4},
- {"trcacatr5", TRCACATR5},
- {"trcacatr6", TRCACATR6},
- {"trcacatr7", TRCACATR7},
- {"trcacatr8", TRCACATR8},
- {"trcacatr9", TRCACATR9},
- {"trcacatr10", TRCACATR10},
- {"trcacatr11", TRCACATR11},
- {"trcacatr12", TRCACATR12},
- {"trcacatr13", TRCACATR13},
- {"trcacatr14", TRCACATR14},
- {"trcacatr15", TRCACATR15},
- {"trcdvcvr0", TRCDVCVR0},
- {"trcdvcvr1", TRCDVCVR1},
- {"trcdvcvr2", TRCDVCVR2},
- {"trcdvcvr3", TRCDVCVR3},
- {"trcdvcvr4", TRCDVCVR4},
- {"trcdvcvr5", TRCDVCVR5},
- {"trcdvcvr6", TRCDVCVR6},
- {"trcdvcvr7", TRCDVCVR7},
- {"trcdvcmr0", TRCDVCMR0},
- {"trcdvcmr1", TRCDVCMR1},
- {"trcdvcmr2", TRCDVCMR2},
- {"trcdvcmr3", TRCDVCMR3},
- {"trcdvcmr4", TRCDVCMR4},
- {"trcdvcmr5", TRCDVCMR5},
- {"trcdvcmr6", TRCDVCMR6},
- {"trcdvcmr7", TRCDVCMR7},
- {"trccidcvr0", TRCCIDCVR0},
- {"trccidcvr1", TRCCIDCVR1},
- {"trccidcvr2", TRCCIDCVR2},
- {"trccidcvr3", TRCCIDCVR3},
- {"trccidcvr4", TRCCIDCVR4},
- {"trccidcvr5", TRCCIDCVR5},
- {"trccidcvr6", TRCCIDCVR6},
- {"trccidcvr7", TRCCIDCVR7},
- {"trcvmidcvr0", TRCVMIDCVR0},
- {"trcvmidcvr1", TRCVMIDCVR1},
- {"trcvmidcvr2", TRCVMIDCVR2},
- {"trcvmidcvr3", TRCVMIDCVR3},
- {"trcvmidcvr4", TRCVMIDCVR4},
- {"trcvmidcvr5", TRCVMIDCVR5},
- {"trcvmidcvr6", TRCVMIDCVR6},
- {"trcvmidcvr7", TRCVMIDCVR7},
- {"trccidcctlr0", TRCCIDCCTLR0},
- {"trccidcctlr1", TRCCIDCCTLR1},
- {"trcvmidcctlr0", TRCVMIDCCTLR0},
- {"trcvmidcctlr1", TRCVMIDCCTLR1},
- {"trcitctrl", TRCITCTRL},
- {"trcclaimset", TRCCLAIMSET},
- {"trcclaimclr", TRCCLAIMCLR},
-
- // GICv3 registers
- {"icc_bpr1_el1", ICC_BPR1_EL1},
- {"icc_bpr0_el1", ICC_BPR0_EL1},
- {"icc_pmr_el1", ICC_PMR_EL1},
- {"icc_ctlr_el1", ICC_CTLR_EL1},
- {"icc_ctlr_el3", ICC_CTLR_EL3},
- {"icc_sre_el1", ICC_SRE_EL1},
- {"icc_sre_el2", ICC_SRE_EL2},
- {"icc_sre_el3", ICC_SRE_EL3},
- {"icc_igrpen0_el1", ICC_IGRPEN0_EL1},
- {"icc_igrpen1_el1", ICC_IGRPEN1_EL1},
- {"icc_igrpen1_el3", ICC_IGRPEN1_EL3},
- {"icc_seien_el1", ICC_SEIEN_EL1},
- {"icc_ap0r0_el1", ICC_AP0R0_EL1},
- {"icc_ap0r1_el1", ICC_AP0R1_EL1},
- {"icc_ap0r2_el1", ICC_AP0R2_EL1},
- {"icc_ap0r3_el1", ICC_AP0R3_EL1},
- {"icc_ap1r0_el1", ICC_AP1R0_EL1},
- {"icc_ap1r1_el1", ICC_AP1R1_EL1},
- {"icc_ap1r2_el1", ICC_AP1R2_EL1},
- {"icc_ap1r3_el1", ICC_AP1R3_EL1},
- {"ich_ap0r0_el2", ICH_AP0R0_EL2},
- {"ich_ap0r1_el2", ICH_AP0R1_EL2},
- {"ich_ap0r2_el2", ICH_AP0R2_EL2},
- {"ich_ap0r3_el2", ICH_AP0R3_EL2},
- {"ich_ap1r0_el2", ICH_AP1R0_EL2},
- {"ich_ap1r1_el2", ICH_AP1R1_EL2},
- {"ich_ap1r2_el2", ICH_AP1R2_EL2},
- {"ich_ap1r3_el2", ICH_AP1R3_EL2},
- {"ich_hcr_el2", ICH_HCR_EL2},
- {"ich_misr_el2", ICH_MISR_EL2},
- {"ich_vmcr_el2", ICH_VMCR_EL2},
- {"ich_vseir_el2", ICH_VSEIR_EL2},
- {"ich_lr0_el2", ICH_LR0_EL2},
- {"ich_lr1_el2", ICH_LR1_EL2},
- {"ich_lr2_el2", ICH_LR2_EL2},
- {"ich_lr3_el2", ICH_LR3_EL2},
- {"ich_lr4_el2", ICH_LR4_EL2},
- {"ich_lr5_el2", ICH_LR5_EL2},
- {"ich_lr6_el2", ICH_LR6_EL2},
- {"ich_lr7_el2", ICH_LR7_EL2},
- {"ich_lr8_el2", ICH_LR8_EL2},
- {"ich_lr9_el2", ICH_LR9_EL2},
- {"ich_lr10_el2", ICH_LR10_EL2},
- {"ich_lr11_el2", ICH_LR11_EL2},
- {"ich_lr12_el2", ICH_LR12_EL2},
- {"ich_lr13_el2", ICH_LR13_EL2},
- {"ich_lr14_el2", ICH_LR14_EL2},
- {"ich_lr15_el2", ICH_LR15_EL2}
-};
-
-const ARM64NamedImmMapper::Mapping
-ARM64SysReg::SysRegMapper::CycloneSysRegPairs[] = {
- {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3}
-};
-
-uint32_t
-ARM64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
- std::string NameLower = Name.lower();
-
- // First search the registers shared by all
- for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
- if (SysRegPairs[i].Name == NameLower) {
- Valid = true;
- return SysRegPairs[i].Value;
- }
- }
-
- // Next search for target specific registers
- if (FeatureBits & ARM64::ProcCyclone) {
- for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
- if (CycloneSysRegPairs[i].Name == NameLower) {
- Valid = true;
- return CycloneSysRegPairs[i].Value;
- }
- }
- }
-
- // Now try the instruction-specific registers (either read-only or
- // write-only).
- for (unsigned i = 0; i < NumInstPairs; ++i) {
- if (InstPairs[i].Name == NameLower) {
- Valid = true;
- return InstPairs[i].Value;
- }
- }
-
- // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits
- // are: 11 xxx 1x11 xxxx xxx
- Regex GenericRegPattern("^s3_([0-7])_c(1[15])_c([0-9]|1[0-5])_([0-7])$");
-
- SmallVector<StringRef, 4> Ops;
- if (!GenericRegPattern.match(NameLower, &Ops)) {
- Valid = false;
- return -1;
- }
-
- uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
- uint32_t Bits;
- Ops[1].getAsInteger(10, Op1);
- Ops[2].getAsInteger(10, CRn);
- Ops[3].getAsInteger(10, CRm);
- Ops[4].getAsInteger(10, Op2);
- Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
-
- Valid = true;
- return Bits;
-}
-
-std::string
-ARM64SysReg::SysRegMapper::toString(uint32_t Bits, bool &Valid) const {
- // First search the registers shared by all
- for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
- if (SysRegPairs[i].Value == Bits) {
- Valid = true;
- return SysRegPairs[i].Name;
- }
- }
-
- // Next search for target specific registers
- if (FeatureBits & ARM64::ProcCyclone) {
- for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
- if (CycloneSysRegPairs[i].Value == Bits) {
- Valid = true;
- return CycloneSysRegPairs[i].Name;
- }
- }
- }
-
- // Now try the instruction-specific registers (either read-only or
- // write-only).
- for (unsigned i = 0; i < NumInstPairs; ++i) {
- if (InstPairs[i].Value == Bits) {
- Valid = true;
- return InstPairs[i].Name;
- }
- }
-
- uint32_t Op0 = (Bits >> 14) & 0x3;
- uint32_t Op1 = (Bits >> 11) & 0x7;
- uint32_t CRn = (Bits >> 7) & 0xf;
- uint32_t CRm = (Bits >> 3) & 0xf;
- uint32_t Op2 = Bits & 0x7;
-
- // Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
- // name.
- if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
- Valid = false;
- return "";
- }
-
- assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
-
- Valid = true;
- return "s3_" + utostr(Op1) + "_c" + utostr(CRn)
- + "_c" + utostr(CRm) + "_" + utostr(Op2);
-}
-
-const ARM64NamedImmMapper::Mapping ARM64TLBI::TLBIMapper::TLBIPairs[] = {
- {"ipas2e1is", IPAS2E1IS},
- {"ipas2le1is", IPAS2LE1IS},
- {"vmalle1is", VMALLE1IS},
- {"alle2is", ALLE2IS},
- {"alle3is", ALLE3IS},
- {"vae1is", VAE1IS},
- {"vae2is", VAE2IS},
- {"vae3is", VAE3IS},
- {"aside1is", ASIDE1IS},
- {"vaae1is", VAAE1IS},
- {"alle1is", ALLE1IS},
- {"vale1is", VALE1IS},
- {"vale2is", VALE2IS},
- {"vale3is", VALE3IS},
- {"vmalls12e1is", VMALLS12E1IS},
- {"vaale1is", VAALE1IS},
- {"ipas2e1", IPAS2E1},
- {"ipas2le1", IPAS2LE1},
- {"vmalle1", VMALLE1},
- {"alle2", ALLE2},
- {"alle3", ALLE3},
- {"vae1", VAE1},
- {"vae2", VAE2},
- {"vae3", VAE3},
- {"aside1", ASIDE1},
- {"vaae1", VAAE1},
- {"alle1", ALLE1},
- {"vale1", VALE1},
- {"vale2", VALE2},
- {"vale3", VALE3},
- {"vmalls12e1", VMALLS12E1},
- {"vaale1", VAALE1}
-};
-
-ARM64TLBI::TLBIMapper::TLBIMapper()
- : ARM64NamedImmMapper(TLBIPairs, 0) {}
Removed: llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h (original)
+++ llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h (removed)
@@ -1,1294 +0,0 @@
-//===-- ARM64BaseInfo.h - Top level definitions for ARM64 -------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains small standalone helper functions and enum definitions for
-// the ARM64 target useful for the compiler back-end and the MC libraries.
-// As such, it deliberately does not include references to LLVM core
-// code gen types, passes, etc..
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ARM64BASEINFO_H
-#define ARM64BASEINFO_H
-
-// FIXME: Is it easiest to fix this layering violation by moving the .inc
-// #includes from ARM64MCTargetDesc.h to here?
-#include "MCTargetDesc/ARM64MCTargetDesc.h" // For ARM64::X0 and friends.
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/StringSwitch.h"
-#include "llvm/Support/ErrorHandling.h"
-
-namespace llvm {
-
-inline static unsigned getWRegFromXReg(unsigned Reg) {
- switch (Reg) {
- case ARM64::X0: return ARM64::W0;
- case ARM64::X1: return ARM64::W1;
- case ARM64::X2: return ARM64::W2;
- case ARM64::X3: return ARM64::W3;
- case ARM64::X4: return ARM64::W4;
- case ARM64::X5: return ARM64::W5;
- case ARM64::X6: return ARM64::W6;
- case ARM64::X7: return ARM64::W7;
- case ARM64::X8: return ARM64::W8;
- case ARM64::X9: return ARM64::W9;
- case ARM64::X10: return ARM64::W10;
- case ARM64::X11: return ARM64::W11;
- case ARM64::X12: return ARM64::W12;
- case ARM64::X13: return ARM64::W13;
- case ARM64::X14: return ARM64::W14;
- case ARM64::X15: return ARM64::W15;
- case ARM64::X16: return ARM64::W16;
- case ARM64::X17: return ARM64::W17;
- case ARM64::X18: return ARM64::W18;
- case ARM64::X19: return ARM64::W19;
- case ARM64::X20: return ARM64::W20;
- case ARM64::X21: return ARM64::W21;
- case ARM64::X22: return ARM64::W22;
- case ARM64::X23: return ARM64::W23;
- case ARM64::X24: return ARM64::W24;
- case ARM64::X25: return ARM64::W25;
- case ARM64::X26: return ARM64::W26;
- case ARM64::X27: return ARM64::W27;
- case ARM64::X28: return ARM64::W28;
- case ARM64::FP: return ARM64::W29;
- case ARM64::LR: return ARM64::W30;
- case ARM64::SP: return ARM64::WSP;
- case ARM64::XZR: return ARM64::WZR;
- }
- // For anything else, return it unchanged.
- return Reg;
-}
-
-inline static unsigned getXRegFromWReg(unsigned Reg) {
- switch (Reg) {
- case ARM64::W0: return ARM64::X0;
- case ARM64::W1: return ARM64::X1;
- case ARM64::W2: return ARM64::X2;
- case ARM64::W3: return ARM64::X3;
- case ARM64::W4: return ARM64::X4;
- case ARM64::W5: return ARM64::X5;
- case ARM64::W6: return ARM64::X6;
- case ARM64::W7: return ARM64::X7;
- case ARM64::W8: return ARM64::X8;
- case ARM64::W9: return ARM64::X9;
- case ARM64::W10: return ARM64::X10;
- case ARM64::W11: return ARM64::X11;
- case ARM64::W12: return ARM64::X12;
- case ARM64::W13: return ARM64::X13;
- case ARM64::W14: return ARM64::X14;
- case ARM64::W15: return ARM64::X15;
- case ARM64::W16: return ARM64::X16;
- case ARM64::W17: return ARM64::X17;
- case ARM64::W18: return ARM64::X18;
- case ARM64::W19: return ARM64::X19;
- case ARM64::W20: return ARM64::X20;
- case ARM64::W21: return ARM64::X21;
- case ARM64::W22: return ARM64::X22;
- case ARM64::W23: return ARM64::X23;
- case ARM64::W24: return ARM64::X24;
- case ARM64::W25: return ARM64::X25;
- case ARM64::W26: return ARM64::X26;
- case ARM64::W27: return ARM64::X27;
- case ARM64::W28: return ARM64::X28;
- case ARM64::W29: return ARM64::FP;
- case ARM64::W30: return ARM64::LR;
- case ARM64::WSP: return ARM64::SP;
- case ARM64::WZR: return ARM64::XZR;
- }
- // For anything else, return it unchanged.
- return Reg;
-}
-
-static inline unsigned getBRegFromDReg(unsigned Reg) {
- switch (Reg) {
- case ARM64::D0: return ARM64::B0;
- case ARM64::D1: return ARM64::B1;
- case ARM64::D2: return ARM64::B2;
- case ARM64::D3: return ARM64::B3;
- case ARM64::D4: return ARM64::B4;
- case ARM64::D5: return ARM64::B5;
- case ARM64::D6: return ARM64::B6;
- case ARM64::D7: return ARM64::B7;
- case ARM64::D8: return ARM64::B8;
- case ARM64::D9: return ARM64::B9;
- case ARM64::D10: return ARM64::B10;
- case ARM64::D11: return ARM64::B11;
- case ARM64::D12: return ARM64::B12;
- case ARM64::D13: return ARM64::B13;
- case ARM64::D14: return ARM64::B14;
- case ARM64::D15: return ARM64::B15;
- case ARM64::D16: return ARM64::B16;
- case ARM64::D17: return ARM64::B17;
- case ARM64::D18: return ARM64::B18;
- case ARM64::D19: return ARM64::B19;
- case ARM64::D20: return ARM64::B20;
- case ARM64::D21: return ARM64::B21;
- case ARM64::D22: return ARM64::B22;
- case ARM64::D23: return ARM64::B23;
- case ARM64::D24: return ARM64::B24;
- case ARM64::D25: return ARM64::B25;
- case ARM64::D26: return ARM64::B26;
- case ARM64::D27: return ARM64::B27;
- case ARM64::D28: return ARM64::B28;
- case ARM64::D29: return ARM64::B29;
- case ARM64::D30: return ARM64::B30;
- case ARM64::D31: return ARM64::B31;
- }
- // For anything else, return it unchanged.
- return Reg;
-}
-
-
-static inline unsigned getDRegFromBReg(unsigned Reg) {
- switch (Reg) {
- case ARM64::B0: return ARM64::D0;
- case ARM64::B1: return ARM64::D1;
- case ARM64::B2: return ARM64::D2;
- case ARM64::B3: return ARM64::D3;
- case ARM64::B4: return ARM64::D4;
- case ARM64::B5: return ARM64::D5;
- case ARM64::B6: return ARM64::D6;
- case ARM64::B7: return ARM64::D7;
- case ARM64::B8: return ARM64::D8;
- case ARM64::B9: return ARM64::D9;
- case ARM64::B10: return ARM64::D10;
- case ARM64::B11: return ARM64::D11;
- case ARM64::B12: return ARM64::D12;
- case ARM64::B13: return ARM64::D13;
- case ARM64::B14: return ARM64::D14;
- case ARM64::B15: return ARM64::D15;
- case ARM64::B16: return ARM64::D16;
- case ARM64::B17: return ARM64::D17;
- case ARM64::B18: return ARM64::D18;
- case ARM64::B19: return ARM64::D19;
- case ARM64::B20: return ARM64::D20;
- case ARM64::B21: return ARM64::D21;
- case ARM64::B22: return ARM64::D22;
- case ARM64::B23: return ARM64::D23;
- case ARM64::B24: return ARM64::D24;
- case ARM64::B25: return ARM64::D25;
- case ARM64::B26: return ARM64::D26;
- case ARM64::B27: return ARM64::D27;
- case ARM64::B28: return ARM64::D28;
- case ARM64::B29: return ARM64::D29;
- case ARM64::B30: return ARM64::D30;
- case ARM64::B31: return ARM64::D31;
- }
- // For anything else, return it unchanged.
- return Reg;
-}
-
-namespace ARM64CC {
-
-// The CondCodes constants map directly to the 4-bit encoding of the condition
-// field for predicated instructions.
-enum CondCode { // Meaning (integer) Meaning (floating-point)
- EQ = 0x0, // Equal Equal
- NE = 0x1, // Not equal Not equal, or unordered
- HS = 0x2, // Unsigned higher or same >, ==, or unordered
- LO = 0x3, // Unsigned lower Less than
- MI = 0x4, // Minus, negative Less than
- PL = 0x5, // Plus, positive or zero >, ==, or unordered
- VS = 0x6, // Overflow Unordered
- VC = 0x7, // No overflow Not unordered
- HI = 0x8, // Unsigned higher Greater than, or unordered
- LS = 0x9, // Unsigned lower or same Less than or equal
- GE = 0xa, // Greater than or equal Greater than or equal
- LT = 0xb, // Less than Less than, or unordered
- GT = 0xc, // Greater than Greater than
- LE = 0xd, // Less than or equal <, ==, or unordered
- AL = 0xe, // Always (unconditional) Always (unconditional)
- NV = 0xf, // Always (unconditional) Always (unconditional)
- // Note the NV exists purely to disassemble 0b1111. Execution is "always".
- Invalid
-};
-
-inline static const char *getCondCodeName(CondCode Code) {
- switch (Code) {
- default: llvm_unreachable("Unknown condition code");
- case EQ: return "eq";
- case NE: return "ne";
- case HS: return "hs";
- case LO: return "lo";
- case MI: return "mi";
- case PL: return "pl";
- case VS: return "vs";
- case VC: return "vc";
- case HI: return "hi";
- case LS: return "ls";
- case GE: return "ge";
- case LT: return "lt";
- case GT: return "gt";
- case LE: return "le";
- case AL: return "al";
- case NV: return "nv";
- }
-}
-
-inline static CondCode getInvertedCondCode(CondCode Code) {
- switch (Code) {
- default: llvm_unreachable("Unknown condition code");
- case EQ: return NE;
- case NE: return EQ;
- case HS: return LO;
- case LO: return HS;
- case MI: return PL;
- case PL: return MI;
- case VS: return VC;
- case VC: return VS;
- case HI: return LS;
- case LS: return HI;
- case GE: return LT;
- case LT: return GE;
- case GT: return LE;
- case LE: return GT;
- }
-}
-
-/// Given a condition code, return NZCV flags that would satisfy that condition.
-/// The flag bits are in the format expected by the ccmp instructions.
-/// Note that many different flag settings can satisfy a given condition code,
-/// this function just returns one of them.
-inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
- // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
- enum { N = 8, Z = 4, C = 2, V = 1 };
- switch (Code) {
- default: llvm_unreachable("Unknown condition code");
- case EQ: return Z; // Z == 1
- case NE: return 0; // Z == 0
- case HS: return C; // C == 1
- case LO: return 0; // C == 0
- case MI: return N; // N == 1
- case PL: return 0; // N == 0
- case VS: return V; // V == 1
- case VC: return 0; // V == 0
- case HI: return C; // C == 1 && Z == 0
- case LS: return 0; // C == 0 || Z == 1
- case GE: return 0; // N == V
- case LT: return N; // N != V
- case GT: return 0; // Z == 0 && N == V
- case LE: return Z; // Z == 1 || N != V
- }
-}
-} // end namespace ARM64CC
-
-/// Instances of this class can perform bidirectional mapping from random
-/// identifier strings to operand encodings. For example "MSR" takes a named
-/// system-register which must be encoded somehow and decoded for printing. This
-/// central location means that the information for those transformations is not
-/// duplicated and remains in sync.
-///
-/// FIXME: currently the algorithm is a completely unoptimised linear
-/// search. Obviously this could be improved, but we would probably want to work
-/// out just how often these instructions are emitted before working on it. It
-/// might even be optimal to just reorder the tables for the common instructions
-/// rather than changing the algorithm.
-struct ARM64NamedImmMapper {
- struct Mapping {
- const char *Name;
- uint32_t Value;
- };
-
- template<int N>
- ARM64NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm)
- : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {}
-
- StringRef toString(uint32_t Value, bool &Valid) const;
- uint32_t fromString(StringRef Name, bool &Valid) const;
-
- /// Many of the instructions allow an alternative assembly form consisting of
- /// a simple immediate. Currently the only valid forms are ranges [0, N) where
- /// N being 0 indicates no immediate syntax-form is allowed.
- bool validImm(uint32_t Value) const;
-protected:
- const Mapping *Pairs;
- size_t NumPairs;
- uint32_t TooBigImm;
-};
-
-namespace ARM64AT {
- enum ATValues {
- Invalid = -1, // Op0 Op1 CRn CRm Op2
- S1E1R = 0x43c0, // 01 000 0111 1000 000
- S1E2R = 0x63c0, // 01 100 0111 1000 000
- S1E3R = 0x73c0, // 01 110 0111 1000 000
- S1E1W = 0x43c1, // 01 000 0111 1000 001
- S1E2W = 0x63c1, // 01 100 0111 1000 001
- S1E3W = 0x73c1, // 01 110 0111 1000 001
- S1E0R = 0x43c2, // 01 000 0111 1000 010
- S1E0W = 0x43c3, // 01 000 0111 1000 011
- S12E1R = 0x63c4, // 01 100 0111 1000 100
- S12E1W = 0x63c5, // 01 100 0111 1000 101
- S12E0R = 0x63c6, // 01 100 0111 1000 110
- S12E0W = 0x63c7 // 01 100 0111 1000 111
- };
-
- struct ATMapper : ARM64NamedImmMapper {
- const static Mapping ATPairs[];
-
- ATMapper();
- };
-
-}
-namespace ARM64DB {
- enum DBValues {
- Invalid = -1,
- OSHLD = 0x1,
- OSHST = 0x2,
- OSH = 0x3,
- NSHLD = 0x5,
- NSHST = 0x6,
- NSH = 0x7,
- ISHLD = 0x9,
- ISHST = 0xa,
- ISH = 0xb,
- LD = 0xd,
- ST = 0xe,
- SY = 0xf
- };
-
- struct DBarrierMapper : ARM64NamedImmMapper {
- const static Mapping DBarrierPairs[];
-
- DBarrierMapper();
- };
-}
-
-namespace ARM64DC {
- enum DCValues {
- Invalid = -1, // Op1 CRn CRm Op2
- ZVA = 0x5ba1, // 01 011 0111 0100 001
- IVAC = 0x43b1, // 01 000 0111 0110 001
- ISW = 0x43b2, // 01 000 0111 0110 010
- CVAC = 0x5bd1, // 01 011 0111 1010 001
- CSW = 0x43d2, // 01 000 0111 1010 010
- CVAU = 0x5bd9, // 01 011 0111 1011 001
- CIVAC = 0x5bf1, // 01 011 0111 1110 001
- CISW = 0x43f2 // 01 000 0111 1110 010
- };
-
- struct DCMapper : ARM64NamedImmMapper {
- const static Mapping DCPairs[];
-
- DCMapper();
- };
-
-}
-
-namespace ARM64IC {
- enum ICValues {
- Invalid = -1, // Op1 CRn CRm Op2
- IALLUIS = 0x0388, // 000 0111 0001 000
- IALLU = 0x03a8, // 000 0111 0101 000
- IVAU = 0x1ba9 // 011 0111 0101 001
- };
-
-
- struct ICMapper : ARM64NamedImmMapper {
- const static Mapping ICPairs[];
-
- ICMapper();
- };
-
- static inline bool NeedsRegister(ICValues Val) {
- return Val == IVAU;
- }
-}
-
-namespace ARM64ISB {
- enum ISBValues {
- Invalid = -1,
- SY = 0xf
- };
- struct ISBMapper : ARM64NamedImmMapper {
- const static Mapping ISBPairs[];
-
- ISBMapper();
- };
-}
-
-namespace ARM64PRFM {
- enum PRFMValues {
- Invalid = -1,
- PLDL1KEEP = 0x00,
- PLDL1STRM = 0x01,
- PLDL2KEEP = 0x02,
- PLDL2STRM = 0x03,
- PLDL3KEEP = 0x04,
- PLDL3STRM = 0x05,
- PLIL1KEEP = 0x08,
- PLIL1STRM = 0x09,
- PLIL2KEEP = 0x0a,
- PLIL2STRM = 0x0b,
- PLIL3KEEP = 0x0c,
- PLIL3STRM = 0x0d,
- PSTL1KEEP = 0x10,
- PSTL1STRM = 0x11,
- PSTL2KEEP = 0x12,
- PSTL2STRM = 0x13,
- PSTL3KEEP = 0x14,
- PSTL3STRM = 0x15
- };
-
- struct PRFMMapper : ARM64NamedImmMapper {
- const static Mapping PRFMPairs[];
-
- PRFMMapper();
- };
-}
-
-namespace ARM64PState {
- enum PStateValues {
- Invalid = -1,
- SPSel = 0x05,
- DAIFSet = 0x1e,
- DAIFClr = 0x1f
- };
-
- struct PStateMapper : ARM64NamedImmMapper {
- const static Mapping PStatePairs[];
-
- PStateMapper();
- };
-
-}
-
-namespace ARM64SE {
- enum ShiftExtSpecifiers {
- Invalid = -1,
- LSL,
- MSL,
- LSR,
- ASR,
- ROR,
-
- UXTB,
- UXTH,
- UXTW,
- UXTX,
-
- SXTB,
- SXTH,
- SXTW,
- SXTX
- };
-}
-
-namespace ARM64Layout {
- enum VectorLayout {
- Invalid = -1,
- VL_8B,
- VL_4H,
- VL_2S,
- VL_1D,
-
- VL_16B,
- VL_8H,
- VL_4S,
- VL_2D,
-
- // Bare layout for the 128-bit vector
- // (only show ".b", ".h", ".s", ".d" without vector number)
- VL_B,
- VL_H,
- VL_S,
- VL_D
- };
-}
-
-inline static const char *
-ARM64VectorLayoutToString(ARM64Layout::VectorLayout Layout) {
- switch (Layout) {
- case ARM64Layout::VL_8B: return ".8b";
- case ARM64Layout::VL_4H: return ".4h";
- case ARM64Layout::VL_2S: return ".2s";
- case ARM64Layout::VL_1D: return ".1d";
- case ARM64Layout::VL_16B: return ".16b";
- case ARM64Layout::VL_8H: return ".8h";
- case ARM64Layout::VL_4S: return ".4s";
- case ARM64Layout::VL_2D: return ".2d";
- case ARM64Layout::VL_B: return ".b";
- case ARM64Layout::VL_H: return ".h";
- case ARM64Layout::VL_S: return ".s";
- case ARM64Layout::VL_D: return ".d";
- default: llvm_unreachable("Unknown Vector Layout");
- }
-}
-
-inline static ARM64Layout::VectorLayout
-ARM64StringToVectorLayout(StringRef LayoutStr) {
- return StringSwitch<ARM64Layout::VectorLayout>(LayoutStr)
- .Case(".8b", ARM64Layout::VL_8B)
- .Case(".4h", ARM64Layout::VL_4H)
- .Case(".2s", ARM64Layout::VL_2S)
- .Case(".1d", ARM64Layout::VL_1D)
- .Case(".16b", ARM64Layout::VL_16B)
- .Case(".8h", ARM64Layout::VL_8H)
- .Case(".4s", ARM64Layout::VL_4S)
- .Case(".2d", ARM64Layout::VL_2D)
- .Case(".b", ARM64Layout::VL_B)
- .Case(".h", ARM64Layout::VL_H)
- .Case(".s", ARM64Layout::VL_S)
- .Case(".d", ARM64Layout::VL_D)
- .Default(ARM64Layout::Invalid);
-}
-
-namespace ARM64SysReg {
- enum SysRegROValues {
- MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
- DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
- MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
- OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
- DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
- PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
- PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
- MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
- CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
- CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
- CTR_EL0 = 0xd801, // 11 011 0000 0000 001
- MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
- REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
- AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
- DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
- ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
- ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
- ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
- ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
- ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
- ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
- ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
- ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
- ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
- ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
- ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
- ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
- ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
- ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
- ID_AARM64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
- ID_AARM64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
- ID_AARM64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
- ID_AARM64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
- ID_AARM64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
- ID_AARM64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
- ID_AARM64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
- ID_AARM64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
- ID_AARM64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
- ID_AARM64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
- MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
- MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
- MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
- RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
- RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
- RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
- ISR_EL1 = 0xc608, // 11 000 1100 0001 000
- CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
- CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
-
- // Trace registers
- TRCSTATR = 0x8818, // 10 001 0000 0011 000
- TRCIDR8 = 0x8806, // 10 001 0000 0000 110
- TRCIDR9 = 0x880e, // 10 001 0000 0001 110
- TRCIDR10 = 0x8816, // 10 001 0000 0010 110
- TRCIDR11 = 0x881e, // 10 001 0000 0011 110
- TRCIDR12 = 0x8826, // 10 001 0000 0100 110
- TRCIDR13 = 0x882e, // 10 001 0000 0101 110
- TRCIDR0 = 0x8847, // 10 001 0000 1000 111
- TRCIDR1 = 0x884f, // 10 001 0000 1001 111
- TRCIDR2 = 0x8857, // 10 001 0000 1010 111
- TRCIDR3 = 0x885f, // 10 001 0000 1011 111
- TRCIDR4 = 0x8867, // 10 001 0000 1100 111
- TRCIDR5 = 0x886f, // 10 001 0000 1101 111
- TRCIDR6 = 0x8877, // 10 001 0000 1110 111
- TRCIDR7 = 0x887f, // 10 001 0000 1111 111
- TRCOSLSR = 0x888c, // 10 001 0001 0001 100
- TRCPDSR = 0x88ac, // 10 001 0001 0101 100
- TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
- TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
- TRCLSR = 0x8bee, // 10 001 0111 1101 110
- TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
- TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
- TRCDEVID = 0x8b97, // 10 001 0111 0010 111
- TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
- TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
- TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
- TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
- TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
- TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
- TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
- TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
- TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
- TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
- TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
- TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
- TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
-
- // GICv3 registers
- ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
- ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
- ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
- ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
- ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
- ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
- ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
- ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
- };
-
- enum SysRegWOValues {
- DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
- OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
- PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
-
- // Trace Registers
- TRCOSLAR = 0x8884, // 10 001 0001 0000 100
- TRCLAR = 0x8be6, // 10 001 0111 1100 110
-
- // GICv3 registers
- ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
- ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
- ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
- ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
- ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
- ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
- };
-
- enum SysRegValues {
- Invalid = -1, // Op0 Op1 CRn CRm Op2
- OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
- OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
- TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
- MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
- MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
- DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
- OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
- DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
- DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
- DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
- DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
- DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
- DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
- DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
- DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
- DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
- DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
- DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
- DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
- DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
- DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
- DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
- DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
- DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
- DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
- DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
- DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
- DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
- DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
- DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
- DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
- DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
- DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
- DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
- DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
- DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
- DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
- DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
- DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
- DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
- DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
- DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
- DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
- DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
- DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
- DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
- DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
- DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
- DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
- DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
- DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
- DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
- DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
- DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
- DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
- DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
- DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
- DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
- DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
- DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
- DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
- DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
- DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
- DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
- DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
- DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
- DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
- DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
- DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
- DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
- DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
- DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
- TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
- OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
- DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
- DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
- DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
- CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
- VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
- VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
- CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
- SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
- SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
- SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
- ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
- ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
- ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
- HCR_EL2 = 0xe088, // 11 100 0001 0001 000
- SCR_EL3 = 0xf088, // 11 110 0001 0001 000
- MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
- SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
- CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
- CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
- HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
- HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
- MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
- TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
- TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
- TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
- TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
- TCR_EL1 = 0xc102, // 11 000 0010 0000 010
- TCR_EL2 = 0xe102, // 11 100 0010 0000 010
- TCR_EL3 = 0xf102, // 11 110 0010 0000 010
- VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
- VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
- DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
- SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
- SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
- SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
- ELR_EL1 = 0xc201, // 11 000 0100 0000 001
- ELR_EL2 = 0xe201, // 11 100 0100 0000 001
- ELR_EL3 = 0xf201, // 11 110 0100 0000 001
- SP_EL0 = 0xc208, // 11 000 0100 0001 000
- SP_EL1 = 0xe208, // 11 100 0100 0001 000
- SP_EL2 = 0xf208, // 11 110 0100 0001 000
- SPSel = 0xc210, // 11 000 0100 0010 000
- NZCV = 0xda10, // 11 011 0100 0010 000
- DAIF = 0xda11, // 11 011 0100 0010 001
- CurrentEL = 0xc212, // 11 000 0100 0010 010
- SPSR_irq = 0xe218, // 11 100 0100 0011 000
- SPSR_abt = 0xe219, // 11 100 0100 0011 001
- SPSR_und = 0xe21a, // 11 100 0100 0011 010
- SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
- FPCR = 0xda20, // 11 011 0100 0100 000
- FPSR = 0xda21, // 11 011 0100 0100 001
- DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
- DLR_EL0 = 0xda29, // 11 011 0100 0101 001
- IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
- AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
- AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
- AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
- AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
- AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
- AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
- ESR_EL1 = 0xc290, // 11 000 0101 0010 000
- ESR_EL2 = 0xe290, // 11 100 0101 0010 000
- ESR_EL3 = 0xf290, // 11 110 0101 0010 000
- FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
- FAR_EL1 = 0xc300, // 11 000 0110 0000 000
- FAR_EL2 = 0xe300, // 11 100 0110 0000 000
- FAR_EL3 = 0xf300, // 11 110 0110 0000 000
- HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
- PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
- PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
- PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
- PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
- PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
- PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
- PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
- PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
- PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
- PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
- PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
- PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
- PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
- MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
- MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
- MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
- AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
- AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
- AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
- VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
- VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
- VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
- RMR_EL1 = 0xc602, // 11 000 1100 0000 010
- RMR_EL2 = 0xe602, // 11 100 1100 0000 010
- RMR_EL3 = 0xf602, // 11 110 1100 0000 010
- CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
- TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
- TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
- TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
- TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
- TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
- CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
- CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
- CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
- CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
- CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
- CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
- CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
- CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
- CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
- CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
- CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
- CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
- CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
- CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
- CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
- CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
- PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
- PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
- PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
- PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
- PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
- PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
- PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
- PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
- PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
- PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
- PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
- PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
- PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
- PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
- PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
- PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
- PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
- PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
- PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
- PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
- PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
- PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
- PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
- PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
- PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
- PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
- PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
- PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
- PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
- PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
- PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
- PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
- PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
- PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
- PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
- PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
- PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
- PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
- PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
- PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
- PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
- PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
- PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
- PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
- PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
- PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
- PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
- PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
- PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
- PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
- PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
- PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
- PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
- PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
- PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
- PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
- PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
- PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
- PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
- PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
- PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
- PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
- PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
-
- // Trace registers
- TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
- TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
- TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
- TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
- TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
- TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
- TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
- TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
- TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
- TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
- TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
- TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
- TRCQCTLR = 0x8809, // 10 001 0000 0001 001
- TRCVICTLR = 0x8802, // 10 001 0000 0000 010
- TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
- TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
- TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
- TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
- TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
- TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
- TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
- TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
- TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
- TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
- TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
- TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
- TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
- TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
- TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
- TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
- TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
- TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
- TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
- TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
- TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
- TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
- TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
- TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
- TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
- TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
- TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
- TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
- TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
- TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
- TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
- TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
- TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
- TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
- TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
- TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
- TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
- TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
- TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
- TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
- TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
- TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
- TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
- TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
- TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
- TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
- TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
- TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
- TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
- TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
- TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
- TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
- TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
- TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
- TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
- TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
- TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
- TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
- TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
- TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
- TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
- TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
- TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
- TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
- TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
- TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
- TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
- TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
- TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
- TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
- TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
- TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
- TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
- TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
- TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
- TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
- TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
- TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
- TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
- TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
- TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
- TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
- TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
- TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
- TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
- TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
- TRCPDCR = 0x88a4, // 10 001 0001 0100 100
- TRCACVR0 = 0x8900, // 10 001 0010 0000 000
- TRCACVR1 = 0x8910, // 10 001 0010 0010 000
- TRCACVR2 = 0x8920, // 10 001 0010 0100 000
- TRCACVR3 = 0x8930, // 10 001 0010 0110 000
- TRCACVR4 = 0x8940, // 10 001 0010 1000 000
- TRCACVR5 = 0x8950, // 10 001 0010 1010 000
- TRCACVR6 = 0x8960, // 10 001 0010 1100 000
- TRCACVR7 = 0x8970, // 10 001 0010 1110 000
- TRCACVR8 = 0x8901, // 10 001 0010 0000 001
- TRCACVR9 = 0x8911, // 10 001 0010 0010 001
- TRCACVR10 = 0x8921, // 10 001 0010 0100 001
- TRCACVR11 = 0x8931, // 10 001 0010 0110 001
- TRCACVR12 = 0x8941, // 10 001 0010 1000 001
- TRCACVR13 = 0x8951, // 10 001 0010 1010 001
- TRCACVR14 = 0x8961, // 10 001 0010 1100 001
- TRCACVR15 = 0x8971, // 10 001 0010 1110 001
- TRCACATR0 = 0x8902, // 10 001 0010 0000 010
- TRCACATR1 = 0x8912, // 10 001 0010 0010 010
- TRCACATR2 = 0x8922, // 10 001 0010 0100 010
- TRCACATR3 = 0x8932, // 10 001 0010 0110 010
- TRCACATR4 = 0x8942, // 10 001 0010 1000 010
- TRCACATR5 = 0x8952, // 10 001 0010 1010 010
- TRCACATR6 = 0x8962, // 10 001 0010 1100 010
- TRCACATR7 = 0x8972, // 10 001 0010 1110 010
- TRCACATR8 = 0x8903, // 10 001 0010 0000 011
- TRCACATR9 = 0x8913, // 10 001 0010 0010 011
- TRCACATR10 = 0x8923, // 10 001 0010 0100 011
- TRCACATR11 = 0x8933, // 10 001 0010 0110 011
- TRCACATR12 = 0x8943, // 10 001 0010 1000 011
- TRCACATR13 = 0x8953, // 10 001 0010 1010 011
- TRCACATR14 = 0x8963, // 10 001 0010 1100 011
- TRCACATR15 = 0x8973, // 10 001 0010 1110 011
- TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
- TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
- TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
- TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
- TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
- TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
- TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
- TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
- TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
- TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
- TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
- TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
- TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
- TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
- TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
- TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
- TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
- TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
- TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
- TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
- TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
- TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
- TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
- TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
- TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
- TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
- TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
- TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
- TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
- TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
- TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
- TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
- TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
- TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
- TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
- TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
- TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
- TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
- TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
-
- // GICv3 registers
- ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
- ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
- ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
- ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
- ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
- ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
- ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
- ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
- ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
- ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
- ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
- ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
- ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
- ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
- ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
- ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
- ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
- ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
- ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
- ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
- ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
- ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
- ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
- ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
- ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
- ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
- ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
- ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
- ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
- ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
- ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
- ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
- ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
- ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
- ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
- ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
- ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
- ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
- ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
- ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
- ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
- ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
- ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
- ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
- ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
- ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
- ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
- ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111
- };
-
- // Cyclone specific system registers
- enum CycloneSysRegValues {
- CPM_IOACC_CTL_EL3 = 0xff90
- };
-
- // Note that these do not inherit from ARM64NamedImmMapper. This class is
- // sufficiently different in its behaviour that I don't believe it's worth
- // burdening the common ARM64NamedImmMapper with abstractions only needed in
- // this one case.
- struct SysRegMapper {
- static const ARM64NamedImmMapper::Mapping SysRegPairs[];
- static const ARM64NamedImmMapper::Mapping CycloneSysRegPairs[];
-
- const ARM64NamedImmMapper::Mapping *InstPairs;
- size_t NumInstPairs;
- uint64_t FeatureBits;
-
- SysRegMapper(uint64_t FeatureBits) : FeatureBits(FeatureBits) { }
- uint32_t fromString(StringRef Name, bool &Valid) const;
- std::string toString(uint32_t Bits, bool &Valid) const;
- };
-
- struct MSRMapper : SysRegMapper {
- static const ARM64NamedImmMapper::Mapping MSRPairs[];
- MSRMapper(uint64_t FeatureBits);
- };
-
- struct MRSMapper : SysRegMapper {
- static const ARM64NamedImmMapper::Mapping MRSPairs[];
- MRSMapper(uint64_t FeatureBits);
- };
-
- uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
-}
-
-namespace ARM64TLBI {
- enum TLBIValues {
- Invalid = -1, // Op0 Op1 CRn CRm Op2
- IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
- IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
- VMALLE1IS = 0x4418, // 01 000 1000 0011 000
- ALLE2IS = 0x6418, // 01 100 1000 0011 000
- ALLE3IS = 0x7418, // 01 110 1000 0011 000
- VAE1IS = 0x4419, // 01 000 1000 0011 001
- VAE2IS = 0x6419, // 01 100 1000 0011 001
- VAE3IS = 0x7419, // 01 110 1000 0011 001
- ASIDE1IS = 0x441a, // 01 000 1000 0011 010
- VAAE1IS = 0x441b, // 01 000 1000 0011 011
- ALLE1IS = 0x641c, // 01 100 1000 0011 100
- VALE1IS = 0x441d, // 01 000 1000 0011 101
- VALE2IS = 0x641d, // 01 100 1000 0011 101
- VALE3IS = 0x741d, // 01 110 1000 0011 101
- VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
- VAALE1IS = 0x441f, // 01 000 1000 0011 111
- IPAS2E1 = 0x6421, // 01 100 1000 0100 001
- IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
- VMALLE1 = 0x4438, // 01 000 1000 0111 000
- ALLE2 = 0x6438, // 01 100 1000 0111 000
- ALLE3 = 0x7438, // 01 110 1000 0111 000
- VAE1 = 0x4439, // 01 000 1000 0111 001
- VAE2 = 0x6439, // 01 100 1000 0111 001
- VAE3 = 0x7439, // 01 110 1000 0111 001
- ASIDE1 = 0x443a, // 01 000 1000 0111 010
- VAAE1 = 0x443b, // 01 000 1000 0111 011
- ALLE1 = 0x643c, // 01 100 1000 0111 100
- VALE1 = 0x443d, // 01 000 1000 0111 101
- VALE2 = 0x643d, // 01 100 1000 0111 101
- VALE3 = 0x743d, // 01 110 1000 0111 101
- VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
- VAALE1 = 0x443f // 01 000 1000 0111 111
- };
-
- struct TLBIMapper : ARM64NamedImmMapper {
- const static Mapping TLBIPairs[];
-
- TLBIMapper();
- };
-
- static inline bool NeedsRegister(TLBIValues Val) {
- switch (Val) {
- case VMALLE1IS:
- case ALLE2IS:
- case ALLE3IS:
- case ALLE1IS:
- case VMALLS12E1IS:
- case VMALLE1:
- case ALLE2:
- case ALLE3:
- case ALLE1:
- case VMALLS12E1:
- return false;
- default:
- return true;
- }
- }
-}
-
-namespace ARM64II {
- /// Target Operand Flag enum.
- enum TOF {
- //===------------------------------------------------------------------===//
- // ARM64 Specific MachineOperand flags.
-
- MO_NO_FLAG,
-
- MO_FRAGMENT = 0x7,
-
- /// MO_PAGE - A symbol operand with this flag represents the pc-relative
- /// offset of the 4K page containing the symbol. This is used with the
- /// ADRP instruction.
- MO_PAGE = 1,
-
- /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
- /// that symbol within a 4K page. This offset is added to the page address
- /// to produce the complete address.
- MO_PAGEOFF = 2,
-
- /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
- /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
- MO_G3 = 3,
-
- /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
- /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
- MO_G2 = 4,
-
- /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
- /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
- MO_G1 = 5,
-
- /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
- /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
- MO_G0 = 6,
-
- /// MO_GOT - This flag indicates that a symbol operand represents the
- /// address of the GOT entry for the symbol, rather than the address of
- /// the symbol itself.
- MO_GOT = 8,
-
- /// MO_NC - Indicates whether the linker is expected to check the symbol
- /// reference for overflow. For example in an ADRP/ADD pair of relocations
- /// the ADRP usually does check, but not the ADD.
- MO_NC = 0x10,
-
- /// MO_TLS - Indicates that the operand being accessed is some kind of
- /// thread-local symbol. On Darwin, only one type of thread-local access
- /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
- /// referee will affect interpretation.
- MO_TLS = 0x20
- };
-} // end namespace ARM64II
-
-} // end namespace llvm
-
-#endif
Removed: llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt (removed)
@@ -1,3 +0,0 @@
-add_llvm_library(LLVMARM64Utils
- ARM64BaseInfo.cpp
- )
Removed: llvm/trunk/lib/Target/ARM64/Utils/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/LLVMBuild.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Utils/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/ARM64/Utils/LLVMBuild.txt (removed)
@@ -1,23 +0,0 @@
-;===- ./lib/Target/ARM64/Utils/LLVMBuild.txt ----------------*- Conf -*--===;
-;
-; The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-; http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = ARM64Utils
-parent = ARM64
-required_libraries = Support
-add_to_library_groups = ARM64
Removed: llvm/trunk/lib/Target/ARM64/Utils/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/Makefile?rev=209576&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Utils/Makefile (original)
+++ llvm/trunk/lib/Target/ARM64/Utils/Makefile (removed)
@@ -1,15 +0,0 @@
-##===- lib/Target/ARM64/Utils/Makefile -------------------*- Makefile -*-===##
-#
-# The LLVM Compiler Infrastructure
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-##===----------------------------------------------------------------------===##
-LEVEL = ../../../..
-LIBRARYNAME = LLVMARM64Utils
-
-# Hack: we need to include 'main' ARM64 target directory to grab private headers
-CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
-
-include $(LEVEL)/Makefile.common
Modified: llvm/trunk/lib/Target/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/lib/Target/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/LLVMBuild.txt Sat May 24 07:50:23 2014
@@ -16,7 +16,7 @@
;===------------------------------------------------------------------------===;
[common]
-subdirectories = ARM ARM64 CppBackend Hexagon MSP430 NVPTX Mips PowerPC R600 Sparc SystemZ X86 XCore
+subdirectories = ARM AArch64 CppBackend Hexagon MSP430 NVPTX Mips PowerPC R600 Sparc SystemZ X86 XCore
; This is a special group whose required libraries are extended (by llvm-build)
; with the best execution engine (the native JIT, if available, or the
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Sat May 24 07:50:23 2014
@@ -836,8 +836,8 @@ Instruction *InstCombiner::visitCallInst
case Intrinsic::arm_neon_vmulls:
case Intrinsic::arm_neon_vmullu:
- case Intrinsic::arm64_neon_smull:
- case Intrinsic::arm64_neon_umull: {
+ case Intrinsic::aarch64_neon_smull:
+ case Intrinsic::aarch64_neon_umull: {
Value *Arg0 = II->getArgOperand(0);
Value *Arg1 = II->getArgOperand(1);
@@ -848,7 +848,7 @@ Instruction *InstCombiner::visitCallInst
// Check for constant LHS & RHS - in this case we just simplify.
bool Zext = (II->getIntrinsicID() == Intrinsic::arm_neon_vmullu ||
- II->getIntrinsicID() == Intrinsic::arm64_neon_umull);
+ II->getIntrinsicID() == Intrinsic::aarch64_neon_umull);
VectorType *NewVT = cast<VectorType>(II->getType());
if (Constant *CV0 = dyn_cast<Constant>(Arg0)) {
if (Constant *CV1 = dyn_cast<Constant>(Arg1)) {
Copied: llvm/trunk/test/Analysis/CostModel/AArch64/lit.local.cfg (from r209576, llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/AArch64/lit.local.cfg?p2=llvm/trunk/test/Analysis/CostModel/AArch64/lit.local.cfg&p1=llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Analysis/CostModel/AArch64/lit.local.cfg Sat May 24 07:50:23 2014
@@ -1,3 +1,3 @@
targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
config.unsupported = True
Copied: llvm/trunk/test/Analysis/CostModel/AArch64/select.ll (from r209576, llvm/trunk/test/Analysis/CostModel/ARM64/select.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/AArch64/select.ll?p2=llvm/trunk/test/Analysis/CostModel/AArch64/select.ll&p1=llvm/trunk/test/Analysis/CostModel/ARM64/select.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/Analysis/CostModel/AArch64/store.ll (from r209576, llvm/trunk/test/Analysis/CostModel/ARM64/store.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/AArch64/store.ll?p2=llvm/trunk/test/Analysis/CostModel/AArch64/store.ll&p1=llvm/trunk/test/Analysis/CostModel/ARM64/store.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg (removed)
@@ -1,3 +0,0 @@
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
Removed: llvm/trunk/test/Analysis/CostModel/ARM64/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/ARM64/select.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/ARM64/select.ll (original)
+++ llvm/trunk/test/Analysis/CostModel/ARM64/select.ll (removed)
@@ -1,38 +0,0 @@
-; RUN: opt < %s -cost-model -analyze -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s
-target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
-
-; CHECK-LABEL: select
-define void @select() {
- ; Scalar values
- ; CHECK: cost of 1 {{.*}} select
- %v1 = select i1 undef, i8 undef, i8 undef
- ; CHECK: cost of 1 {{.*}} select
- %v2 = select i1 undef, i16 undef, i16 undef
- ; CHECK: cost of 1 {{.*}} select
- %v3 = select i1 undef, i32 undef, i32 undef
- ; CHECK: cost of 1 {{.*}} select
- %v4 = select i1 undef, i64 undef, i64 undef
- ; CHECK: cost of 1 {{.*}} select
- %v5 = select i1 undef, float undef, float undef
- ; CHECK: cost of 1 {{.*}} select
- %v6 = select i1 undef, double undef, double undef
-
- ; Vector values - check for vectors that have a high cost because they end up
- ; scalarized.
- ; CHECK: cost of 320 {{.*}} select
- %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef
-
- ; CHECK: cost of 160 {{.*}} select
- %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef
- ; CHECK: cost of 320 {{.*}} select
- %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef
-
- ; CHECK: cost of 80 {{.*}} select
- %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef
- ; CHECK: cost of 160 {{.*}} select
- %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef
- ; CHECK: cost of 320 {{.*}} select
- %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef
-
- ret void
-}
Removed: llvm/trunk/test/Analysis/CostModel/ARM64/store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/ARM64/store.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/ARM64/store.ll (original)
+++ llvm/trunk/test/Analysis/CostModel/ARM64/store.ll (removed)
@@ -1,22 +0,0 @@
-; RUN: opt < %s -cost-model -analyze -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s
-target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
-; CHECK-LABEL: store
-define void @store() {
- ; Stores of <2 x i64> should be expensive because we don't split them and
- ; and unaligned 16b stores have bad performance.
- ; CHECK: cost of 12 {{.*}} store
- store <2 x i64> undef, <2 x i64> * undef
-
- ; We scalarize the loads/stores because there is no vector register name for
- ; these types (they get extended to v.4h/v.2s).
- ; CHECK: cost of 16 {{.*}} store
- store <2 x i8> undef, <2 x i8> * undef
- ; CHECK: cost of 64 {{.*}} store
- store <4 x i8> undef, <4 x i8> * undef
- ; CHECK: cost of 16 {{.*}} load
- load <2 x i8> * undef
- ; CHECK: cost of 64 {{.*}} load
- load <4 x i8> * undef
-
- ret void
-}
Modified: llvm/trunk/test/CodeGen/AArch64/128bit_load_store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/128bit_load_store.ll?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/128bit_load_store.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/128bit_load_store.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon | FileCheck %s --check-prefix=CHECK
define void @test_store_f128(fp128* %ptr, fp128 %val) #0 {
; CHECK-LABEL: test_store_f128
@@ -17,8 +17,8 @@ entry:
}
define void @test_vstrq_p128(i128* %ptr, i128 %val) #0 {
-; CHECK-ARM64-LABEL: test_vstrq_p128
-; CHECK-ARM64: stp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
+; CHECK-LABEL: test_vstrq_p128
+; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
entry:
%0 = bitcast i128* %ptr to fp128*
@@ -28,8 +28,8 @@ entry:
}
define i128 @test_vldrq_p128(i128* readonly %ptr) #2 {
-; CHECK-ARM64-LABEL: test_vldrq_p128
-; CHECK-ARM64: ldp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
+; CHECK-LABEL: test_vldrq_p128
+; CHECK: ldp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
entry:
%0 = bitcast i128* %ptr to fp128*
Copied: llvm/trunk/test/CodeGen/AArch64/aarch64-neon-v1i1-setcc.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/aarch64-neon-v1i1-setcc.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-neon-v1i1-setcc.ll?p2=llvm/trunk/test/CodeGen/AArch64/aarch64-neon-v1i1-setcc.ll&p1=llvm/trunk/test/CodeGen/ARM64/aarch64-neon-v1i1-setcc.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Modified: llvm/trunk/test/CodeGen/AArch64/addsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/addsub.ll?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/addsub.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/addsub.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-linux-gnu | FileCheck %s
; Note that this should be refactored (for efficiency if nothing else)
; when the PCS is implemented so we don't have to worry about the
Modified: llvm/trunk/test/CodeGen/AArch64/addsub_ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/addsub_ext.ll?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/addsub_ext.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/addsub_ext.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu | FileCheck %s
@var8 = global i8 0
@var16 = global i16 0
Modified: llvm/trunk/test/CodeGen/AArch64/alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/alloca.ll?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/alloca.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/alloca.ll Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
-; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s
+; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s
declare void @use_addr(i8*)
@@ -53,7 +53,7 @@ define i64 @test_alloca_with_local(i64 %
%val = load i64* %loc
-; CHECK-ARM64: ldur x0, [x29, #-[[LOC_FROM_FP]]]
+; CHECK: ldur x0, [x29, #-[[LOC_FROM_FP]]]
ret i64 %val
; Make sure epilogue restores sp from fp
@@ -74,16 +74,16 @@ define void @test_variadic_alloca(i64 %n
; CHECK-NOFP-AARCH64: add x8, [[TMP]], #0
-; CHECK-ARM64: stp x29, x30, [sp, #-16]!
-; CHECK-ARM64: mov x29, sp
-; CHECK-ARM64: sub sp, sp, #192
-; CHECK-ARM64: stp q6, q7, [x29, #-96]
+; CHECK: stp x29, x30, [sp, #-16]!
+; CHECK: mov x29, sp
+; CHECK: sub sp, sp, #192
+; CHECK: stp q6, q7, [x29, #-96]
; [...]
-; CHECK-ARM64: stp q0, q1, [x29, #-192]
+; CHECK: stp q0, q1, [x29, #-192]
-; CHECK-ARM64: stp x6, x7, [x29, #-16]
+; CHECK: stp x6, x7, [x29, #-16]
; [...]
-; CHECK-ARM64: stp x2, x3, [x29, #-48]
+; CHECK: stp x2, x3, [x29, #-48]
; CHECK-NOFP-ARM64: stp x29, x30, [sp, #-16]!
; CHECK-NOFP-ARM64: mov x29, sp
@@ -115,11 +115,11 @@ define void @test_alloca_large_frame(i64
; CHECK-LABEL: test_alloca_large_frame:
-; CHECK-ARM64: stp x20, x19, [sp, #-32]!
-; CHECK-ARM64: stp x29, x30, [sp, #16]
-; CHECK-ARM64: add x29, sp, #16
-; CHECK-ARM64: sub sp, sp, #1953, lsl #12
-; CHECK-ARM64: sub sp, sp, #512
+; CHECK: stp x20, x19, [sp, #-32]!
+; CHECK: stp x29, x30, [sp, #16]
+; CHECK: add x29, sp, #16
+; CHECK: sub sp, sp, #1953, lsl #12
+; CHECK: sub sp, sp, #512
%addr1 = alloca i8, i64 %n
%addr2 = alloca i64, i64 1000000
@@ -128,9 +128,9 @@ define void @test_alloca_large_frame(i64
ret void
-; CHECK-ARM64: sub sp, x29, #16
-; CHECK-ARM64: ldp x29, x30, [sp, #16]
-; CHECK-ARM64: ldp x20, x19, [sp], #32
+; CHECK: sub sp, x29, #16
+; CHECK: ldp x29, x30, [sp, #16]
+; CHECK: ldp x20, x19, [sp], #32
}
declare i8* @llvm.stacksave()
Modified: llvm/trunk/test/CodeGen/AArch64/analyze-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/analyze-branch.ll?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/analyze-branch.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/analyze-branch.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm64-none-linux-gnu < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
; This test checks that LLVM can do basic stripping and reapplying of branches
; to basic blocks.
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2011-03-09-CPSRSpill.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll&p1=llvm/trunk/test/CodeGen/ARM64/2011-03-09-CPSRSpill.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2011-03-17-AsmPrinterCrash.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll&p1=llvm/trunk/test/CodeGen/ARM64/2011-03-17-AsmPrinterCrash.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2011-03-21-Unaligned-Frame-Index.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll&p1=llvm/trunk/test/CodeGen/ARM64/2011-03-21-Unaligned-Frame-Index.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2011-04-21-CPSRBug.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll&p1=llvm/trunk/test/CodeGen/ARM64/2011-04-21-CPSRBug.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll&p1=llvm/trunk/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2012-01-11-ComparisonDAGCrash.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll&p1=llvm/trunk/test/CodeGen/ARM64/2012-01-11-ComparisonDAGCrash.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-07-DAGCombineVectorExtract.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2012-05-07-DAGCombineVectorExtract.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-07-DAGCombineVectorExtract.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-07-DAGCombineVectorExtract.ll&p1=llvm/trunk/test/CodeGen/ARM64/2012-05-07-DAGCombineVectorExtract.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-07-MemcpyAlignBug.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2012-05-07-MemcpyAlignBug.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-07-MemcpyAlignBug.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-07-MemcpyAlignBug.ll&p1=llvm/trunk/test/CodeGen/ARM64/2012-05-07-MemcpyAlignBug.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-09-LOADgot-bug.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2012-05-09-LOADgot-bug.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-09-LOADgot-bug.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-09-LOADgot-bug.ll&p1=llvm/trunk/test/CodeGen/ARM64/2012-05-09-LOADgot-bug.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2012-05-22-LdStOptBug.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll&p1=llvm/trunk/test/CodeGen/ARM64/2012-05-22-LdStOptBug.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2012-06-06-FPToUI.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll&p1=llvm/trunk/test/CodeGen/ARM64/2012-06-06-FPToUI.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2012-07-11-InstrEmitterBug.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll&p1=llvm/trunk/test/CodeGen/ARM64/2012-07-11-InstrEmitterBug.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2013-01-13-ffast-fcmp.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll&p1=llvm/trunk/test/CodeGen/ARM64/2013-01-13-ffast-fcmp.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/2013-01-13-ffast-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -fp-contract=fast | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -fp-contract=fast | FileCheck %s --check-prefix=FAST
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2013-01-23-frem-crash.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll&p1=llvm/trunk/test/CodeGen/ARM64/2013-01-23-frem-crash.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2013-01-23-sext-crash.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll&p1=llvm/trunk/test/CodeGen/ARM64/2013-01-23-sext-crash.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2013-02-12-shufv8i8.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2013-02-12-shufv8i8.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2013-02-12-shufv8i8.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2013-02-12-shufv8i8.ll&p1=llvm/trunk/test/CodeGen/ARM64/2013-02-12-shufv8i8.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/2013-02-12-shufv8i8.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-2013-02-12-shufv8i8.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple
;CHECK-LABEL: Shuff:
;CHECK: tbl.8b
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2014-04-16-AnInfiniteLoopInDAGCombine.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll&p1=llvm/trunk/test/CodeGen/ARM64/2014-04-16-AnInfiniteLoopInDAGCombine.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2014-04-28-sqshl-uqshl-i64Contant.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll&p1=llvm/trunk/test/CodeGen/ARM64/2014-04-28-sqshl-uqshl-i64Contant.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/2014-04-28-sqshl-uqshl-i64Contant.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll Sat May 24 07:50:23 2014
@@ -4,16 +4,16 @@
define i64 @test_vqshld_s64_i(i64 %a) {
; CHECK-LABEL: test_vqshld_s64_i:
; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
- %1 = tail call i64 @llvm.arm64.neon.sqshl.i64(i64 %a, i64 36)
+ %1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36)
ret i64 %1
}
define i64 @test_vqshld_u64_i(i64 %a) {
; CHECK-LABEL: test_vqshld_u64_i:
; CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
- %1 = tail call i64 @llvm.arm64.neon.uqshl.i64(i64 %a, i64 36)
+ %1 = tail call i64 @llvm.aarch64.neon.uqshl.i64(i64 %a, i64 36)
ret i64 %1
}
-declare i64 @llvm.arm64.neon.uqshl.i64(i64, i64)
-declare i64 @llvm.arm64.neon.sqshl.i64(i64, i64)
+declare i64 @llvm.aarch64.neon.uqshl.i64(i64, i64)
+declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/2014-04-29-EXT-undef-mask.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll&p1=llvm/trunk/test/CodeGen/ARM64/2014-04-29-EXT-undef-mask.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/2014-04-29-EXT-undef-mask.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -O0 -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
; The following 2 test cases test shufflevector with beginning UNDEF mask.
define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) {
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/AdvSIMD-Scalar.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll&p1=llvm/trunk/test/CodeGen/ARM64/AdvSIMD-Scalar.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/AdvSIMD-Scalar.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -arm64-simd-scalar=true -asm-verbose=false | FileCheck %s
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=generic -arm64-simd-scalar=true -asm-verbose=false | FileCheck %s -check-prefix=GENERIC
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false | FileCheck %s -check-prefix=GENERIC
define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
; CHECK-LABEL: bar:
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/aapcs.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll&p1=llvm/trunk/test/CodeGen/ARM64/aapcs.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/abi-varargs.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll&p1=llvm/trunk/test/CodeGen/ARM64/abi-varargs.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/abi.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll&p1=llvm/trunk/test/CodeGen/ARM64/abi.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/abi_align.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll&p1=llvm/trunk/test/CodeGen/ARM64/abi_align.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-addp.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/addp.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-addp.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-addp.ll&p1=llvm/trunk/test/CodeGen/ARM64/addp.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/addp.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-addp.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
define double @foo(<2 x double> %a) nounwind {
; CHECK-LABEL: foo:
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-addr-mode-folding.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/addr-mode-folding.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-addr-mode-folding.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-addr-mode-folding.ll&p1=llvm/trunk/test/CodeGen/ARM64/addr-mode-folding.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-addr-type-promotion.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/addr-type-promotion.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-addr-type-promotion.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-addr-type-promotion.ll&p1=llvm/trunk/test/CodeGen/ARM64/addr-type-promotion.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-addrmode.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/addrmode.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-addrmode.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-addrmode.ll&p1=llvm/trunk/test/CodeGen/ARM64/addrmode.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/alloc-no-stack-realign.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll&p1=llvm/trunk/test/CodeGen/ARM64/alloc-no-stack-realign.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/alloca-frame-pointer-offset.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll&p1=llvm/trunk/test/CodeGen/ARM64/alloca-frame-pointer-offset.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/andCmpBrToTBZ.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll&p1=llvm/trunk/test/CodeGen/ARM64/andCmpBrToTBZ.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-ands-bad-peephole.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/ands-bad-peephole.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ands-bad-peephole.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-ands-bad-peephole.ll&p1=llvm/trunk/test/CodeGen/ARM64/ands-bad-peephole.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-anyregcc-crash.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/anyregcc-crash.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-anyregcc-crash.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-anyregcc-crash.ll&p1=llvm/trunk/test/CodeGen/ARM64/anyregcc-crash.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-anyregcc.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/anyregcc.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-anyregcc.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-anyregcc.ll&p1=llvm/trunk/test/CodeGen/ARM64/anyregcc.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-arith-saturating.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/arith-saturating.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-arith-saturating.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-arith-saturating.ll&p1=llvm/trunk/test/CodeGen/ARM64/arith-saturating.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/arith-saturating.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-arith-saturating.ll Sat May 24 07:50:23 2014
@@ -5,7 +5,7 @@ define i32 @qadds(<4 x i32> %b, <4 x i32
; CHECK: sqadd s0, s0, s1
%vecext = extractelement <4 x i32> %b, i32 0
%vecext1 = extractelement <4 x i32> %c, i32 0
- %vqadd.i = tail call i32 @llvm.arm64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
+ %vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
ret i32 %vqadd.i
}
@@ -14,7 +14,7 @@ define i64 @qaddd(<2 x i64> %b, <2 x i64
; CHECK: sqadd d0, d0, d1
%vecext = extractelement <2 x i64> %b, i32 0
%vecext1 = extractelement <2 x i64> %c, i32 0
- %vqadd.i = tail call i64 @llvm.arm64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind
+ %vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind
ret i64 %vqadd.i
}
@@ -23,7 +23,7 @@ define i32 @uqadds(<4 x i32> %b, <4 x i3
; CHECK: uqadd s0, s0, s1
%vecext = extractelement <4 x i32> %b, i32 0
%vecext1 = extractelement <4 x i32> %c, i32 0
- %vqadd.i = tail call i32 @llvm.arm64.neon.uqadd.i32(i32 %vecext, i32 %vecext1) nounwind
+ %vqadd.i = tail call i32 @llvm.aarch64.neon.uqadd.i32(i32 %vecext, i32 %vecext1) nounwind
ret i32 %vqadd.i
}
@@ -32,21 +32,21 @@ define i64 @uqaddd(<2 x i64> %b, <2 x i6
; CHECK: uqadd d0, d0, d1
%vecext = extractelement <2 x i64> %b, i32 0
%vecext1 = extractelement <2 x i64> %c, i32 0
- %vqadd.i = tail call i64 @llvm.arm64.neon.uqadd.i64(i64 %vecext, i64 %vecext1) nounwind
+ %vqadd.i = tail call i64 @llvm.aarch64.neon.uqadd.i64(i64 %vecext, i64 %vecext1) nounwind
ret i64 %vqadd.i
}
-declare i64 @llvm.arm64.neon.uqadd.i64(i64, i64) nounwind readnone
-declare i32 @llvm.arm64.neon.uqadd.i32(i32, i32) nounwind readnone
-declare i64 @llvm.arm64.neon.sqadd.i64(i64, i64) nounwind readnone
-declare i32 @llvm.arm64.neon.sqadd.i32(i32, i32) nounwind readnone
+declare i64 @llvm.aarch64.neon.uqadd.i64(i64, i64) nounwind readnone
+declare i32 @llvm.aarch64.neon.uqadd.i32(i32, i32) nounwind readnone
+declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64) nounwind readnone
+declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) nounwind readnone
define i32 @qsubs(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: qsubs:
; CHECK: sqsub s0, s0, s1
%vecext = extractelement <4 x i32> %b, i32 0
%vecext1 = extractelement <4 x i32> %c, i32 0
- %vqsub.i = tail call i32 @llvm.arm64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind
+ %vqsub.i = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind
ret i32 %vqsub.i
}
@@ -55,7 +55,7 @@ define i64 @qsubd(<2 x i64> %b, <2 x i64
; CHECK: sqsub d0, d0, d1
%vecext = extractelement <2 x i64> %b, i32 0
%vecext1 = extractelement <2 x i64> %c, i32 0
- %vqsub.i = tail call i64 @llvm.arm64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwind
+ %vqsub.i = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwind
ret i64 %vqsub.i
}
@@ -64,7 +64,7 @@ define i32 @uqsubs(<4 x i32> %b, <4 x i3
; CHECK: uqsub s0, s0, s1
%vecext = extractelement <4 x i32> %b, i32 0
%vecext1 = extractelement <4 x i32> %c, i32 0
- %vqsub.i = tail call i32 @llvm.arm64.neon.uqsub.i32(i32 %vecext, i32 %vecext1) nounwind
+ %vqsub.i = tail call i32 @llvm.aarch64.neon.uqsub.i32(i32 %vecext, i32 %vecext1) nounwind
ret i32 %vqsub.i
}
@@ -73,21 +73,21 @@ define i64 @uqsubd(<2 x i64> %b, <2 x i6
; CHECK: uqsub d0, d0, d1
%vecext = extractelement <2 x i64> %b, i32 0
%vecext1 = extractelement <2 x i64> %c, i32 0
- %vqsub.i = tail call i64 @llvm.arm64.neon.uqsub.i64(i64 %vecext, i64 %vecext1) nounwind
+ %vqsub.i = tail call i64 @llvm.aarch64.neon.uqsub.i64(i64 %vecext, i64 %vecext1) nounwind
ret i64 %vqsub.i
}
-declare i64 @llvm.arm64.neon.uqsub.i64(i64, i64) nounwind readnone
-declare i32 @llvm.arm64.neon.uqsub.i32(i32, i32) nounwind readnone
-declare i64 @llvm.arm64.neon.sqsub.i64(i64, i64) nounwind readnone
-declare i32 @llvm.arm64.neon.sqsub.i32(i32, i32) nounwind readnone
+declare i64 @llvm.aarch64.neon.uqsub.i64(i64, i64) nounwind readnone
+declare i32 @llvm.aarch64.neon.uqsub.i32(i32, i32) nounwind readnone
+declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64) nounwind readnone
+declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32) nounwind readnone
define i32 @qabss(<4 x i32> %b, <4 x i32> %c) nounwind readnone {
; CHECK-LABEL: qabss:
; CHECK: sqabs s0, s0
; CHECK: ret
%vecext = extractelement <4 x i32> %b, i32 0
- %vqabs.i = tail call i32 @llvm.arm64.neon.sqabs.i32(i32 %vecext) nounwind
+ %vqabs.i = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %vecext) nounwind
ret i32 %vqabs.i
}
@@ -96,7 +96,7 @@ define i64 @qabsd(<2 x i64> %b, <2 x i64
; CHECK: sqabs d0, d0
; CHECK: ret
%vecext = extractelement <2 x i64> %b, i32 0
- %vqabs.i = tail call i64 @llvm.arm64.neon.sqabs.i64(i64 %vecext) nounwind
+ %vqabs.i = tail call i64 @llvm.aarch64.neon.sqabs.i64(i64 %vecext) nounwind
ret i64 %vqabs.i
}
@@ -105,7 +105,7 @@ define i32 @qnegs(<4 x i32> %b, <4 x i32
; CHECK: sqneg s0, s0
; CHECK: ret
%vecext = extractelement <4 x i32> %b, i32 0
- %vqneg.i = tail call i32 @llvm.arm64.neon.sqneg.i32(i32 %vecext) nounwind
+ %vqneg.i = tail call i32 @llvm.aarch64.neon.sqneg.i32(i32 %vecext) nounwind
ret i32 %vqneg.i
}
@@ -114,21 +114,21 @@ define i64 @qnegd(<2 x i64> %b, <2 x i64
; CHECK: sqneg d0, d0
; CHECK: ret
%vecext = extractelement <2 x i64> %b, i32 0
- %vqneg.i = tail call i64 @llvm.arm64.neon.sqneg.i64(i64 %vecext) nounwind
+ %vqneg.i = tail call i64 @llvm.aarch64.neon.sqneg.i64(i64 %vecext) nounwind
ret i64 %vqneg.i
}
-declare i64 @llvm.arm64.neon.sqneg.i64(i64) nounwind readnone
-declare i32 @llvm.arm64.neon.sqneg.i32(i32) nounwind readnone
-declare i64 @llvm.arm64.neon.sqabs.i64(i64) nounwind readnone
-declare i32 @llvm.arm64.neon.sqabs.i32(i32) nounwind readnone
+declare i64 @llvm.aarch64.neon.sqneg.i64(i64) nounwind readnone
+declare i32 @llvm.aarch64.neon.sqneg.i32(i32) nounwind readnone
+declare i64 @llvm.aarch64.neon.sqabs.i64(i64) nounwind readnone
+declare i32 @llvm.aarch64.neon.sqabs.i32(i32) nounwind readnone
define i32 @vqmovund(<2 x i64> %b) nounwind readnone {
; CHECK-LABEL: vqmovund:
; CHECK: sqxtun s0, d0
%vecext = extractelement <2 x i64> %b, i32 0
- %vqmovun.i = tail call i32 @llvm.arm64.neon.scalar.sqxtun.i32.i64(i64 %vecext) nounwind
+ %vqmovun.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64 %vecext) nounwind
ret i32 %vqmovun.i
}
@@ -136,7 +136,7 @@ define i32 @vqmovnd_s(<2 x i64> %b) noun
; CHECK-LABEL: vqmovnd_s:
; CHECK: sqxtn s0, d0
%vecext = extractelement <2 x i64> %b, i32 0
- %vqmovn.i = tail call i32 @llvm.arm64.neon.scalar.sqxtn.i32.i64(i64 %vecext) nounwind
+ %vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %vecext) nounwind
ret i32 %vqmovn.i
}
@@ -144,10 +144,10 @@ define i32 @vqmovnd_u(<2 x i64> %b) noun
; CHECK-LABEL: vqmovnd_u:
; CHECK: uqxtn s0, d0
%vecext = extractelement <2 x i64> %b, i32 0
- %vqmovn.i = tail call i32 @llvm.arm64.neon.scalar.uqxtn.i32.i64(i64 %vecext) nounwind
+ %vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64 %vecext) nounwind
ret i32 %vqmovn.i
}
-declare i32 @llvm.arm64.neon.scalar.uqxtn.i32.i64(i64) nounwind readnone
-declare i32 @llvm.arm64.neon.scalar.sqxtn.i32.i64(i64) nounwind readnone
-declare i32 @llvm.arm64.neon.scalar.sqxtun.i32.i64(i64) nounwind readnone
+declare i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64) nounwind readnone
+declare i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64) nounwind readnone
+declare i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64) nounwind readnone
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/arith.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll&p1=llvm/trunk/test/CodeGen/ARM64/arith.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/arith.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll Sat May 24 07:50:23 2014
@@ -168,7 +168,7 @@ entry:
; CHECK-LABEL: t18:
; CHECK: sdiv w0, w0, w1
; CHECK: ret
- %sdiv = call i32 @llvm.arm64.sdiv.i32(i32 %a, i32 %b)
+ %sdiv = call i32 @llvm.aarch64.sdiv.i32(i32 %a, i32 %b)
ret i32 %sdiv
}
@@ -177,7 +177,7 @@ entry:
; CHECK-LABEL: t19:
; CHECK: sdiv x0, x0, x1
; CHECK: ret
- %sdiv = call i64 @llvm.arm64.sdiv.i64(i64 %a, i64 %b)
+ %sdiv = call i64 @llvm.aarch64.sdiv.i64(i64 %a, i64 %b)
ret i64 %sdiv
}
@@ -186,7 +186,7 @@ entry:
; CHECK-LABEL: t20:
; CHECK: udiv w0, w0, w1
; CHECK: ret
- %udiv = call i32 @llvm.arm64.udiv.i32(i32 %a, i32 %b)
+ %udiv = call i32 @llvm.aarch64.udiv.i32(i32 %a, i32 %b)
ret i32 %udiv
}
@@ -195,14 +195,14 @@ entry:
; CHECK-LABEL: t21:
; CHECK: udiv x0, x0, x1
; CHECK: ret
- %udiv = call i64 @llvm.arm64.udiv.i64(i64 %a, i64 %b)
+ %udiv = call i64 @llvm.aarch64.udiv.i64(i64 %a, i64 %b)
ret i64 %udiv
}
-declare i32 @llvm.arm64.sdiv.i32(i32, i32) nounwind readnone
-declare i64 @llvm.arm64.sdiv.i64(i64, i64) nounwind readnone
-declare i32 @llvm.arm64.udiv.i32(i32, i32) nounwind readnone
-declare i64 @llvm.arm64.udiv.i64(i64, i64) nounwind readnone
+declare i32 @llvm.aarch64.sdiv.i32(i32, i32) nounwind readnone
+declare i64 @llvm.aarch64.sdiv.i64(i64, i64) nounwind readnone
+declare i32 @llvm.aarch64.udiv.i32(i32, i32) nounwind readnone
+declare i64 @llvm.aarch64.udiv.i64(i64, i64) nounwind readnone
; 32-bit not.
define i32 @inv_32(i32 %x) nounwind ssp {
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-arm64-dead-def-elimination-flag.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/arm64-dead-def-elimination-flag.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-arm64-dead-def-elimination-flag.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-arm64-dead-def-elimination-flag.ll&p1=llvm/trunk/test/CodeGen/ARM64/arm64-dead-def-elimination-flag.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/arm64-dead-def-elimination-flag.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-arm64-dead-def-elimination-flag.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=arm64 -arm64-dead-def-elimination=false < %s | FileCheck %s
+; RUN: llc -march=arm64 -aarch64-dead-def-elimination=false < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-atomic-128.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/atomic-128.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-atomic-128.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-atomic-128.ll&p1=llvm/trunk/test/CodeGen/ARM64/atomic-128.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-atomic.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/atomic.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-atomic.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-atomic.ll&p1=llvm/trunk/test/CodeGen/ARM64/atomic.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-basic-pic.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/basic-pic.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-basic-pic.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-basic-pic.ll&p1=llvm/trunk/test/CodeGen/ARM64/basic-pic.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/big-endian-bitconverts.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll&p1=llvm/trunk/test/CodeGen/ARM64/big-endian-bitconverts.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/big-endian-bitconverts.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -O1 -o - | FileCheck %s
-; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -O0 -fast-isel=true -o - | FileCheck %s
+; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -O1 -o - | FileCheck %s
+; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -O0 -fast-isel=true -o - | FileCheck %s
; CHECK-LABEL: test_i64_f64:
define void @test_i64_f64(double* %p, i64* %q) {
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-eh.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/big-endian-eh.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-eh.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-eh.ll&p1=llvm/trunk/test/CodeGen/ARM64/big-endian-eh.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-varargs.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/big-endian-varargs.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-varargs.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-varargs.ll&p1=llvm/trunk/test/CodeGen/ARM64/big-endian-varargs.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/big-endian-vector-callee.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll&p1=llvm/trunk/test/CodeGen/ARM64/big-endian-vector-callee.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/big-endian-vector-callee.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -o - | FileCheck %s
-; RUN: llc -mtriple arm64_be < %s -fast-isel=true -arm64-load-store-opt=false -o - | FileCheck %s
+; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -o - | FileCheck %s
+; RUN: llc -mtriple arm64_be < %s -fast-isel=true -aarch64-load-store-opt=false -o - | FileCheck %s
; CHECK-LABEL: test_i64_f64:
define i64 @test_i64_f64(double %p) {
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/big-endian-vector-caller.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll&p1=llvm/trunk/test/CodeGen/ARM64/big-endian-vector-caller.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/big-endian-vector-caller.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -o - | FileCheck %s
-; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -fast-isel=true -O0 -o - | FileCheck %s
+; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -o - | FileCheck %s
+; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -fast-isel=true -O0 -o - | FileCheck %s
; CHECK-LABEL: test_i64_f64:
declare i64 @test_i64_f64_helper(double %p)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-big-imm-offsets.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/big-imm-offsets.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-big-imm-offsets.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-big-imm-offsets.ll&p1=llvm/trunk/test/CodeGen/ARM64/big-imm-offsets.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-big-stack.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/big-stack.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-big-stack.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-big-stack.ll&p1=llvm/trunk/test/CodeGen/ARM64/big-stack.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-bitfield-extract.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-bitfield-extract.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-bitfield-extract.ll&p1=llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-blockaddress.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/blockaddress.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-blockaddress.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-blockaddress.ll&p1=llvm/trunk/test/CodeGen/ARM64/blockaddress.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/build-vector.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll&p1=llvm/trunk/test/CodeGen/ARM64/build-vector.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/build-vector.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
; Check that building up a vector w/ only one non-zero lane initializes
; intelligently.
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-call-tailcalls.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/call-tailcalls.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-call-tailcalls.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-call-tailcalls.ll&p1=llvm/trunk/test/CodeGen/ARM64/call-tailcalls.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-cast-opt.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/cast-opt.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-cast-opt.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-cast-opt.ll&p1=llvm/trunk/test/CodeGen/ARM64/cast-opt.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/ccmp-heuristics.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll&p1=llvm/trunk/test/CodeGen/ARM64/ccmp-heuristics.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ccmp-heuristics.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=cyclone -verify-machineinstrs -arm64-ccmp | FileCheck %s
+; RUN: llc < %s -mcpu=cyclone -verify-machineinstrs -aarch64-ccmp | FileCheck %s
target triple = "arm64-apple-ios7.0.0"
@channelColumns = external global i64
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/ccmp.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll&p1=llvm/trunk/test/CodeGen/ARM64/ccmp.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ccmp.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=cyclone -verify-machineinstrs -arm64-ccmp -arm64-stress-ccmp | FileCheck %s
+; RUN: llc < %s -mcpu=cyclone -verify-machineinstrs -aarch64-ccmp -aarch64-stress-ccmp | FileCheck %s
target triple = "arm64-apple-ios"
; CHECK: single_same
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-clrsb.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/clrsb.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-clrsb.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-clrsb.ll&p1=llvm/trunk/test/CodeGen/ARM64/clrsb.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-coalesce-ext.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/coalesce-ext.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-coalesce-ext.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-coalesce-ext.ll&p1=llvm/trunk/test/CodeGen/ARM64/coalesce-ext.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-code-model-large-abs.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/code-model-large-abs.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-code-model-large-abs.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-code-model-large-abs.ll&p1=llvm/trunk/test/CodeGen/ARM64/code-model-large-abs.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/collect-loh-garbage-crash.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll&p1=llvm/trunk/test/CodeGen/ARM64/collect-loh-garbage-crash.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/collect-loh-garbage-crash.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm64-apple-ios -O3 -arm64-collect-loh -arm64-collect-loh-bb-only=true -arm64-collect-loh-pre-collect-register=false < %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-ios -O3 -aarch64-collect-loh -aarch64-collect-loh-bb-only=true -aarch64-collect-loh-pre-collect-register=false < %s -o - | FileCheck %s
; Check that the LOH analysis does not crash when the analysed chained
; contains instructions that are filtered out.
;
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh-str.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/collect-loh-str.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh-str.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh-str.ll&p1=llvm/trunk/test/CodeGen/ARM64/collect-loh-str.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/collect-loh-str.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh-str.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm64-apple-ios -O2 -arm64-collect-loh -arm64-collect-loh-bb-only=false < %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-ios -O2 -aarch64-collect-loh -aarch64-collect-loh-bb-only=false < %s -o - | FileCheck %s
; Test case for <rdar://problem/15942912>.
; AdrpAddStr cannot be used when the store uses same
; register as address and value. Indeed, the related
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/collect-loh.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh.ll&p1=llvm/trunk/test/CodeGen/ARM64/collect-loh.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/collect-loh.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh.ll Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=arm64-apple-ios -O2 -arm64-collect-loh -arm64-collect-loh-bb-only=false < %s -o - | FileCheck %s
-; RUN: llc -mtriple=arm64-linux-gnu -O2 -arm64-collect-loh -arm64-collect-loh-bb-only=false < %s -o - | FileCheck %s --check-prefix=CHECK-ELF
+; RUN: llc -mtriple=arm64-apple-ios -O2 -aarch64-collect-loh -aarch64-collect-loh-bb-only=false < %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm64-linux-gnu -O2 -aarch64-collect-loh -aarch64-collect-loh-bb-only=false < %s -o - | FileCheck %s --check-prefix=CHECK-ELF
; CHECK-ELF-NOT: .loh
; CHECK-ELF-NOT: AdrpAdrp
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/complex-copy-noneon.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll&p1=llvm/trunk/test/CodeGen/ARM64/complex-copy-noneon.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-complex-ret.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/complex-ret.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-complex-ret.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-complex-ret.ll&p1=llvm/trunk/test/CodeGen/ARM64/complex-ret.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-const-addr.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/const-addr.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-const-addr.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-const-addr.ll&p1=llvm/trunk/test/CodeGen/ARM64/const-addr.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-convert-v2f64-v2i32.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/convert-v2f64-v2i32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-convert-v2f64-v2i32.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-convert-v2f64-v2i32.ll&p1=llvm/trunk/test/CodeGen/ARM64/convert-v2f64-v2i32.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/convert-v2f64-v2i32.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-convert-v2f64-v2i32.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
; CHECK: fptosi_1
; CHECK: fcvtzs.2d
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-convert-v2i32-v2f64.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/convert-v2i32-v2f64.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-convert-v2i32-v2f64.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-convert-v2i32-v2f64.ll&p1=llvm/trunk/test/CodeGen/ARM64/convert-v2i32-v2f64.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/convert-v2i32-v2f64.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-convert-v2i32-v2f64.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
define <2 x double> @f1(<2 x i32> %v) nounwind readnone {
; CHECK-LABEL: f1:
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-copy-tuple.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/copy-tuple.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-copy-tuple.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-copy-tuple.ll&p1=llvm/trunk/test/CodeGen/ARM64/copy-tuple.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/copy-tuple.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-copy-tuple.ll Sat May 24 07:50:23 2014
@@ -13,14 +13,14 @@ define void @test_D1D2_from_D0D1(i8* %ad
; CHECK: mov.8b v1, v0
entry:
%addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
+ %vec = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
%vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
%vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
+ tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
tail call void asm sideeffect "", "~{v0},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
+ tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
ret void
}
@@ -30,14 +30,14 @@ define void @test_D0D1_from_D1D2(i8* %ad
; CHECK: mov.8b v1, v2
entry:
%addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
+ %vec = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
%vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
%vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
tail call void asm sideeffect "", "~{v0},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
+ tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
+ tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
ret void
}
@@ -47,14 +47,14 @@ define void @test_D0D1_from_D31D0(i8* %a
; CHECK: mov.8b v0, v31
entry:
%addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
+ %vec = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
%vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
%vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
tail call void asm sideeffect "", "~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
+ tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
+ tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
ret void
}
@@ -64,14 +64,14 @@ define void @test_D31D0_from_D0D1(i8* %a
; CHECK: mov.8b v0, v1
entry:
%addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
+ %vec = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
%vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
%vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
+ tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
tail call void asm sideeffect "", "~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
+ tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
ret void
}
@@ -82,16 +82,16 @@ define void @test_D2D3D4_from_D0D1D2(i8*
; CHECK: mov.8b v2, v0
entry:
%addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
+ %vec = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
%vec0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 0
%vec1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 1
%vec2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 2
tail call void asm sideeffect "", "~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8* %addr)
+ tail call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8* %addr)
tail call void asm sideeffect "", "~{v0},~{v1},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8* %addr)
+ tail call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8* %addr)
ret void
}
@@ -102,15 +102,15 @@ define void @test_Q0Q1Q2_from_Q1Q2Q3(i8*
; CHECK: mov.16b v2, v3
entry:
%addr_v16i8 = bitcast i8* %addr to <16 x i8>*
- %vec = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3.v16i8.p0v16i8(<16 x i8>* %addr_v16i8)
+ %vec = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0v16i8(<16 x i8>* %addr_v16i8)
%vec0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 0
%vec1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 1
%vec2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 2
tail call void asm sideeffect "", "~{v0},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, i8* %addr)
+ tail call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, i8* %addr)
tail call void asm sideeffect "", "~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, i8* %addr)
+ tail call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, i8* %addr)
ret void
}
@@ -121,26 +121,26 @@ define void @test_Q1Q2Q3Q4_from_Q30Q31Q0
; CHECK: mov.16b v2, v31
; CHECK: mov.16b v1, v30
%addr_v16i8 = bitcast i8* %addr to <16 x i8>*
- %vec = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4.v16i8.p0v16i8(<16 x i8>* %addr_v16i8)
+ %vec = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0v16i8(<16 x i8>* %addr_v16i8)
%vec0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 0
%vec1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 1
%vec2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 2
%vec3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 3
tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}"()
- tail call void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, i8* %addr)
+ tail call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, i8* %addr)
tail call void asm sideeffect "", "~{v0},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, i8* %addr)
+ tail call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, i8* %addr)
ret void
}
-declare { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>*)
-declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3.v8i8.p0v8i8(<8 x i8>*)
-declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3.v16i8.p0v16i8(<16 x i8>*)
-declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4.v16i8.p0v16i8(<16 x i8>*)
+declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>*)
+declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0v8i8(<8 x i8>*)
+declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0v16i8(<16 x i8>*)
+declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0v16i8(<16 x i8>*)
-declare void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*)
-declare void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*)
-declare void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*)
-declare void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*)
+declare void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*)
+declare void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*)
+declare void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*)
+declare void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-crc32.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/crc32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-crc32.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-crc32.ll&p1=llvm/trunk/test/CodeGen/ARM64/crc32.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/crc32.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-crc32.ll Sat May 24 07:50:23 2014
@@ -4,7 +4,7 @@ define i32 @test_crc32b(i32 %cur, i8 %ne
; CHECK-LABEL: test_crc32b:
; CHECK: crc32b w0, w0, w1
%bits = zext i8 %next to i32
- %val = call i32 @llvm.arm64.crc32b(i32 %cur, i32 %bits)
+ %val = call i32 @llvm.aarch64.crc32b(i32 %cur, i32 %bits)
ret i32 %val
}
@@ -12,21 +12,21 @@ define i32 @test_crc32h(i32 %cur, i16 %n
; CHECK-LABEL: test_crc32h:
; CHECK: crc32h w0, w0, w1
%bits = zext i16 %next to i32
- %val = call i32 @llvm.arm64.crc32h(i32 %cur, i32 %bits)
+ %val = call i32 @llvm.aarch64.crc32h(i32 %cur, i32 %bits)
ret i32 %val
}
define i32 @test_crc32w(i32 %cur, i32 %next) {
; CHECK-LABEL: test_crc32w:
; CHECK: crc32w w0, w0, w1
- %val = call i32 @llvm.arm64.crc32w(i32 %cur, i32 %next)
+ %val = call i32 @llvm.aarch64.crc32w(i32 %cur, i32 %next)
ret i32 %val
}
define i32 @test_crc32x(i32 %cur, i64 %next) {
; CHECK-LABEL: test_crc32x:
; CHECK: crc32x w0, w0, x1
- %val = call i32 @llvm.arm64.crc32x(i32 %cur, i64 %next)
+ %val = call i32 @llvm.aarch64.crc32x(i32 %cur, i64 %next)
ret i32 %val
}
@@ -34,7 +34,7 @@ define i32 @test_crc32cb(i32 %cur, i8 %n
; CHECK-LABEL: test_crc32cb:
; CHECK: crc32cb w0, w0, w1
%bits = zext i8 %next to i32
- %val = call i32 @llvm.arm64.crc32cb(i32 %cur, i32 %bits)
+ %val = call i32 @llvm.aarch64.crc32cb(i32 %cur, i32 %bits)
ret i32 %val
}
@@ -42,30 +42,30 @@ define i32 @test_crc32ch(i32 %cur, i16 %
; CHECK-LABEL: test_crc32ch:
; CHECK: crc32ch w0, w0, w1
%bits = zext i16 %next to i32
- %val = call i32 @llvm.arm64.crc32ch(i32 %cur, i32 %bits)
+ %val = call i32 @llvm.aarch64.crc32ch(i32 %cur, i32 %bits)
ret i32 %val
}
define i32 @test_crc32cw(i32 %cur, i32 %next) {
; CHECK-LABEL: test_crc32cw:
; CHECK: crc32cw w0, w0, w1
- %val = call i32 @llvm.arm64.crc32cw(i32 %cur, i32 %next)
+ %val = call i32 @llvm.aarch64.crc32cw(i32 %cur, i32 %next)
ret i32 %val
}
define i32 @test_crc32cx(i32 %cur, i64 %next) {
; CHECK-LABEL: test_crc32cx:
; CHECK: crc32cx w0, w0, x1
- %val = call i32 @llvm.arm64.crc32cx(i32 %cur, i64 %next)
+ %val = call i32 @llvm.aarch64.crc32cx(i32 %cur, i64 %next)
ret i32 %val
}
-declare i32 @llvm.arm64.crc32b(i32, i32)
-declare i32 @llvm.arm64.crc32h(i32, i32)
-declare i32 @llvm.arm64.crc32w(i32, i32)
-declare i32 @llvm.arm64.crc32x(i32, i64)
+declare i32 @llvm.aarch64.crc32b(i32, i32)
+declare i32 @llvm.aarch64.crc32h(i32, i32)
+declare i32 @llvm.aarch64.crc32w(i32, i32)
+declare i32 @llvm.aarch64.crc32x(i32, i64)
-declare i32 @llvm.arm64.crc32cb(i32, i32)
-declare i32 @llvm.arm64.crc32ch(i32, i32)
-declare i32 @llvm.arm64.crc32cw(i32, i32)
-declare i32 @llvm.arm64.crc32cx(i32, i64)
+declare i32 @llvm.aarch64.crc32cb(i32, i32)
+declare i32 @llvm.aarch64.crc32ch(i32, i32)
+declare i32 @llvm.aarch64.crc32cw(i32, i32)
+declare i32 @llvm.aarch64.crc32cx(i32, i64)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-crypto.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/crypto.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-crypto.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-crypto.ll&p1=llvm/trunk/test/CodeGen/ARM64/crypto.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/crypto.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-crypto.ll Sat May 24 07:50:23 2014
@@ -1,50 +1,50 @@
-; RUN: llc -march=arm64 -mattr=crypto -arm64-neon-syntax=apple -o - %s | FileCheck %s
+; RUN: llc -march=arm64 -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s
-declare <16 x i8> @llvm.arm64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
-declare <16 x i8> @llvm.arm64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
-declare <16 x i8> @llvm.arm64.crypto.aesmc(<16 x i8> %data)
-declare <16 x i8> @llvm.arm64.crypto.aesimc(<16 x i8> %data)
+declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
+declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
+declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data)
+declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
define <16 x i8> @test_aese(<16 x i8> %data, <16 x i8> %key) {
; CHECK-LABEL: test_aese:
; CHECK: aese.16b v0, v1
- %res = call <16 x i8> @llvm.arm64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
+ %res = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
ret <16 x i8> %res
}
define <16 x i8> @test_aesd(<16 x i8> %data, <16 x i8> %key) {
; CHECK-LABEL: test_aesd:
; CHECK: aesd.16b v0, v1
- %res = call <16 x i8> @llvm.arm64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
+ %res = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
ret <16 x i8> %res
}
define <16 x i8> @test_aesmc(<16 x i8> %data) {
; CHECK-LABEL: test_aesmc:
; CHECK: aesmc.16b v0, v0
- %res = call <16 x i8> @llvm.arm64.crypto.aesmc(<16 x i8> %data)
+ %res = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data)
ret <16 x i8> %res
}
define <16 x i8> @test_aesimc(<16 x i8> %data) {
; CHECK-LABEL: test_aesimc:
; CHECK: aesimc.16b v0, v0
- %res = call <16 x i8> @llvm.arm64.crypto.aesimc(<16 x i8> %data)
+ %res = call <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
ret <16 x i8> %res
}
-declare <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
-declare <4 x i32> @llvm.arm64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
-declare <4 x i32> @llvm.arm64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
-declare i32 @llvm.arm64.crypto.sha1h(i32 %hash_e)
-declare <4 x i32> @llvm.arm64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
-declare <4 x i32> @llvm.arm64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
+declare <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
+declare <4 x i32> @llvm.aarch64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
+declare <4 x i32> @llvm.aarch64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
+declare i32 @llvm.aarch64.crypto.sha1h(i32 %hash_e)
+declare <4 x i32> @llvm.aarch64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
+declare <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
define <4 x i32> @test_sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
; CHECK-LABEL: test_sha1c:
; CHECK: fmov [[HASH_E:s[0-9]+]], w0
; CHECK: sha1c.4s q0, [[HASH_E]], v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
ret <4 x i32> %res
}
@@ -55,9 +55,9 @@ define <4 x i32> @test_sha1c_in_a_row(<4
; CHECK: sha1c.4s q[[SHA1RES:[0-9]+]], [[HASH_E]], v1
; CHECK-NOT: fmov
; CHECK: sha1c.4s q0, s[[SHA1RES]], v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
%extract = extractelement <4 x i32> %res, i32 0
- %res2 = call <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %extract, <4 x i32> %wk)
+ %res2 = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %extract, <4 x i32> %wk)
ret <4 x i32> %res2
}
@@ -65,7 +65,7 @@ define <4 x i32> @test_sha1p(<4 x i32> %
; CHECK-LABEL: test_sha1p:
; CHECK: fmov [[HASH_E:s[0-9]+]], w0
; CHECK: sha1p.4s q0, [[HASH_E]], v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
ret <4 x i32> %res
}
@@ -73,7 +73,7 @@ define <4 x i32> @test_sha1m(<4 x i32> %
; CHECK-LABEL: test_sha1m:
; CHECK: fmov [[HASH_E:s[0-9]+]], w0
; CHECK: sha1m.4s q0, [[HASH_E]], v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
ret <4 x i32> %res
}
@@ -82,33 +82,33 @@ define i32 @test_sha1h(i32 %hash_e) {
; CHECK: fmov [[HASH_E:s[0-9]+]], w0
; CHECK: sha1h [[RES:s[0-9]+]], [[HASH_E]]
; CHECK: fmov w0, [[RES]]
- %res = call i32 @llvm.arm64.crypto.sha1h(i32 %hash_e)
+ %res = call i32 @llvm.aarch64.crypto.sha1h(i32 %hash_e)
ret i32 %res
}
define <4 x i32> @test_sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11) {
; CHECK-LABEL: test_sha1su0:
; CHECK: sha1su0.4s v0, v1, v2
- %res = call <4 x i32> @llvm.arm64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
ret <4 x i32> %res
}
define <4 x i32> @test_sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15) {
; CHECK-LABEL: test_sha1su1:
; CHECK: sha1su1.4s v0, v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
ret <4 x i32> %res
}
-declare <4 x i32> @llvm.arm64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
-declare <4 x i32> @llvm.arm64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
-declare <4 x i32> @llvm.arm64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
-declare <4 x i32> @llvm.arm64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
+declare <4 x i32> @llvm.aarch64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
+declare <4 x i32> @llvm.aarch64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
+declare <4 x i32> @llvm.aarch64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
+declare <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
define <4 x i32> @test_sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
; CHECK-LABEL: test_sha256h:
; CHECK: sha256h.4s q0, q1, v2
- %res = call <4 x i32> @llvm.arm64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
ret <4 x i32> %res
}
@@ -116,20 +116,20 @@ define <4 x i32> @test_sha256h2(<4 x i32
; CHECK-LABEL: test_sha256h2:
; CHECK: sha256h2.4s q0, q1, v2
- %res = call <4 x i32> @llvm.arm64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
ret <4 x i32> %res
}
define <4 x i32> @test_sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) {
; CHECK-LABEL: test_sha256su0:
; CHECK: sha256su0.4s v0, v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
ret <4 x i32> %res
}
define <4 x i32> @test_sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
; CHECK-LABEL: test_sha256su1:
; CHECK: sha256su1.4s v0, v1, v2
- %res = call <4 x i32> @llvm.arm64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
+ %res = call <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
ret <4 x i32> %res
}
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-cse.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/cse.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-cse.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-cse.ll&p1=llvm/trunk/test/CodeGen/ARM64/cse.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-csel.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/csel.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-csel.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-csel.ll&p1=llvm/trunk/test/CodeGen/ARM64/csel.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-cvt.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/cvt.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-cvt.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-cvt.ll&p1=llvm/trunk/test/CodeGen/ARM64/cvt.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/cvt.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-cvt.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
;
; Floating-point scalar convert to signed integer (to nearest with ties to away)
@@ -7,7 +7,7 @@ define i32 @fcvtas_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtas_1w1s:
;CHECK: fcvtas w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtas.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)
ret i32 %tmp3
}
@@ -15,7 +15,7 @@ define i64 @fcvtas_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtas_1x1s:
;CHECK: fcvtas x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtas.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
ret i64 %tmp3
}
@@ -23,7 +23,7 @@ define i32 @fcvtas_1w1d(double %A) nounw
;CHECK-LABEL: fcvtas_1w1d:
;CHECK: fcvtas w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtas.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)
ret i32 %tmp3
}
@@ -31,14 +31,14 @@ define i64 @fcvtas_1x1d(double %A) nounw
;CHECK-LABEL: fcvtas_1x1d:
;CHECK: fcvtas x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtas.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtas.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtas.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtas.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtas.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtas.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtas.i64.f64(double) nounwind readnone
;
; Floating-point scalar convert to unsigned integer
@@ -47,7 +47,7 @@ define i32 @fcvtau_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtau_1w1s:
;CHECK: fcvtau w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtau.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
ret i32 %tmp3
}
@@ -55,7 +55,7 @@ define i64 @fcvtau_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtau_1x1s:
;CHECK: fcvtau x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtau.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A)
ret i64 %tmp3
}
@@ -63,7 +63,7 @@ define i32 @fcvtau_1w1d(double %A) nounw
;CHECK-LABEL: fcvtau_1w1d:
;CHECK: fcvtau w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtau.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double %A)
ret i32 %tmp3
}
@@ -71,14 +71,14 @@ define i64 @fcvtau_1x1d(double %A) nounw
;CHECK-LABEL: fcvtau_1x1d:
;CHECK: fcvtau x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtau.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtau.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtau.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtau.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtau.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtau.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtau.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtau.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtau.i64.f64(double) nounwind readnone
;
; Floating-point scalar convert to signed integer (toward -Inf)
@@ -87,7 +87,7 @@ define i32 @fcvtms_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtms_1w1s:
;CHECK: fcvtms w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtms.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float %A)
ret i32 %tmp3
}
@@ -95,7 +95,7 @@ define i64 @fcvtms_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtms_1x1s:
;CHECK: fcvtms x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtms.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtms.i64.f32(float %A)
ret i64 %tmp3
}
@@ -103,7 +103,7 @@ define i32 @fcvtms_1w1d(double %A) nounw
;CHECK-LABEL: fcvtms_1w1d:
;CHECK: fcvtms w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtms.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtms.i32.f64(double %A)
ret i32 %tmp3
}
@@ -111,14 +111,14 @@ define i64 @fcvtms_1x1d(double %A) nounw
;CHECK-LABEL: fcvtms_1x1d:
;CHECK: fcvtms x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtms.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtms.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtms.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtms.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtms.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtms.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtms.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtms.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtms.i64.f64(double) nounwind readnone
;
; Floating-point scalar convert to unsigned integer (toward -Inf)
@@ -127,7 +127,7 @@ define i32 @fcvtmu_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtmu_1w1s:
;CHECK: fcvtmu w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtmu.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float %A)
ret i32 %tmp3
}
@@ -135,7 +135,7 @@ define i64 @fcvtmu_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtmu_1x1s:
;CHECK: fcvtmu x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtmu.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float %A)
ret i64 %tmp3
}
@@ -143,7 +143,7 @@ define i32 @fcvtmu_1w1d(double %A) nounw
;CHECK-LABEL: fcvtmu_1w1d:
;CHECK: fcvtmu w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtmu.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double %A)
ret i32 %tmp3
}
@@ -151,14 +151,14 @@ define i64 @fcvtmu_1x1d(double %A) nounw
;CHECK-LABEL: fcvtmu_1x1d:
;CHECK: fcvtmu x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtmu.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtmu.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtmu.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtmu.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtmu.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double) nounwind readnone
;
; Floating-point scalar convert to signed integer (to nearest with ties to even)
@@ -167,7 +167,7 @@ define i32 @fcvtns_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtns_1w1s:
;CHECK: fcvtns w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtns.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtns.i32.f32(float %A)
ret i32 %tmp3
}
@@ -175,7 +175,7 @@ define i64 @fcvtns_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtns_1x1s:
;CHECK: fcvtns x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtns.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtns.i64.f32(float %A)
ret i64 %tmp3
}
@@ -183,7 +183,7 @@ define i32 @fcvtns_1w1d(double %A) nounw
;CHECK-LABEL: fcvtns_1w1d:
;CHECK: fcvtns w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtns.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtns.i32.f64(double %A)
ret i32 %tmp3
}
@@ -191,14 +191,14 @@ define i64 @fcvtns_1x1d(double %A) nounw
;CHECK-LABEL: fcvtns_1x1d:
;CHECK: fcvtns x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtns.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtns.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtns.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtns.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtns.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtns.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtns.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtns.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtns.i64.f64(double) nounwind readnone
;
; Floating-point scalar convert to unsigned integer (to nearest with ties to even)
@@ -207,7 +207,7 @@ define i32 @fcvtnu_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtnu_1w1s:
;CHECK: fcvtnu w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtnu.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %A)
ret i32 %tmp3
}
@@ -215,7 +215,7 @@ define i64 @fcvtnu_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtnu_1x1s:
;CHECK: fcvtnu x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtnu.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float %A)
ret i64 %tmp3
}
@@ -223,7 +223,7 @@ define i32 @fcvtnu_1w1d(double %A) nounw
;CHECK-LABEL: fcvtnu_1w1d:
;CHECK: fcvtnu w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtnu.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double %A)
ret i32 %tmp3
}
@@ -231,14 +231,14 @@ define i64 @fcvtnu_1x1d(double %A) nounw
;CHECK-LABEL: fcvtnu_1x1d:
;CHECK: fcvtnu x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtnu.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtnu.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtnu.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtnu.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtnu.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double) nounwind readnone
;
; Floating-point scalar convert to signed integer (toward +Inf)
@@ -247,7 +247,7 @@ define i32 @fcvtps_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtps_1w1s:
;CHECK: fcvtps w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtps.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float %A)
ret i32 %tmp3
}
@@ -255,7 +255,7 @@ define i64 @fcvtps_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtps_1x1s:
;CHECK: fcvtps x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtps.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float %A)
ret i64 %tmp3
}
@@ -263,7 +263,7 @@ define i32 @fcvtps_1w1d(double %A) nounw
;CHECK-LABEL: fcvtps_1w1d:
;CHECK: fcvtps w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtps.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f64(double %A)
ret i32 %tmp3
}
@@ -271,14 +271,14 @@ define i64 @fcvtps_1x1d(double %A) nounw
;CHECK-LABEL: fcvtps_1x1d:
;CHECK: fcvtps x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtps.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtps.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtps.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtps.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtps.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtps.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtps.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtps.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtps.i64.f64(double) nounwind readnone
;
; Floating-point scalar convert to unsigned integer (toward +Inf)
@@ -287,7 +287,7 @@ define i32 @fcvtpu_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtpu_1w1s:
;CHECK: fcvtpu w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtpu.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float %A)
ret i32 %tmp3
}
@@ -295,7 +295,7 @@ define i64 @fcvtpu_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtpu_1x1s:
;CHECK: fcvtpu x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtpu.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float %A)
ret i64 %tmp3
}
@@ -303,7 +303,7 @@ define i32 @fcvtpu_1w1d(double %A) nounw
;CHECK-LABEL: fcvtpu_1w1d:
;CHECK: fcvtpu w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtpu.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtpu.i32.f64(double %A)
ret i32 %tmp3
}
@@ -311,14 +311,14 @@ define i64 @fcvtpu_1x1d(double %A) nounw
;CHECK-LABEL: fcvtpu_1x1d:
;CHECK: fcvtpu x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtpu.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtpu.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtpu.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtpu.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtpu.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtpu.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double) nounwind readnone
;
; Floating-point scalar convert to signed integer (toward zero)
@@ -327,7 +327,7 @@ define i32 @fcvtzs_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtzs_1w1s:
;CHECK: fcvtzs w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtzs.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %A)
ret i32 %tmp3
}
@@ -335,7 +335,7 @@ define i64 @fcvtzs_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtzs_1x1s:
;CHECK: fcvtzs x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtzs.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %A)
ret i64 %tmp3
}
@@ -343,7 +343,7 @@ define i32 @fcvtzs_1w1d(double %A) nounw
;CHECK-LABEL: fcvtzs_1w1d:
;CHECK: fcvtzs w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtzs.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f64(double %A)
ret i32 %tmp3
}
@@ -351,14 +351,14 @@ define i64 @fcvtzs_1x1d(double %A) nounw
;CHECK-LABEL: fcvtzs_1x1d:
;CHECK: fcvtzs x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtzs.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtzs.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtzs.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtzs.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtzs.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtzs.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double) nounwind readnone
;
; Floating-point scalar convert to unsigned integer (toward zero)
@@ -367,7 +367,7 @@ define i32 @fcvtzu_1w1s(float %A) nounwi
;CHECK-LABEL: fcvtzu_1w1s:
;CHECK: fcvtzu w0, s0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtzu.i32.f32(float %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %A)
ret i32 %tmp3
}
@@ -375,7 +375,7 @@ define i64 @fcvtzu_1x1s(float %A) nounwi
;CHECK-LABEL: fcvtzu_1x1s:
;CHECK: fcvtzu x0, s0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtzu.i64.f32(float %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float %A)
ret i64 %tmp3
}
@@ -383,7 +383,7 @@ define i32 @fcvtzu_1w1d(double %A) nounw
;CHECK-LABEL: fcvtzu_1w1d:
;CHECK: fcvtzu w0, d0
;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtzu.i32.f64(double %A)
+ %tmp3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f64(double %A)
ret i32 %tmp3
}
@@ -391,11 +391,11 @@ define i64 @fcvtzu_1x1d(double %A) nounw
;CHECK-LABEL: fcvtzu_1x1d:
;CHECK: fcvtzu x0, d0
;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtzu.i64.f64(double %A)
+ %tmp3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %A)
ret i64 %tmp3
}
-declare i32 @llvm.arm64.neon.fcvtzu.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtzu.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtzu.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtzu.i64.f64(double) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float) nounwind readnone
+declare i32 @llvm.aarch64.neon.fcvtzu.i32.f64(double) nounwind readnone
+declare i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double) nounwind readnone
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-convergence.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/dagcombiner-convergence.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-convergence.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-convergence.ll&p1=llvm/trunk/test/CodeGen/ARM64/dagcombiner-convergence.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/dagcombiner-dead-indexed-load.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll&p1=llvm/trunk/test/CodeGen/ARM64/dagcombiner-dead-indexed-load.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-indexed-load.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/dagcombiner-indexed-load.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-indexed-load.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-indexed-load.ll&p1=llvm/trunk/test/CodeGen/ARM64/dagcombiner-indexed-load.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/dagcombiner-load-slicing.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll&p1=llvm/trunk/test/CodeGen/ARM64/dagcombiner-load-slicing.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-dead-def-frame-index.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/dead-def-frame-index.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-dead-def-frame-index.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-dead-def-frame-index.ll&p1=llvm/trunk/test/CodeGen/ARM64/dead-def-frame-index.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/dead-register-def-bug.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll&p1=llvm/trunk/test/CodeGen/ARM64/dead-register-def-bug.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-dup.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/dup.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-dup.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-dup.ll&p1=llvm/trunk/test/CodeGen/ARM64/dup.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/dup.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-dup.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define <8 x i8> @v_dup8(i8 %A) nounwind {
;CHECK-LABEL: v_dup8:
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-early-ifcvt.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/early-ifcvt.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-early-ifcvt.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-early-ifcvt.ll&p1=llvm/trunk/test/CodeGen/ARM64/early-ifcvt.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-elf-calls.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/elf-calls.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-elf-calls.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-elf-calls.ll&p1=llvm/trunk/test/CodeGen/ARM64/elf-calls.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-elf-constpool.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/elf-constpool.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-elf-constpool.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-elf-constpool.ll&p1=llvm/trunk/test/CodeGen/ARM64/elf-constpool.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-elf-globals.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/elf-globals.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-elf-globals.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-elf-globals.ll&p1=llvm/trunk/test/CodeGen/ARM64/elf-globals.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-ext.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/ext.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ext.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-ext.ll&p1=llvm/trunk/test/CodeGen/ARM64/ext.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ext.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-ext.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: test_vextd:
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-extend-int-to-fp.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/extend-int-to-fp.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-extend-int-to-fp.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-extend-int-to-fp.ll&p1=llvm/trunk/test/CodeGen/ARM64/extend-int-to-fp.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/extend-int-to-fp.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-extend-int-to-fp.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
define <4 x float> @foo(<4 x i16> %a) nounwind {
; CHECK-LABEL: foo:
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-extend.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/extend.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-extend.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-extend.ll&p1=llvm/trunk/test/CodeGen/ARM64/extend.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-extern-weak.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/extern-weak.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-extern-weak.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-extern-weak.ll&p1=llvm/trunk/test/CodeGen/ARM64/extern-weak.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-extload-knownzero.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/extload-knownzero.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-extload-knownzero.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-extload-knownzero.ll&p1=llvm/trunk/test/CodeGen/ARM64/extload-knownzero.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-extract.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/extract.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-extract.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-extract.ll&p1=llvm/trunk/test/CodeGen/ARM64/extract.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/extract.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-extract.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc -arm64-extr-generation=true -verify-machineinstrs < %s \
+; RUN: llc -aarch64-extr-generation=true -verify-machineinstrs < %s \
; RUN: -march=arm64 | FileCheck %s
define i64 @ror_i64(i64 %in) {
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-extract_subvector.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/extract_subvector.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-extract_subvector.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-extract_subvector.ll&p1=llvm/trunk/test/CodeGen/ARM64/extract_subvector.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/extract_subvector.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-extract_subvector.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
+; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-addr-offset.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-addr-offset.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-br.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-br.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-br.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-br.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-br.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-call.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-call.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-call.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-conversion.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-conversion.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-gv.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-gv.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-gv.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-gv.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-gv.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-icmp.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-icmp.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-indirectbr.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-indirectbr.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-intrinsic.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-intrinsic.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-materialize.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-materialize.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-noconvert.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-noconvert.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-noconvert.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-noconvert.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-noconvert.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-rem.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-rem.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-rem.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-rem.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-rem.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-ret.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-ret.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-ret.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-ret.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-ret.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-select.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel-select.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-select.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-select.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel-select.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fast-isel.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll&p1=llvm/trunk/test/CodeGen/ARM64/fast-isel.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fastcc-tailcall.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll&p1=llvm/trunk/test/CodeGen/ARM64/fastcc-tailcall.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fastisel-gep-promote-before-add.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll&p1=llvm/trunk/test/CodeGen/ARM64/fastisel-gep-promote-before-add.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fcmp-opt.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fcmp-opt.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fcmp-opt.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fcmp-opt.ll&p1=llvm/trunk/test/CodeGen/ARM64/fcmp-opt.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fcmp-opt.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fcmp-opt.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -mcpu=cyclone -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
; rdar://10263824
define i1 @fcmp_float1(float %a) nounwind ssp {
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fcopysign.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fcopysign.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fcopysign.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fcopysign.ll&p1=llvm/trunk/test/CodeGen/ARM64/fcopysign.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fixed-point-scalar-cvt-dagcombine.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll&p1=llvm/trunk/test/CodeGen/ARM64/fixed-point-scalar-cvt-dagcombine.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fixed-point-scalar-cvt-dagcombine.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
; DAGCombine to transform a conversion of an extract_vector_elt to an
; extract_vector_elt of a conversion, which saves a round trip of copies
@@ -8,8 +8,8 @@ define double @foo0(<2 x i64> %a) nounwi
; CHECK: scvtf.2d [[REG:v[0-9]+]], v0, #9
; CHECK-NEXT: ins.d v0[0], [[REG]][1]
%vecext = extractelement <2 x i64> %a, i32 1
- %fcvt_n = tail call double @llvm.arm64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9)
+ %fcvt_n = tail call double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9)
ret double %fcvt_n
}
-declare double @llvm.arm64.neon.vcvtfxs2fp.f64.i64(i64, i32) nounwind readnone
+declare double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64, i32) nounwind readnone
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fmadd.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fmadd.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fmadd.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fmadd.ll&p1=llvm/trunk/test/CodeGen/ARM64/fmadd.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fmax.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fmax.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fmax.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fmax.ll&p1=llvm/trunk/test/CodeGen/ARM64/fmax.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Added: llvm/trunk/test/CodeGen/AArch64/arm64-fminv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fminv.ll?rev=209577&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fminv.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fminv.ll Sat May 24 07:50:23 2014
@@ -0,0 +1,101 @@
+; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
+
+define float @test_fminv_v2f32(<2 x float> %in) {
+; CHECK: test_fminv_v2f32:
+; CHECK: fminp s0, v0.2s
+ %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in)
+ ret float %min
+}
+
+define float @test_fminv_v4f32(<4 x float> %in) {
+; CHECK: test_fminv_v4f32:
+; CHECK: fminv s0, v0.4s
+ %min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in)
+ ret float %min
+}
+
+define double @test_fminv_v2f64(<2 x double> %in) {
+; CHECK: test_fminv_v2f64:
+; CHECK: fminp d0, v0.2d
+ %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in)
+ ret double %min
+}
+
+declare float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float>)
+declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
+declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>)
+
+define float @test_fmaxv_v2f32(<2 x float> %in) {
+; CHECK: test_fmaxv_v2f32:
+; CHECK: fmaxp s0, v0.2s
+ %max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in)
+ ret float %max
+}
+
+define float @test_fmaxv_v4f32(<4 x float> %in) {
+; CHECK: test_fmaxv_v4f32:
+; CHECK: fmaxv s0, v0.4s
+ %max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in)
+ ret float %max
+}
+
+define double @test_fmaxv_v2f64(<2 x double> %in) {
+; CHECK: test_fmaxv_v2f64:
+; CHECK: fmaxp d0, v0.2d
+ %max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in)
+ ret double %max
+}
+
+declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)
+declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
+declare double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double>)
+
+define float @test_fminnmv_v2f32(<2 x float> %in) {
+; CHECK: test_fminnmv_v2f32:
+; CHECK: fminnmp s0, v0.2s
+ %minnm = call float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float> %in)
+ ret float %minnm
+}
+
+define float @test_fminnmv_v4f32(<4 x float> %in) {
+; CHECK: test_fminnmv_v4f32:
+; CHECK: fminnmv s0, v0.4s
+ %minnm = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %in)
+ ret float %minnm
+}
+
+define double @test_fminnmv_v2f64(<2 x double> %in) {
+; CHECK: test_fminnmv_v2f64:
+; CHECK: fminnmp d0, v0.2d
+ %minnm = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> %in)
+ ret double %minnm
+}
+
+declare float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float>)
+declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
+declare double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double>)
+
+define float @test_fmaxnmv_v2f32(<2 x float> %in) {
+; CHECK: test_fmaxnmv_v2f32:
+; CHECK: fmaxnmp s0, v0.2s
+ %maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %in)
+ ret float %maxnm
+}
+
+define float @test_fmaxnmv_v4f32(<4 x float> %in) {
+; CHECK: test_fmaxnmv_v4f32:
+; CHECK: fmaxnmv s0, v0.4s
+ %maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %in)
+ ret float %maxnm
+}
+
+define double @test_fmaxnmv_v2f64(<2 x double> %in) {
+; CHECK: test_fmaxnmv_v2f64:
+; CHECK: fmaxnmp d0, v0.2d
+ %maxnm = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)
+ ret double %maxnm
+}
+
+declare float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float>)
+declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)
+declare double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double>)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fmuladd.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fmuladd.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fmuladd.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fmuladd.ll&p1=llvm/trunk/test/CodeGen/ARM64/fmuladd.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fmuladd.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fmuladd.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc -asm-verbose=false < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc -asm-verbose=false < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
define float @test_f32(float* %A, float* %B, float* %C) nounwind {
;CHECK-LABEL: test_f32:
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fold-address.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fold-address.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fold-address.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fold-address.ll&p1=llvm/trunk/test/CodeGen/ARM64/fold-address.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fold-lsl.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fold-lsl.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fold-lsl.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fold-lsl.ll&p1=llvm/trunk/test/CodeGen/ARM64/fold-lsl.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fold-lsl.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fold-lsl.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
;
; <rdar://problem/14486451>
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fp-contract-zero.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fp-contract-zero.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fp-contract-zero.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fp-contract-zero.ll&p1=llvm/trunk/test/CodeGen/ARM64/fp-contract-zero.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fp-imm.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fp-imm.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fp-imm.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fp-imm.ll&p1=llvm/trunk/test/CodeGen/ARM64/fp-imm.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fp.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fp.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fp.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fp.ll&p1=llvm/trunk/test/CodeGen/ARM64/fp.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fp128-folding.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fp128-folding.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fp128-folding.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fp128-folding.ll&p1=llvm/trunk/test/CodeGen/ARM64/fp128-folding.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-fp128.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/fp128.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fp128.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-fp128.ll&p1=llvm/trunk/test/CodeGen/ARM64/fp128.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-frame-index.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/frame-index.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-frame-index.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-frame-index.ll&p1=llvm/trunk/test/CodeGen/ARM64/frame-index.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-frameaddr.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/frameaddr.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-frameaddr.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-frameaddr.ll&p1=llvm/trunk/test/CodeGen/ARM64/frameaddr.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-global-address.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/global-address.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-global-address.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-global-address.ll&p1=llvm/trunk/test/CodeGen/ARM64/global-address.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/hello.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-hello.ll&p1=llvm/trunk/test/CodeGen/ARM64/hello.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/i16-subreg-extract.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll&p1=llvm/trunk/test/CodeGen/ARM64/i16-subreg-extract.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/i16-subreg-extract.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
define i32 @foo(<4 x i16>* %__a) nounwind {
; CHECK-LABEL: foo:
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-icmp-opt.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/icmp-opt.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-icmp-opt.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-icmp-opt.ll&p1=llvm/trunk/test/CodeGen/ARM64/icmp-opt.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-illegal-float-ops.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/illegal-float-ops.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-illegal-float-ops.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-illegal-float-ops.ll&p1=llvm/trunk/test/CodeGen/ARM64/illegal-float-ops.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-indexed-memory.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/indexed-memory.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-indexed-memory.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-indexed-memory.ll&p1=llvm/trunk/test/CodeGen/ARM64/indexed-memory.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/indexed-memory.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-indexed-memory.ll Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm64 -arm64-redzone | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-redzone | FileCheck %s
define void @store64(i64** nocapture %out, i64 %index, i64 %spacing) nounwind noinline ssp {
; CHECK-LABEL: store64:
Copied: llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll (from r209576, llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll?p2=llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll&p1=llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
More information about the llvm-commits
mailing list