[PATCH] InstCombine Check if Signed Addition Overflows

[Jingyue Wu]

Nice work!

+      if (RHSKnownOne.countPopulation() == 1) {

This looks too aggressive. Are you supposed to say there are (BitWidth - 1)
known zeros? Do you also need to check this single one-bit is not the sign
bit or is it implied by some later conditions?
+        // Ignore Sign Bit.



On Sun, May 18, 2014 at 9:49 PM, suyog sarda <sardask01 at gmail.com> wrote:

> Gentle Ping !! Please help in reviewing the patch.
>
>
> ---------- Forwarded message ----------
> From: suyog sarda <sardask01 at gmail.com>
> Date: Fri, May 16, 2014 at 6:09 PM
> Subject: Fwd: [PATCH] InstCombine Check if Signed Addition Overflows
> To: benny.kra at gmail.com, david.majnemer at gmail.com,
> rafael.espindola at gmail.com
>
>
> Hi David, Ben, Rafael,
>
> Please help in reviewing the patch.
>
> ---------- Forwarded message ----------
> From: suyog sarda <sardask01 at gmail.com>
> Date: Thu, May 15, 2014 at 10:12 PM
> Subject: [PATCH] Check if Signed Addition Overflows
> To: llvm-commits at cs.uiuc.edu
>
>
>  Hi,
>
> Attaching patch for checking if Signed Addition overflows.
> This patch implements two things :
>
> 1. If we know one number is positive and another is negative, we return
> true as signed addition of two opposite signed numbers will never overflow.
>
> 2. Implemented TODO : If one of the operands only has one non-zero bit,
> and if the other operand has a known-zero bit in a more significant place
> than it (not including the sign bit) the ripple may go up to and fill the
> zero, but won't change the sign.
> e.x -  (x & ~4) + 1
> We make sure that we are ignoring 0 at MSB.
>
> 3 Test case included :
>
> 1. To check if 0 in one number is at more significant place than 1 in
> second number. We emit 'add nsw' as we are sure there will be no overflow
> as the ripple will die at that zero.
> 2. If 0 is at less significant place than one, then emit normal 'add' as
> we are not sure if the ripple will die before reaching Sign bit.
> 3. IF the two numbers are of opposite sign, we emit 'add nsw' as we are
> sure that it will never overflow.
>
> Please help in reviewing the patch.
>
> --
> With regards,
> Suyog Sarda
>
>
>
> --
> With regards,
> Suyog Sarda
>
>
>
> --
> With regards,
> Suyog Sarda
>
> _______________________________________________
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> llvm-commits at cs.uiuc.edu
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>
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