[llvm] r209027 - R600/SI: Add a PredicateControl class for managing TableGen predicates
Tom Stellard
thomas.stellard at amd.com
Fri May 16 13:56:45 PDT 2014
Author: tstellar
Date: Fri May 16 15:56:45 2014
New Revision: 209027
URL: http://llvm.org/viewvc/llvm-project?rev=209027&view=rev
Log:
R600/SI: Add a PredicateControl class for managing TableGen predicates
This was inspired by the PredicateControl class in the MIPS backend.
Modified:
llvm/trunk/lib/Target/R600/AMDGPU.td
llvm/trunk/lib/Target/R600/SIInstrFormats.td
llvm/trunk/lib/Target/R600/SIInstructions.td
Modified: llvm/trunk/lib/Target/R600/AMDGPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPU.td?rev=209027&r1=209026&r2=209027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPU.td (original)
+++ llvm/trunk/lib/Target/R600/AMDGPU.td Fri May 16 15:56:45 2014
@@ -120,6 +120,17 @@ def AMDGPU : Target {
let InstructionSet = AMDGPUInstrInfo;
}
+//===----------------------------------------------------------------------===//
+// Predicate helper class
+//===----------------------------------------------------------------------===//
+
+class PredicateControl {
+ Predicate SubtargetPredicate;
+ list<Predicate> OtherPredicates = [];
+ list<Predicate> Predicates = !listconcat([SubtargetPredicate],
+ OtherPredicates);
+}
+
// Include AMDGPU TD files
include "R600Schedule.td"
include "SISchedule.td"
Modified: llvm/trunk/lib/Target/R600/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrFormats.td?rev=209027&r1=209026&r2=209027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrFormats.td Fri May 16 15:56:45 2014
@@ -12,7 +12,7 @@
//===----------------------------------------------------------------------===//
class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
- AMDGPUInst<outs, ins, asm, pattern> {
+ AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
field bits<1> VM_CNT = 0;
field bits<1> EXP_CNT = 0;
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=209027&r1=209026&r2=209027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Fri May 16 15:56:45 2014
@@ -36,12 +36,13 @@ def isCFDepth0 : Predicate<"isCFDepth0()
def WAIT_FLAG : InstFlag<"printWaitFlag">;
+let SubtargetPredicate = isSI in {
+let OtherPredicates = [isCFDepth0] in {
+
//===----------------------------------------------------------------------===//
// SMRD Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [isSI, isCFDepth0] in {
-
let mayLoad = 1 in {
// We are using the SGPR_32 and not the SReg_32 register class for 32-bit
@@ -78,14 +79,10 @@ defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helpe
//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
-} // let Predicates = [isSI, isCFDepth0]
-
//===----------------------------------------------------------------------===//
// SOP1 Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [isSI, isCFDepth0] in {
-
let neverHasSideEffects = 1 in {
let isMoveImm = 1 in {
@@ -158,14 +155,10 @@ def S_MOV_REGRD_B32 : SOP1_32 <0x0000003
def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
-} // let Predicates = [isSI, isCFDepth0]
-
//===----------------------------------------------------------------------===//
// SOP2 Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [isSI, isCFDepth0] in {
-
let Defs = [SCC] in { // Carry out goes to SCC
let isCommutable = 1 in {
def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
@@ -279,14 +272,10 @@ def S_BFE_I64 : SOP2_64 <0x0000002a, "S_
//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
-} // let Predicates = [isSI, isCFDepth0]
-
//===----------------------------------------------------------------------===//
// SOPC Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [isSI, isCFDepth0] in {
-
def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
@@ -305,14 +294,10 @@ def S_CMP_LE_U32 : SOPC_32 <0x0000000b,
////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
-} // let Predicates = [isSI, isCFDepth0]
-
//===----------------------------------------------------------------------===//
// SOPK Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [isSI, isCFDepth0] in {
-
def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
@@ -361,14 +346,12 @@ def S_GETREG_REGRD_B32 : SOPK_32 <0x0000
//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
//def EXP : EXP_ <0x00000000, "EXP", []>;
-} // let Predicates = [isSI, isCFDepth0]
+} // End let OtherPredicates = [isCFDepth0]
//===----------------------------------------------------------------------===//
// SOPP Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [isSI] in {
-
def S_NOP : SOPP <0x00000000, (ins i16imm:$SIMM16), "S_NOP $SIMM16", []>;
let isTerminator = 1 in {
@@ -461,10 +444,6 @@ let Uses = [EXEC] in {
//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
} // End hasSideEffects
-} // let Predicates = [isSI, isCFDepth0]
-
-let Predicates = [isSI] in {
-
//===----------------------------------------------------------------------===//
// VOPC Instructions
//===----------------------------------------------------------------------===//
@@ -1457,7 +1436,7 @@ let Uses = [EXEC], Defs = [EXEC,VCC,M0]
let UseNamedOperandTable = 1 in {
-def SI_RegisterLoad : AMDGPUShaderInst <
+def SI_RegisterLoad : InstSI <
(outs VReg_32:$dst, SReg_64:$temp),
(ins FRAMEri32:$addr, i32imm:$chan),
"", []
@@ -1466,7 +1445,7 @@ def SI_RegisterLoad : AMDGPUShaderInst <
let mayLoad = 1;
}
-class SIRegStore<dag outs> : AMDGPUShaderInst <
+class SIRegStore<dag outs> : InstSI <
outs,
(ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
"", []
@@ -1549,6 +1528,10 @@ defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg
} // end IsCodeGenOnly, isPseudo
+} // end SubtargetPredicate = SI
+
+let Predicates = [isSI] in {
+
def : Pat<
(int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
(V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
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