[PATCH] [ARM64] Implement NEON post-increment LD1 (lane) and post-increment LD1R

[Tim Northover]

Hi Hao,

> This patch has two steps:
>       (1) do post LD1 combine in ARM64ISelLowing
>       (2) do select post LD1 in ARM64ISelDAGToDAG
> So you mean it's better to not to do post LD1 combine in ARM64ISelLowering? We can do such combine and select in one step in ARM64ISelDAGToDAG?

No need to take it as a suggestion: it was just a vague desire for the
future really.

> If so, considering other post NEON load/store like LD2/LD3/LD4 are also implemented in two steps, they also need to be refactored.

The main difference there, as I see it, is that they're *already*
intrinsics coming into the DAG. We're definitely not going to be
missing out on any generic DAG combines by fiddling them a bit more.
The same can't necessarily be said for more generic ISD::LOADs.

That said, the LD2/LD3/LD4 situation did help convince me that doing
it in ISelLowering wasn't too bad.

Cheers.

Tim.

http://reviews.llvm.org/D3740