[PATCH] Fix and enable the Load/Store optimisation pass for Thumb1

[Moritz Roth]

Hi Renato,

thanks a lot for the feedback. I've updated my diff with the changes.

Changing the UpdateBaseRegUses function wasn't quite as easy as I thought, as there are various parts of the code that are duplicated but with subtle differences (some branches return, others don't etc). I tried a few things as you suggested and ended up with a much nicer function, so let me know what you think. It looks like the conditional over the loop body has to stay there an instruction can both read and kill the base register, in which case we might still have to insert a SUB.

Regarding the tests, I fully agree with you. There is a test case for STR->STM merging in patch 0004 (a fairly trivial / small patch, see my mail on the list), which uses memcpy to generate the chain of LDM/STM to be merged. If you want, I could of course change it and include it with this commit. James said he'd take care of the commits when code review is complete so he'll make sure that this test is pushed at the same time as the patch.

Cheers 
Moritz

http://reviews.llvm.org/D3757

Files:
  lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  lib/Target/ARM/README-Thumb.txt
  test/CodeGen/Thumb/dyn-stackalloc.ll
  test/CodeGen/Thumb/thumb-ldm.ll
  test/CodeGen/Thumb2/thumb2-ldm.ll
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