[PATCH] R600: Add intrinsics for mad24
Tom Stellard
tom at stellard.net
Thu May 15 06:17:39 PDT 2014
On Sat, May 10, 2014 at 10:50:55PM +0000, Matt Arsenault wrote:
> Forgot to attach tests
>
> http://reviews.llvm.org/D3715
>
> Files:
> lib/Target/R600/AMDGPUISelLowering.cpp
> lib/Target/R600/AMDGPUISelLowering.h
> lib/Target/R600/AMDGPUInstrInfo.td
> lib/Target/R600/AMDGPUInstructions.td
> lib/Target/R600/AMDGPUIntrinsics.td
> lib/Target/R600/CaymanInstructions.td
> lib/Target/R600/SIInstructions.td
> test/CodeGen/R600/llvm.AMDGPU.imad24.ll
> test/CodeGen/R600/llvm.AMDGPU.umad24.ll
> Index: lib/Target/R600/AMDGPUISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.cpp
> +++ lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -702,6 +702,14 @@
> return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
> Op.getOperand(1), Op.getOperand(2));
>
> + case AMDGPUIntrinsic::AMDGPU_umad24:
> + return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
> + Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
> +
> + case AMDGPUIntrinsic::AMDGPU_imad24:
> + return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
> + Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
> +
> case AMDGPUIntrinsic::AMDGPU_bfe_i32:
> return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
> Op.getOperand(1),
> @@ -1399,6 +1407,8 @@
> NODE_NAME_CASE(BFM)
> NODE_NAME_CASE(MUL_U24)
> NODE_NAME_CASE(MUL_I24)
> + NODE_NAME_CASE(MAD_U24)
> + NODE_NAME_CASE(MAD_I24)
> NODE_NAME_CASE(URECIP)
> NODE_NAME_CASE(DOT4)
> NODE_NAME_CASE(EXPORT)
> Index: lib/Target/R600/AMDGPUISelLowering.h
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.h
> +++ lib/Target/R600/AMDGPUISelLowering.h
> @@ -187,6 +187,8 @@
> BFM, // Insert a range of bits into a 32-bit word.
> MUL_U24,
> MUL_I24,
> + MAD_U24,
> + MAD_I24,
> TEXTURE_FETCH,
> EXPORT,
> CONST_ADDRESS,
> Index: lib/Target/R600/AMDGPUInstrInfo.td
> ===================================================================
> --- lib/Target/R600/AMDGPUInstrInfo.td
> +++ lib/Target/R600/AMDGPUInstrInfo.td
> @@ -100,3 +100,10 @@
> def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
> [SDNPCommutative]
> >;
> +
> +def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
> + []
> +>;
> +def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
> + []
> +>;
> Index: lib/Target/R600/AMDGPUInstructions.td
> ===================================================================
> --- lib/Target/R600/AMDGPUInstructions.td
> +++ lib/Target/R600/AMDGPUInstructions.td
> @@ -423,6 +423,17 @@
> >;
> */
>
> +class IMad24Pat<Instruction Inst> : Pat <
> + (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
> + (Inst $src0, $src1, $src2)
> +>;
> +
> +class UMad24Pat<Instruction Inst> : Pat <
> + (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
> + (Inst $src0, $src1, $src2)
> +>;
> +
> +
> include "R600Instructions.td"
> include "R700Instructions.td"
> include "EvergreenInstructions.td"
> Index: lib/Target/R600/AMDGPUIntrinsics.td
> ===================================================================
> --- lib/Target/R600/AMDGPUIntrinsics.td
> +++ lib/Target/R600/AMDGPUIntrinsics.td
> @@ -51,6 +51,8 @@
> def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_umul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_imul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_imad24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_umad24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
> def int_AMDGPU_bfi : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_bfe_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> Index: lib/Target/R600/CaymanInstructions.td
> ===================================================================
> --- lib/Target/R600/CaymanInstructions.td
> +++ lib/Target/R600/CaymanInstructions.td
> @@ -21,12 +21,14 @@
> let Predicates = [isCayman] in {
>
> def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24",
> - [(set i32:$dst, (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2))], VecALU
> + [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU
> >;
> def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
> [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU
> >;
>
> +def : IMad24Pat<MULADD_INT24_cm>;
> +
We need to add a fall-back pattern for targets that don't support 24-bit
ops. Pre-Evergreen doesn't have 24-bit ops and Evergreen only supports 24-bit
unsigned operations.
-Tom
> let isVector = 1 in {
>
> def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
> Index: lib/Target/R600/SIInstructions.td
> ===================================================================
> --- lib/Target/R600/SIInstructions.td
> +++ lib/Target/R600/SIInstructions.td
> @@ -1281,13 +1281,17 @@
> def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
> def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
> def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
> - [(set i32:$dst, (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2))]
> + [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))]
> >;
> def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
> - [(set i32:$dst, (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2))]
> + [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))]
> >;
>
> } // End neverHasSideEffects
> +
> +def : IMad24Pat<V_MAD_I32_I24>;
> +def : UMad24Pat<V_MAD_U32_U24>;
> +
> def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
> def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
> def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
> Index: test/CodeGen/R600/llvm.AMDGPU.imad24.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/llvm.AMDGPU.imad24.ll
> @@ -0,0 +1,14 @@
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> +; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
> +
> +declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) nounwind readnone
> +
> +; FUNC-LABEL: @test_imad24
> +; SI: V_MAD_I32_I24
> +; CM: MULADD_INT24
> +define void @test_imad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
> + %mad = call i32 @llvm.AMDGPU.imad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone
> + store i32 %mad, i32 addrspace(1)* %out, align 4
> + ret void
> +}
> +
> Index: test/CodeGen/R600/llvm.AMDGPU.umad24.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/llvm.AMDGPU.umad24.ll
> @@ -0,0 +1,12 @@
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> +
> +declare i32 @llvm.AMDGPU.umad24(i32, i32, i32) nounwind readnone
> +
> +; FUNC-LABEL: @test_umad24
> +; SI: V_MAD_U32_U24
> +define void @test_umad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
> + %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone
> + store i32 %mad, i32 addrspace(1)* %out, align 4
> + ret void
> +}
> +
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