[llvm] r208877 - [mips][mips64r6] Add bitswap, and dbitswap
Daniel Sanders
daniel.sanders at imgtec.com
Thu May 15 05:18:24 PDT 2014
Author: dsanders
Date: Thu May 15 07:18:23 2014
New Revision: 208877
URL: http://llvm.org/viewvc/llvm-project?rev=208877&view=rev
Log:
[mips][mips64r6] Add bitswap, and dbitswap
Summary: Depends on D3728
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3729
Modified:
llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td?rev=208877&r1=208876&r2=208877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td Thu May 15 07:18:23 2014
@@ -47,8 +47,10 @@ def OPCODE5_DATI : OPCODE5<0b11110>;
class OPCODE6<bits<6> Val> {
bits<6> Value = Val;
}
-def OPCODE6_ALIGN : OPCODE6<0b100000>;
-def OPCODE6_DALIGN : OPCODE6<0b100100>;
+def OPCODE6_ALIGN : OPCODE6<0b100000>;
+def OPCODE6_DALIGN : OPCODE6<0b100100>;
+def OPCODE6_BITSWAP : OPCODE6<0b100000>;
+def OPCODE6_DBITSWAP : OPCODE6<0b100100>;
class FIELD_FMT<bits<5> Val> {
bits<5> Value = Val;
@@ -118,6 +120,20 @@ class PCREL19_FM<OPCODE2 Operation> : Mi
let Inst{18-0} = imm;
}
+class SPECIAL3_2R_FM<OPCODE6 Operation> : MipsR6Inst {
+ bits<5> rd;
+ bits<5> rt;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = OPGROUP_SPECIAL3.Value;
+ let Inst{25-21} = 0b00000;
+ let Inst{20-16} = rt;
+ let Inst{15-11} = rd;
+ let Inst{10-6} = 0b00000;
+ let Inst{5-0} = Operation.Value;
+}
+
class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
bits<5> rd;
bits<5> rs;
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=208877&r1=208876&r2=208877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Thu May 15 07:18:23 2014
@@ -63,6 +63,7 @@ class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPC
class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
class AUI_ENC : AUI_FM;
class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
+class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
@@ -118,6 +119,15 @@ class AUI_DESC_BASE<string instr_asm, Re
class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
+class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
+ dag OutOperandList = (outs GPROpnd:$rd);
+ dag InOperandList = (ins GPROpnd:$rt);
+ string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
+ list<dag> Pattern = [];
+}
+
+class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
+
class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
@@ -179,7 +189,7 @@ def BGEZALC;
def BGEZC;
def BGTZALC;
def BGTZC;
-def BITSWAP; // Known as BITREV in DSP ASE
+def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
def BLEZALC;
def BLEZC;
def BLTC; // Also aliased to bgtc with operands swapped
Modified: llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td?rev=208877&r1=208876&r2=208877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td Thu May 15 07:18:23 2014
@@ -29,6 +29,7 @@ class DALIGN_ENC : SPECIAL3_DALIGN_FM<O
class DAUI_ENC : DAUI_FM;
class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
+class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
@@ -48,6 +49,7 @@ class DALIGN_DESC : ALIGN_DESC_BASE<"da
class DAHI_DESC : AUI_DESC_BASE<"dahi", GPR64Opnd>;
class DATI_DESC : AUI_DESC_BASE<"dati", GPR64Opnd>;
class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>;
+class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd>;
class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd>;
class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd>;
@@ -67,7 +69,7 @@ def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS
def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
-def DBITSWAP;
+def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
// def DLSA; // See MSA
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=208877&r1=208876&r2=208877&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Thu May 15 07:18:23 2014
@@ -9,6 +9,7 @@
aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
+ bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20]
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=208877&r1=208876&r2=208877&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Thu May 15 07:18:23 2014
@@ -9,10 +9,12 @@
aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
+ bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20]
dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
dahi $3,$3,0x5678 # CHECK: dahi $3, $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
dati $3,$3,0xabcd # CHECK: dati $3, $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd]
+ dbitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24]
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
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