[llvm] r208864 - [ARM64] Improve load/store diagnostics and forbid 32-bit register addresses

[Bradley Smith]

Author: brasmi01
Date: Thu May 15 06:08:30 2014
New Revision: 208864

URL: http://llvm.org/viewvc/llvm-project?rev=208864&view=rev
Log:
[ARM64] Improve load/store diagnostics and forbid 32-bit register addresses

Modified:
    llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
    llvm/trunk/test/MC/ARM64/diags.s

Modified: llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp?rev=208864&r1=208863&r2=208864&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp Thu May 15 06:08:30 2014
@@ -2985,12 +2985,16 @@ bool ARM64AsmParser::parseMemory(Operand
   Parser.Lex(); // Eat left bracket token.
 
   const AsmToken &BaseRegTok = Parser.getTok();
+  SMLoc BaseRegLoc = BaseRegTok.getLoc();
   if (BaseRegTok.isNot(AsmToken::Identifier))
-    return Error(BaseRegTok.getLoc(), "register expected");
+    return Error(BaseRegLoc, "register expected");
 
   int64_t Reg = tryParseRegister();
   if (Reg == -1)
-    return Error(BaseRegTok.getLoc(), "register expected");
+    return Error(BaseRegLoc, "register expected");
+
+  if (!ARM64MCRegisterClasses[ARM64::GPR64spRegClassID].contains(Reg))
+    return Error(BaseRegLoc, "invalid operand for instruction");
 
   // If there is an offset expression, parse it.
   const MCExpr *OffsetExpr = nullptr;
@@ -4148,6 +4152,10 @@ bool ARM64AsmParser::MatchAndEmitInstruc
       // diagnose.
       MatchResult = Match_InvalidMemoryIndexed;
     }
+    else if(Operands.size() == 3 && Operands.size() == ErrorInfo + 1 &&
+            ((ARM64Operand *)Operands[ErrorInfo])->isImm()) {
+      MatchResult = Match_InvalidLabel;
+    }
     SMLoc ErrorLoc = ((ARM64Operand *)Operands[ErrorInfo])->getStartLoc();
     if (ErrorLoc == SMLoc())
       ErrorLoc = IDLoc;
@@ -4172,6 +4180,7 @@ bool ARM64AsmParser::MatchAndEmitInstruc
   case Match_InvalidMovImm32Shift:
   case Match_InvalidMovImm64Shift:
   case Match_InvalidFPImm:
+  case Match_InvalidMemoryIndexed:
   case Match_InvalidMemoryIndexed8:
   case Match_InvalidMemoryIndexed16:
   case Match_InvalidMemoryIndexed32SImm7:

Modified: llvm/trunk/test/MC/ARM64/diags.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/diags.s?rev=208864&r1=208863&r2=208864&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/diags.s (original)
+++ llvm/trunk/test/MC/ARM64/diags.s Thu May 15 06:08:30 2014
@@ -42,15 +42,15 @@ foo:
 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
 ; CHECK-ERRORS:         ldr x0, [x0, #804]!
 ; CHECK-ERRORS:                 ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
+; CHECK-ERRORS: error: invalid operand for instruction
 ; CHECK-ERRORS:         ldr w0, [w0, #301]!
-; CHECK-ERRORS:                 ^
+; CHECK-ERRORS:                  ^
 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
 ; CHECK-ERRORS:         ldr x0, [x0], #804
 ; CHECK-ERRORS:                       ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
+; CHECK-ERRORS: error: invalid operand for instruction
 ; CHECK-ERRORS:         ldr w0, [w0], #301
-; CHECK-ERRORS:                       ^
+; CHECK-ERRORS:                  ^
 ; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
 ; CHECK-ERRORS:         ldp w3, w4, [x5, #11]!
 ; CHECK-ERRORS:                     ^