[PATCH] [ARM64] Implement NEON post-increment LD1 (lane) and post-increment LD1R

[Hao Liu]

Hi t.p.northover,

Hi Tim,

This patch implements post-increment LD1 (lane) and post-increment LD1R. The implementation is like the implementation of NEON post-increment load with 2/3/4 vectors.
It tries to do the following 2 combines if satisfied:
  (1) combine an ARM64ISD:DUP and a post-increment load into a post-increment LD1R.
  (2) combine an ISD::INSERT_VECTOR_ELT and a post-increment load into a post-increment LD1 (lane).

Ask for code review.

Thanks,
-Hao

http://reviews.llvm.org/D3740

Files:
  lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
  lib/Target/ARM64/ARM64ISelLowering.cpp
  lib/Target/ARM64/ARM64ISelLowering.h
  test/CodeGen/ARM64/indexed-vector-ldst.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D3740.9340.patch
Type: text/x-patch
Size: 30700 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20140513/81a7632c/attachment.bin>