[llvm] r208620 - Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb

[Reid Kleckner]

Thanks!


On Mon, May 12, 2014 at 3:21 PM, Louis Gerbarg <lgg at apple.com> wrote:

> Committed r208638.
>
> Louis
>
> On May 12, 2014, at 3:12 PM, Louis Gerbarg <lgg at apple.com> wrote:
>
> I’ll submit something in sec.
>
> Louis
>
> On May 12, 2014, at 3:09 PM, Reid Kleckner <rnk at google.com> wrote:
>
> This test fails on Windows:
> http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/2682
>
> The Windows target is thumb-only.  You need to add a triple.
>
>
> On Mon, May 12, 2014 at 12:53 PM, Louis Gerbarg <lgg at apple.com> wrote:
>
>> Author: louis
>> Date: Mon May 12 14:53:52 2014
>> New Revision: 208620
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=208620&view=rev
>> Log:
>> Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb
>>
>> The current patterns for REV16 misses mostn __builtin_bswap16() due to
>> legalization promoting the operands to from load/stores toi32s and then
>> truncing/extending them. This patch adds new patterns that catch the
>> resultant
>> DAGs and codegens them to rev16 instructions. Tests included.
>>
>> rdar://15353652
>>
>> Added:
>>     llvm/trunk/test/CodeGen/ARM/bswap16.ll
>> Modified:
>>     llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>>     llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=208620&r1=208619&r2=208620&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon May 12 14:53:52 2014
>> @@ -4122,6 +4122,11 @@ def REV16 : AMiscA1I<0b01101011, 0b1011,
>>                 Requires<[IsARM, HasV6]>,
>>             Sched<[WriteALU]>;
>>
>> +def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
>> +              (REV16 (LDRH addrmode3:$addr))>;
>> +def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)),
>> addrmode3:$addr),
>> +               (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
>> +
>>  let AddedComplexity = 5 in
>>  def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
>>                 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=208620&r1=208619&r2=208620&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon May 12 14:53:52 2014
>> @@ -1308,6 +1308,18 @@ def : T1Pat<(addc   tGPR:$lhs, imm8_255_
>>  def : T1Pat<(subc   tGPR:$lhs, tGPR:$rhs),
>>              (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
>>
>> +// Bswap 16 with load/store
>> +def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rrs2:$addr)), (i32 16)),
>> +            (tREV16 (tLDRHr t_addrmode_rrs2:$addr))>;
>> +def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
>> +            (tREV16 (tLDRHi t_addrmode_is2:$addr))>;
>> +def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
>> +                           t_addrmode_rrs2:$addr),
>> +            (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rrs2:$addr)>;
>> +def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
>> +                           t_addrmode_is2:$addr),
>> +            (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>;
>> +
>>  // ConstantPool
>>  def : T1Pat<(ARMWrapper  tconstpool  :$dst), (tLEApcrel tconstpool
>>  :$dst)>;
>>
>>
>> Added: llvm/trunk/test/CodeGen/ARM/bswap16.ll
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bswap16.ll?rev=208620&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/bswap16.ll (added)
>> +++ llvm/trunk/test/CodeGen/ARM/bswap16.ll Mon May 12 14:53:52 2014
>> @@ -0,0 +1,42 @@
>> +; RUN: llc -march=arm  -mattr=v6 < %s | FileCheck %s
>> +; RUN: llc -march=thumb  -mattr=v6 < %s | FileCheck %s
>> +
>> +
>> +define void @test1(i16* nocapture %data) {
>> +entry:
>> +  %0 = load i16* %data, align 2
>> +  %1 = tail call i16 @llvm.bswap.i16(i16 %0)
>> +  store i16 %1, i16* %data, align 2
>> +  ret void
>> +
>> +  ; CHECK-LABEL: test1:
>> +  ; CHECK: ldrh r[[R1:[0-9]+]], [r0]
>> +  ; CHECK: rev16 r[[R1]], r[[R1]]
>> +  ; CHECK: strh r[[R1]], [r0]
>> +}
>> +
>> +
>> +define void @test2(i16* nocapture %data, i16 zeroext %in) {
>> +entry:
>> +  %0 = tail call i16 @llvm.bswap.i16(i16 %in)
>> +  store i16 %0, i16* %data, align 2
>> +  ret void
>> +
>> +  ; CHECK-LABEL: test2:
>> +  ; CHECK: rev16 r[[R1:[0-9]+]], r1
>> +  ; CHECK: strh r[[R1]], [r0]
>> +}
>> +
>> +
>> +define i16 @test3(i16* nocapture %data) {
>> +entry:
>> +  %0 = load i16* %data, align 2
>> +  %1 = tail call i16 @llvm.bswap.i16(i16 %0)
>> +  ret i16 %1
>> +
>> +  ; CHECK-LABEL: test3:
>> +  ; CHECK: ldrh r[[R0:[0-9]+]], [r0]
>> +  ; CHECK: rev16 r[[R0]], r0
>> +}
>> +
>> +declare i16 @llvm.bswap.i16(i16)
>>
>>
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