[PATCH] R600: Add mul24 intrinsics
Tom Stellard
tom at stellard.net
Mon May 12 10:46:25 PDT 2014
On Sat, May 10, 2014 at 06:02:40PM +0000, Matt Arsenault wrote:
> http://reviews.llvm.org/D3713
>
LGTM.
> Files:
> lib/Target/R600/AMDGPUISelLowering.cpp
> lib/Target/R600/AMDGPUIntrinsics.td
> lib/Target/R600/AMDILIntrinsics.td
> test/CodeGen/R600/llvm.AMDGPU.imul24.ll
> test/CodeGen/R600/llvm.AMDGPU.umul24.ll
>
> Index: lib/Target/R600/AMDGPUISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.cpp
> +++ lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -762,6 +762,14 @@
> return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
> Op.getOperand(2));
>
> + case AMDGPUIntrinsic::AMDGPU_imul24:
> + return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
> + Op.getOperand(1), Op.getOperand(2));
> +
> + case AMDGPUIntrinsic::AMDGPU_umul24:
> + return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
> + Op.getOperand(1), Op.getOperand(2));
> +
> case AMDGPUIntrinsic::AMDGPU_bfe_i32:
> return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
> Op.getOperand(1),
> Index: lib/Target/R600/AMDGPUIntrinsics.td
> ===================================================================
> --- lib/Target/R600/AMDGPUIntrinsics.td
> +++ lib/Target/R600/AMDGPUIntrinsics.td
> @@ -49,6 +49,8 @@
> def int_AMDGPU_imin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_imul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_umul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
> def int_AMDGPU_bfi : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_bfe_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> Index: lib/Target/R600/AMDILIntrinsics.td
> ===================================================================
> --- lib/Target/R600/AMDILIntrinsics.td
> +++ lib/Target/R600/AMDILIntrinsics.td
> @@ -92,10 +92,6 @@
> BinaryIntInt;
> def int_AMDIL_mulhi_u32 : GCCBuiltin<"__amdil_umul_high">,
> BinaryIntInt;
> - def int_AMDIL_mul24_i32 : GCCBuiltin<"__amdil_imul24">,
> - BinaryIntInt;
> - def int_AMDIL_mul24_u32 : GCCBuiltin<"__amdil_umul24">,
> - BinaryIntInt;
> def int_AMDIL_mulhi24_i32 : GCCBuiltin<"__amdil_imul24_high">,
> BinaryIntInt;
> def int_AMDIL_mulhi24_u32 : GCCBuiltin<"__amdil_umul24_high">,
> Index: test/CodeGen/R600/llvm.AMDGPU.imul24.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/llvm.AMDGPU.imul24.ll
> @@ -0,0 +1,14 @@
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> +; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
> +
> +declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone
> +
> +; FUNC-LABEL: @test_imul24
> +; SI: V_MUL_I32_I24
> +; CM: MUL_INT24
> +define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
> + %mul = call i32 @llvm.AMDGPU.imul24(i32 %src0, i32 %src1) nounwind readnone
> + store i32 %mul, i32 addrspace(1)* %out, align 4
> + ret void
> +}
> +
> Index: test/CodeGen/R600/llvm.AMDGPU.umul24.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/llvm.AMDGPU.umul24.ll
> @@ -0,0 +1,11 @@
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
> +
> +declare i32 @llvm.AMDGPU.umul24(i32, i32) nounwind readnone
> +
> +; SI-LABEL: @test_umul24
> +define void @test_umul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
> + %mul = call i32 @llvm.AMDGPU.umul24(i32 %src0, i32 %src1) nounwind readnone
> + store i32 %mul, i32 addrspace(1)* %out, align 4
> + ret void
> +}
> +
> Index: lib/Target/R600/AMDGPUISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.cpp
> +++ lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -762,6 +762,14 @@
> return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
> Op.getOperand(2));
>
> + case AMDGPUIntrinsic::AMDGPU_imul24:
> + return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
> + Op.getOperand(1), Op.getOperand(2));
> +
> + case AMDGPUIntrinsic::AMDGPU_umul24:
> + return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
> + Op.getOperand(1), Op.getOperand(2));
> +
> case AMDGPUIntrinsic::AMDGPU_bfe_i32:
> return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
> Op.getOperand(1),
> Index: lib/Target/R600/AMDGPUIntrinsics.td
> ===================================================================
> --- lib/Target/R600/AMDGPUIntrinsics.td
> +++ lib/Target/R600/AMDGPUIntrinsics.td
> @@ -49,6 +49,8 @@
> def int_AMDGPU_imin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_imul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_umul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
> def int_AMDGPU_bfi : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_bfe_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> Index: lib/Target/R600/AMDILIntrinsics.td
> ===================================================================
> --- lib/Target/R600/AMDILIntrinsics.td
> +++ lib/Target/R600/AMDILIntrinsics.td
> @@ -92,10 +92,6 @@
> BinaryIntInt;
> def int_AMDIL_mulhi_u32 : GCCBuiltin<"__amdil_umul_high">,
> BinaryIntInt;
> - def int_AMDIL_mul24_i32 : GCCBuiltin<"__amdil_imul24">,
> - BinaryIntInt;
> - def int_AMDIL_mul24_u32 : GCCBuiltin<"__amdil_umul24">,
> - BinaryIntInt;
> def int_AMDIL_mulhi24_i32 : GCCBuiltin<"__amdil_imul24_high">,
> BinaryIntInt;
> def int_AMDIL_mulhi24_u32 : GCCBuiltin<"__amdil_umul24_high">,
> Index: test/CodeGen/R600/llvm.AMDGPU.imul24.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/llvm.AMDGPU.imul24.ll
> @@ -0,0 +1,14 @@
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> +; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
> +
> +declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone
> +
> +; FUNC-LABEL: @test_imul24
> +; SI: V_MUL_I32_I24
> +; CM: MUL_INT24
> +define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
> + %mul = call i32 @llvm.AMDGPU.imul24(i32 %src0, i32 %src1) nounwind readnone
> + store i32 %mul, i32 addrspace(1)* %out, align 4
> + ret void
> +}
> +
> Index: test/CodeGen/R600/llvm.AMDGPU.umul24.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/llvm.AMDGPU.umul24.ll
> @@ -0,0 +1,11 @@
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
> +
> +declare i32 @llvm.AMDGPU.umul24(i32, i32) nounwind readnone
> +
> +; SI-LABEL: @test_umul24
> +define void @test_umul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
> + %mul = call i32 @llvm.AMDGPU.umul24(i32 %src0, i32 %src1) nounwind readnone
> + store i32 %mul, i32 addrspace(1)* %out, align 4
> + ret void
> +}
> +
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