[llvm] r208580 - [ARM64-BE] Correct grammar mistake pointed out by Tobias.

[James Molloy]

Author: jamesm
Date: Mon May 12 10:30:31 2014
New Revision: 208580

URL: http://llvm.org/viewvc/llvm-project?rev=208580&view=rev
Log:
[ARM64-BE] Correct grammar mistake pointed out by Tobias.

Modified:
    llvm/trunk/docs/BigEndianNEON.rst

Modified: llvm/trunk/docs/BigEndianNEON.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/BigEndianNEON.rst?rev=208580&r1=208579&r2=208580&view=diff
==============================================================================
--- llvm/trunk/docs/BigEndianNEON.rst (original)
+++ llvm/trunk/docs/BigEndianNEON.rst Mon May 12 10:30:31 2014
@@ -90,7 +90,7 @@ Considerations
 LLVM IR Lane ordering
 ---------------------
 
-LLVM IR has first class vector types. In LLVM IR, the zero'th element of a vector resides at the lowest memory address. The optimizer relies on this property in certain areas, for example when concatenating vectors together. The intention is for arrays and vectors to have identical memory layouts - ``[4 x i8]`` and ``<4 x i8>`` should be represented the same in memory. Without this property there would be many special cases that the optimizer would have the cleverly handle.
+LLVM IR has first class vector types. In LLVM IR, the zero'th element of a vector resides at the lowest memory address. The optimizer relies on this property in certain areas, for example when concatenating vectors together. The intention is for arrays and vectors to have identical memory layouts - ``[4 x i8]`` and ``<4 x i8>`` should be represented the same in memory. Without this property there would be many special cases that the optimizer would have to cleverly handle.
 
 Use of ``LDR`` would break this lane ordering property. This doesn't preclude the use of ``LDR``, but we would have to do one of two things: