[PATCH] [ARM64] Recognize conditional incremental when there is ZEXT after SETCC in DAG

[Weiming Zhao]

This patch fixes bug http://llvm.org/bugs/show_bug.cgi?id=19680

http://reviews.llvm.org/D3655

Files:
  lib/Target/ARM64/ARM64ISelLowering.cpp
  test/CodeGen/ARM64/csel.ll

Index: lib/Target/ARM64/ARM64ISelLowering.cpp
===================================================================
--- lib/Target/ARM64/ARM64ISelLowering.cpp
+++ lib/Target/ARM64/ARM64ISelLowering.cpp
@@ -6505,7 +6505,7 @@
 }
 
 // The folding we want to perform is:
-// (add x, (setcc cc ...) )
+// (add x, [zext] (setcc cc ...) )
 //   -->
 // (csel x, (add x, 1), !cc ...)
 //
@@ -6519,8 +6519,16 @@
   // If neither operand is a SET_CC, give up.
   if (!isSetCC(LHS, InfoAndKind)) {
     std::swap(LHS, RHS);
-    if (!isSetCC(LHS, InfoAndKind))
-      return SDValue();
+    if (!isSetCC(LHS, InfoAndKind)) {
+      // Further check if there is a ZEXT of SET_CC.
+      if (!(LHS.getOpcode() == ISD::ZERO_EXTEND &&
+            isSetCC(LHS->getOperand(0), InfoAndKind))) {
+        std::swap(LHS, RHS);
+        if (!(LHS.getOpcode() == ISD::ZERO_EXTEND &&
+              isSetCC(LHS->getOperand(0), InfoAndKind)))
+          return SDValue();
+      }
+    }
   }
 
   // FIXME: This could be generatized to work for FP comparisons.
Index: test/CodeGen/ARM64/csel.ll
===================================================================
--- test/CodeGen/ARM64/csel.ll
+++ test/CodeGen/ARM64/csel.ll
@@ -220,3 +220,14 @@
   %. = select i1 %cmp, i64 1, i64 2
   ret i64 %.
 }
+
+define i64 @foo19(i64 %a, i64 %b, i64 %c) {
+entry:
+; CHECK-LABEL: foo19:
+; CHECK: csinc x0, x2, x2
+; CHECK-NOT: add
+  %cmp = icmp ult i64 %a, %b
+  %inc = zext i1 %cmp to i64
+  %inc.c = add i64 %inc, %c
+  ret i64 %inc.c
+}
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