[llvm] r208410 - [mips] Remove unused CondMov feature bit
Daniel Sanders
daniel.sanders at imgtec.com
Fri May 9 06:15:07 PDT 2014
Author: dsanders
Date: Fri May 9 08:15:07 2014
New Revision: 208410
URL: http://llvm.org/viewvc/llvm-project?rev=208410&view=rev
Log:
[mips] Remove unused CondMov feature bit
Summary:
No functional change
Depends on D3675
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3676
Modified:
llvm/trunk/lib/Target/Mips/Mips.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=208410&r1=208409&r2=208410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Fri May 9 08:15:07 2014
@@ -77,8 +77,6 @@ def FeatureVFPU : SubtargetFeatur
"true", "Enable vector FPU instructions.">;
def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
"Enable 'signext in register' instructions.">;
-def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
- "Enable 'conditional move' instructions.">;
def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
"Enable 'byte/half swap' instructions.">;
def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
@@ -99,14 +97,14 @@ def FeatureMips3 : SubtargetFeatur
FeatureGP64Bit, FeatureFP64Bit]>;
def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
"Mips4", "MIPS IV ISA Support",
- [FeatureMips3, FeatureFPIdx, FeatureCondMov]>;
+ [FeatureMips3, FeatureFPIdx]>;
def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
"MIPS V ISA Support [highly experimental]",
[FeatureMips4]>;
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
"Mips32 ISA Support",
[FeatureMips2, FeatureMips3_32,
- FeatureCondMov, FeatureBitCount]>;
+ FeatureBitCount]>;
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
"Mips32r2", "Mips32r2 ISA Support",
[FeatureMips32, FeatureSEInReg, FeatureSwap,
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=208410&r1=208409&r2=208410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri May 9 08:15:07 2014
@@ -152,8 +152,6 @@ def HasBitCount : Predicate<"Subtarg
AssemblerPredicate<"FeatureBitCount">;
def HasSwap : Predicate<"Subtarget.hasSwap()">,
AssemblerPredicate<"FeatureSwap">;
-def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
- AssemblerPredicate<"FeatureCondMov">;
def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
AssemblerPredicate<"FeatureFPIdx">;
def HasMips2 : Predicate<"Subtarget.hasMips2()">,
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=208410&r1=208409&r2=208410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri May 9 08:15:07 2014
@@ -81,11 +81,11 @@ MipsSubtarget::MipsSubtarget(const std::
MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
HasCnMips(false), IsLinux(true), HasMips3_32(false), HasSEInReg(false),
- HasCondMov(false), HasSwap(false), HasBitCount(false), HasFPIdx(false),
- InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
- InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
- AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
- RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) {
+ HasSwap(false), HasBitCount(false), HasFPIdx(false), InMips16Mode(false),
+ InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
+ HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
+ HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM),
+ TargetTriple(TT) {
std::string CPUName = CPU;
CPUName = selectMipsCPU(TT, CPUName);
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=208410&r1=208409&r2=208410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri May 9 08:15:07 2014
@@ -85,9 +85,6 @@ protected:
// HasSEInReg - SEB and SEH (signext in register) instructions.
bool HasSEInReg;
- // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
- bool HasCondMov;
-
// HasSwap - Byte and half swap instructions.
bool HasSwap;
@@ -213,7 +210,6 @@ public:
/// Features related to the presence of specific instructions.
bool hasSEInReg() const { return HasSEInReg; }
- bool hasCondMov() const { return HasCondMov; }
bool hasSwap() const { return HasSwap; }
bool hasBitCount() const { return HasBitCount; }
bool hasFPIdx() const { return HasFPIdx; }
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