[llvm] r208351 - Make a CodeGen test more robust against vector register selection

[Justin Bogner]

Quentin Colombet <qcolombet at apple.com> writes:
> Hi Justin,
>
> I think you have relaxed the test too much.
>
> On May 8, 2014, at 11:53 AM, Justin Bogner <mail at justinbogner.com> wrote:
>
>> Author: bogner
>> Date: Thu May  8 13:53:56 2014
>> New Revision: 208351
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=208351&view=rev> Log:
>> Make a CodeGen test more robust against vector register selection
>> 
>> Modified:
>>    llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll
>> 
>> Modified: llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll?rev=208351&r1=208350&r2=208351&view=diff> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/func-argpassing-endian.ll Thu May 8
>> 13:53:56 2014
>> @@ -22,11 +22,11 @@ define void @arg_double( double %val ) {
>> 
>> define void @arg_v4i32(<4 x i32> %vec ) {
>> ; CHECK-LABEL: arg_v4i32:
>> -; CHECK-LE: vmov d17, r2, r3
>> -; CHECK-LE: vmov d16, r0, r1
>> -; CHECK-BE: vmov d17, r3, r2
>> -; CHECK-BE: vmov d16, r1, r0
>> -; CHECK: vst1.32 {d16[0]}, [r0:32]
>> +; CHECK-LE: vmov {{d[0-9]+}}, r2, r3
>> +; CHECK-LE: vmov {{d[0-9]+}}, r0, r1
>> +; CHECK-BE: vmov {{d[0-9]+}}, r3, r2
>> +; CHECK-BE: vmov {{d[0-9]+}}, r1, r0
>> +; CHECK: vst1.32 {{{d[0-9]+}}[0]}, [r0:32]
> We do not actually check now that the store is fed with the value we
> just created.

Good point. I've tightened this up in r208368.

>>     %tmp = extractelement <4 x i32> %vec, i32 0
>>     store i32 %tmp, i32* @var32
>>     ret void
>> @@ -51,26 +51,26 @@ define i64 @return_longint() {
>> 
>> define double @return_double() {
>> ; CHECK-LABEL: return_double:
>> -; CHECK-LE: vmov r0, r1, d16
>> -; CHECK-BE: vmov r1, r0, d16
>> +; CHECK-LE: vmov r0, r1, {{d[0-9]+}}
>> +; CHECK-BE: vmov r1, r0, {{d[0-9]+}}
> Isn't this register defined by the ABI? (I’m asking, I do not know.)

Nope, these are regular callee saved registers. Thanks for checking.

>>     ret double 1.0
>> }
>> 
>> define <4 x i32> @return_v4i32() {
>> ; CHECK-LABEL: return_v4i32:
>> -; CHECK-LE: vmov r0, r1, d16
>> -; CHECK-LE: vmov r2, r3, d17
>> -; CHECK-BE: vmov r1, r0, d16
>> -; CHECK-BE: vmov r3, r2, d17
>> +; CHECK-LE: vmov r0, r1, {{d[0-9]+}}
>> +; CHECK-LE: vmov r2, r3, {{d[0-9]+}}
>> +; CHECK-BE: vmov r1, r0, {{d[0-9]+}}
>> +; CHECK-BE: vmov r3, r2, {{d[0-9]+}}
> ABI registers?
>>    ret < 4 x i32> < i32 42, i32 43, i32 44, i32 45 >
>> }
>> 
>> define <2 x double> @return_v2f64() {
>> ; CHECK-LABEL: return_v2f64:
>> -; CHECK-LE: vmov r0, r1, d16
>> -; CHECK-LE: vmov r2, r3, d17
>> -; CHECK-BE: vmov r1, r0, d16
>> -; CHECK-BE: vmov r3, r2, d17
>> +; CHECK-LE: vmov r0, r1, {{d[0-9]+}}
>> +; CHECK-LE: vmov r2, r3, {{d[0-9]+}}
>> +; CHECK-BE: vmov r1, r0, {{d[0-9]+}}
>> +; CHECK-BE: vmov r3, r2, {{d[0-9]+}}
> Ditto?
>>    ret <2 x double> < double 3.14, double 6.28 >
>> }
>> 
>> @@ -86,8 +86,8 @@ define void @caller_arg_longint() {
>> 
>> define void @caller_arg_double() {
>> ; CHECK-LABEL: caller_arg_double:
>> -; CHECK-LE: vmov r0, r1, d16
>> -; CHECK-BE: vmov r1, r0, d16
>> +; CHECK-LE: vmov r0, r1, {{d[0-9]+}}
>> +; CHECK-BE: vmov r1, r0, {{d[0-9]+}}
> Ditto?
>>    call void @arg_double( double 1.0 )
>>    ret void
>> }
>> @@ -104,8 +104,8 @@ define void @caller_return_longint() {
>> 
>> define void @caller_return_double() {
>> ; CHECK-LABEL: caller_return_double:
>> -; CHECK-LE: vmov d17, r0, r1
>> -; CHECK-BE: vmov d17, r1, r0
>> +; CHECK-LE: vmov {{d[0-9]+}}, r0, r1
>> +; CHECK-BE: vmov {{d[0-9]+}}, r1, r0
> Ditto?
>>   %val = call double @return_double( )
>>   %tmp = fadd double %val, 3.14
>>   store double  %tmp, double* @vardouble
>> @@ -120,4 +120,3 @@ define void @caller_return_v2f64() {
>>     store double %tmp, double* @vardouble
>>     ret void
>> }
>> -
>> 
>> 
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