[llvm] r208301 - [mips] Implement tlbp, tlbr, tlbwi, and tlbwr
Daniel Sanders
daniel.sanders at imgtec.com
Thu May 8 04:51:20 PDT 2014
Author: dsanders
Date: Thu May 8 06:51:18 2014
New Revision: 208301
URL: http://llvm.org/viewvc/llvm-project?rev=208301&view=rev
Log:
[mips] Implement tlbp, tlbr, tlbwi, and tlbwr
Reviewers: vmedic, dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D3571
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/mips1/valid-xfail.s
llvm/trunk/test/MC/Mips/mips1/valid.s
llvm/trunk/test/MC/Mips/mips2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips2/valid.s
llvm/trunk/test/MC/Mips/mips3/valid-xfail.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips32/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips4/valid-xfail.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid-xfail.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Thu May 8 06:51:18 2014
@@ -843,3 +843,12 @@ class BARRIER_FM<bits<5> op> : StdArch {
let Inst{10-6} = op; // Operation
let Inst{5-0} = 0; // SLL
}
+
+class COP0_TLB_FM<bits<6> op> : StdArch {
+ bits<32> Inst;
+
+ let Inst{31-26} = 0x10; // COP0
+ let Inst{25} = 1; // CO
+ let Inst{24-6} = 0;
+ let Inst{5-0} = op; // Operation
+}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu May 8 06:51:18 2014
@@ -1207,6 +1207,13 @@ def SSNOP : Barrier<"ssnop">, BARRIER_FM
def EHB : Barrier<"ehb">, BARRIER_FM<3>;
def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
+class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
+ FrmOther>;
+def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
+def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
+def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
+def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
+
//===----------------------------------------------------------------------===//
// Instruction aliases
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Mips/mips1/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid-xfail.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid-xfail.s Thu May 8 06:51:18 2014
@@ -7,10 +7,6 @@
# XFAIL: *
.set noat
- tlbp
- tlbr
- tlbwi
- tlbwr
lwc0 c0_entrylo,-7321($s2)
lwc3 $10,-32265($k0)
swc0 c0_prid,18904($s3)
Modified: llvm/trunk/test/MC/Mips/mips1/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid.s Thu May 8 06:51:18 2014
@@ -92,4 +92,8 @@
swc2 $25,24880($s0)
swl $t7,13694($s3)
swr $s1,-26590($t6)
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
xor $s2,$a0,$s8
Modified: llvm/trunk/test/MC/Mips/mips2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid-xfail.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid-xfail.s Thu May 8 06:51:18 2014
@@ -10,7 +10,3 @@
ldc3 $29,-28645($s1)
lwc3 $10,-32265($k0)
sdc3 $12,5835($t2)
- tlbp
- tlbr
- tlbwi
- tlbwr
Modified: llvm/trunk/test/MC/Mips/mips2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid.s Thu May 8 06:51:18 2014
@@ -109,6 +109,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647
Modified: llvm/trunk/test/MC/Mips/mips3/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid-xfail.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid-xfail.s Thu May 8 06:51:18 2014
@@ -8,7 +8,3 @@
.set noat
lwc3 $10,-32265($k0)
- tlbp
- tlbr
- tlbwi
- tlbwr
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Thu May 8 06:51:18 2014
@@ -159,6 +159,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647
Modified: llvm/trunk/test/MC/Mips/mips32/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid-xfail.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid-xfail.s Thu May 8 06:51:18 2014
@@ -38,7 +38,3 @@
ldc3 $29,-28645($s1)
rorv $t5,$a3,$s5
sdc3 $12,5835($t2)
- tlbp
- tlbr
- tlbwi
- tlbwr
Modified: llvm/trunk/test/MC/Mips/mips32/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid.s Thu May 8 06:51:18 2014
@@ -134,6 +134,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s Thu May 8 06:51:18 2014
@@ -304,10 +304,6 @@
tlbgwr
tlbinv
tlbinvf
- tlbp
- tlbr
- tlbwi
- tlbwr
trunc.l.d $f23,$f23
trunc.l.s $f28,$f31
wrpgpr $zero,$t5
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Thu May 8 06:51:18 2014
@@ -161,6 +161,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647
Modified: llvm/trunk/test/MC/Mips/mips4/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid-xfail.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid-xfail.s Thu May 8 06:51:18 2014
@@ -47,7 +47,3 @@
recip.s $f3,$f30
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
- tlbp
- tlbr
- tlbwi
- tlbwr
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Thu May 8 06:51:18 2014
@@ -177,6 +177,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647
Modified: llvm/trunk/test/MC/Mips/mips5/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid-xfail.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid-xfail.s Thu May 8 06:51:18 2014
@@ -85,7 +85,3 @@
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sub.ps $f5,$f14,$f26
- tlbp
- tlbr
- tlbwi
- tlbwr
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Thu May 8 06:51:18 2014
@@ -177,6 +177,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647
Modified: llvm/trunk/test/MC/Mips/mips64/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid-xfail.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid-xfail.s Thu May 8 06:51:18 2014
@@ -92,7 +92,3 @@
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sub.ps $f5,$f14,$f26
- tlbp
- tlbr
- tlbwi
- tlbwr
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Thu May 8 06:51:18 2014
@@ -191,6 +191,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s Thu May 8 06:51:18 2014
@@ -306,10 +306,6 @@
tlbgwr
tlbinv
tlbinvf
- tlbp
- tlbr
- tlbwi
- tlbwr
wrpgpr $zero,$t5
xor.v $w20,$w21,$w30
yield $v1,$s0
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=208301&r1=208300&r2=208301&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Thu May 8 06:51:18 2014
@@ -213,6 +213,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647
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