[llvm] r208273 - ARM: support FK_SecRel_2 relocations on WoA

[Saleem Abdulrasool]

Author: compnerd
Date: Wed May  7 20:35:57 2014
New Revision: 208273

URL: http://llvm.org/viewvc/llvm-project?rev=208273&view=rev
Log:
ARM: support FK_SecRel_2 relocations on WoA

This adds FK_SecRel_2 relocation support to ARM.  This enables the building of
object files for armv7-windows-msvc which enables CodeView line tables for
debugging as opposed to armv7-windows-itanium which currently uses DWARF.

Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
    llvm/trunk/test/MC/ARM/coff-debugging-secrel.ll

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=208273&r1=208272&r2=208273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed May  7 20:35:57 2014
@@ -344,6 +344,8 @@ static unsigned adjustFixupValue(const M
   case FK_Data_2:
   case FK_Data_4:
     return Value;
+  case FK_SecRel_2:
+    return Value;
   case FK_SecRel_4:
     return Value;
   case ARM::fixup_arm_movt_hi16:
@@ -674,6 +676,8 @@ static unsigned getFixupKindNumBytes(uns
   case ARM::fixup_t2_movw_lo16:
     return 4;
 
+  case FK_SecRel_2:
+    return 2;
   case FK_SecRel_4:
     return 4;
   }

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp?rev=208273&r1=208272&r2=208273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp Wed May  7 20:35:57 2014
@@ -49,6 +49,8 @@ unsigned ARMWinCOFFObjectWriter::getRelo
     default:
       return COFF::IMAGE_REL_ARM_ADDR32;
     }
+  case FK_SecRel_2:
+    return COFF::IMAGE_REL_ARM_SECTION;
   case FK_SecRel_4:
     return COFF::IMAGE_REL_ARM_SECREL;
   case ARM::fixup_t2_condbranch:

Modified: llvm/trunk/test/MC/ARM/coff-debugging-secrel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/coff-debugging-secrel.ll?rev=208273&r1=208272&r2=208273&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/coff-debugging-secrel.ll (original)
+++ llvm/trunk/test/MC/ARM/coff-debugging-secrel.ll Wed May  7 20:35:57 2014
@@ -1,5 +1,8 @@
 ; RUN: llc -mtriple thumbv7--windows-itanium -filetype obj -o - %s \
-; RUN:     | llvm-readobj -r - | FileCheck %s
+; RUN:     | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-ITANIUM
+
+; RUN: llc -mtriple thumbv7--windows-msvc -filetype obj -o - %s \
+; RUN:    | llvm-readobj -r - | Filecheck %s -check-prefix CHECK-MSVC
 
 ; ModuleID = '/Users/compnerd/work/llvm/test/MC/ARM/reduced.c'
 target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
@@ -25,17 +28,24 @@ entry:
 !9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}
 !10 = metadata !{i32 1, metadata !"Debug Info Version", i32 1}
 
-; CHECK: Relocations [
-; CHECK:   Section {{.*}} .debug_info {
-; CHECK:     0x6 IMAGE_REL_ARM_SECREL .debug_abbrev
-; CHECK:     0xC IMAGE_REL_ARM_SECREL .debug_str
-; CHECK:     0x12 IMAGE_REL_ARM_SECREL .debug_str
-; CHECK:     0x16 IMAGE_REL_ARM_SECREL .debug_line
-; CHECK:     0x1A IMAGE_REL_ARM_SECREL .debug_str
-; CHECK:     0x27 IMAGE_REL_ARM_SECREL .debug_str
-; CHECK:   }
-; CHECK:   Section {{.*}}.debug_pubnames {
-; CHECK:     0x6 IMAGE_REL_ARM_SECREL .debug_info
-; CHECK:   }
-; CHECK: ]
+; CHECK-ITANIUM: Relocations [
+; CHECK-ITANIUM:   Section {{.*}} .debug_info {
+; CHECK-ITANIUM:     0x6 IMAGE_REL_ARM_SECREL .debug_abbrev
+; CHECK-ITANIUM:     0xC IMAGE_REL_ARM_SECREL .debug_str
+; CHECK-ITANIUM:     0x12 IMAGE_REL_ARM_SECREL .debug_str
+; CHECK-ITANIUM:     0x16 IMAGE_REL_ARM_SECREL .debug_line
+; CHECK-ITANIUM:     0x1A IMAGE_REL_ARM_SECREL .debug_str
+; CHECK-ITANIUM:     0x27 IMAGE_REL_ARM_SECREL .debug_str
+; CHECK-ITANIUM:   }
+; CHECK-ITANIUM:   Section {{.*}}.debug_pubnames {
+; CHECK-ITANIUM:     0x6 IMAGE_REL_ARM_SECREL .debug_info
+; CHECK-ITANIUM:   }
+; CHECK-ITANIUM: ]
+
+; CHECK-MSVC: Relocations [
+; CHECK-MSVC:   Section {{.*}} .debug$S {
+; CHECK-MSVC:     0xC IMAGE_REL_ARM_SECREL function
+; CHECK-MSVC:     0x10 IMAGE_REL_ARM_SECTION function
+; CHECK-MSVC:   }
+; CHECK-MSVC: ]