[llvm] r207917 - [ARM64] Correctly select ANDWri in FastISel.

[Eric Christopher]

These could probably use a comment as to why we need to constrain here
in these locations.

-eric

On Sat, May 3, 2014 at 10:27 AM, Joey Gouly <joey.gouly at gmail.com> wrote:
> Author: joey
> Date: Sat May  3 12:27:06 2014
> New Revision: 207917
>
> URL: http://llvm.org/viewvc/llvm-project?rev=207917&view=rev
> Log:
> [ARM64] Correctly select ANDWri in FastISel.
>
> http://reviews.llvm.org/D3598
>
> Modified:
>     llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp
>     llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll
>
> Modified: llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp?rev=207917&r1=207916&r2=207917&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp Sat May  3 12:27:06 2014
> @@ -577,7 +577,8 @@ bool ARM64FastISel::EmitLoad(MVT VT, uns
>
>    // Loading an i1 requires special handling.
>    if (VTIsi1) {
> -    unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
> +    MRI.constrainRegClass(ResultReg, &ARM64::GPR32RegClass);
> +    unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
>      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
>              ANDReg)
>          .addReg(ResultReg)
> @@ -665,7 +666,8 @@ bool ARM64FastISel::EmitStore(MVT VT, un
>
>    // Storing an i1 requires special handling.
>    if (VTIsi1) {
> -    unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
> +    MRI.constrainRegClass(SrcReg, &ARM64::GPR32RegClass);
> +    unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
>      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
>              ANDReg)
>          .addReg(SrcReg)
> @@ -788,7 +790,8 @@ bool ARM64FastISel::SelectBranch(const I
>          CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true,
>                                               ARM64::sub_32);
>
> -      unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
> +      MRI.constrainRegClass(CondReg, &ARM64::GPR32RegClass);
> +      unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
>        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
>                ANDReg)
>            .addReg(CondReg)
> @@ -1030,7 +1033,9 @@ bool ARM64FastISel::SelectSelect(const I
>    if (FalseReg == 0)
>      return false;
>
> -  unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
> +
> +  MRI.constrainRegClass(CondReg, &ARM64::GPR32RegClass);
> +  unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
>    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
>            ANDReg)
>        .addReg(CondReg)
> @@ -1669,8 +1674,9 @@ bool ARM64FastISel::SelectTrunc(const In
>      // Issue an extract_subreg to get the lower 32-bits.
>      unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true,
>                                                  ARM64::sub_32);
> +    MRI.constrainRegClass(Reg32, &ARM64::GPR32RegClass);
>      // Create the AND instruction which performs the actual truncation.
> -    unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
> +    unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
>      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
>              ANDReg)
>          .addReg(Reg32)
> @@ -1691,7 +1697,8 @@ unsigned ARM64FastISel::Emiti1Ext(unsign
>      DestVT = MVT::i32;
>
>    if (isZExt) {
> -    unsigned ResultReg = createResultReg(&ARM64::GPR32RegClass);
> +    MRI.constrainRegClass(SrcReg, &ARM64::GPR32RegClass);
> +    unsigned ResultReg = createResultReg(&ARM64::GPR32spRegClass);
>      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
>              ResultReg)
>          .addReg(SrcReg)
>
> Modified: llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll?rev=207917&r1=207916&r2=207917&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll Sat May  3 12:27:06 2014
> @@ -1,4 +1,4 @@
> -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
> +; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin | FileCheck %s
>
>  define zeroext i1 @fcmp_float1(float %a) nounwind ssp {
>  entry:
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits