[PATCH] [ARM64] Select ANDWri correctly in FastISel

[Joey Gouly]

Hi grosbach, t.p.northover,

Pretty mechanical patch to fix the selection of ANDWri.

I didn't add new tests because the all the code I touched is currently exercised by the tests. I just can't add -verify-machineinstrs everywhere just yet. Should I add specific tests for the cases? I'm working towards adding -verify-machineinstrs to more tests, so they should be guarded soon.

http://reviews.llvm.org/D3598

Files:
  lib/Target/ARM64/ARM64FastISel.cpp
  test/CodeGen/ARM64/fast-isel-fcmp.ll

Index: lib/Target/ARM64/ARM64FastISel.cpp
===================================================================
--- lib/Target/ARM64/ARM64FastISel.cpp
+++ lib/Target/ARM64/ARM64FastISel.cpp
@@ -577,7 +577,8 @@
 
   // Loading an i1 requires special handling.
   if (VTIsi1) {
-    unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
+    MRI.constrainRegClass(ResultReg, &ARM64::GPR32RegClass);
+    unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
             ANDReg)
         .addReg(ResultReg)
@@ -665,7 +666,8 @@
 
   // Storing an i1 requires special handling.
   if (VTIsi1) {
-    unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
+    MRI.constrainRegClass(SrcReg, &ARM64::GPR32RegClass);
+    unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
             ANDReg)
         .addReg(SrcReg)
@@ -788,7 +790,8 @@
         CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true,
                                              ARM64::sub_32);
 
-      unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
+      MRI.constrainRegClass(CondReg, &ARM64::GPR32RegClass);
+      unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
               ANDReg)
           .addReg(CondReg)
@@ -1030,7 +1033,9 @@
   if (FalseReg == 0)
     return false;
 
-  unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
+
+  MRI.constrainRegClass(CondReg, &ARM64::GPR32RegClass);
+  unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
           ANDReg)
       .addReg(CondReg)
@@ -1669,8 +1674,9 @@
     // Issue an extract_subreg to get the lower 32-bits.
     unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true,
                                                 ARM64::sub_32);
+    MRI.constrainRegClass(Reg32, &ARM64::GPR32RegClass);
     // Create the AND instruction which performs the actual truncation.
-    unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
+    unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
             ANDReg)
         .addReg(Reg32)
@@ -1691,7 +1697,8 @@
     DestVT = MVT::i32;
 
   if (isZExt) {
-    unsigned ResultReg = createResultReg(&ARM64::GPR32RegClass);
+    MRI.constrainRegClass(SrcReg, &ARM64::GPR32RegClass);
+    unsigned ResultReg = createResultReg(&ARM64::GPR32spRegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
             ResultReg)
         .addReg(SrcReg)
Index: test/CodeGen/ARM64/fast-isel-fcmp.ll
===================================================================
--- test/CodeGen/ARM64/fast-isel-fcmp.ll
+++ test/CodeGen/ARM64/fast-isel-fcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
+; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin | FileCheck %s
 
 define zeroext i1 @fcmp_float1(float %a) nounwind ssp {
 entry:
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