[PATCH] [InstCombine] Combine adjacent i8 loads.

[hfinkel at anl.gov]

I'll point out that on PPC we have byte-swapped loads, and we currently handle this in CodeGen using a target-specific DAG combine. We recognize a LOAD+BSWAP and BSWAP+STORE pair and produce a target-specific node for the desired instruction. This does not, however, handle the case where the the loads are combinable. However, we already have an optimization in DAGCombine that is supposed to combine consecutive loads, DAGCombiner::CombineConsecutiveLoads (maybe it requires AA to be active in DAGCombine to work optimally, but I normally turn that on for PPC, and I think that it should be safe in general). Perhaps it just needs to be called in the right place to work for this input?

> Doing this at the IR level has the benefit that our memory analysis (BasicAA) is better in the current framework. Inlining can cause us to loose information about aliasing (lost noalias parameters, we should really fix this :), Hal had a patch but I digress ...).

Yes, I'll be getting back to this quite soon.

http://reviews.llvm.org/D3580