[PATCH] R600: Expand TruncStore i64 -> {i16,i8}
Matt Arsenault
Matthew.Arsenault at amd.com
Thu May 1 17:07:46 PDT 2014
On 05/02/2014 12:23 AM, Tom Stellard wrote:
> ---
> lib/Target/R600/AMDGPUISelLowering.cpp | 2 ++
> test/CodeGen/R600/store.ll | 40 ++++++++++++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
> diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
> index 52a500c..8adf7a9 100644
> --- a/lib/Target/R600/AMDGPUISelLowering.cpp
> +++ b/lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -145,6 +145,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
> // handle 64-bit stores.
> setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
>
> + setTruncStoreAction(MVT::i64, MVT::i16, Expand);
> + setTruncStoreAction(MVT::i64, MVT::i8, Expand);
> setTruncStoreAction(MVT::i64, MVT::i1, Expand);
> setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
> setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
> diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll
> index b29ad7e..c0c8ccc 100644
> --- a/test/CodeGen/R600/store.ll
> +++ b/test/CodeGen/R600/store.ll
> @@ -177,6 +177,26 @@ entry:
> ret void
> }
>
> +; FUNC-LABEL: @store_i64_i8
> +; EG-CHECK: MEM_RAT MSKOR
> +; SI-CHECK: BUFFER_STORE_BYTE
> +define void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) {
> +entry:
> + %0 = trunc i64 %in to i8
> + store i8 %0, i8 addrspace(1)* %out
> + ret void
> +}
> +
> +; FUNC-LABEL: @store_i64_i16
> +; EG-CHECK: MEM_RAT MSKOR
> +; SI-CHECK: BUFFER_STORE_SHORT
> +define void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) {
> +entry:
> + %0 = trunc i64 %in to i16
> + store i16 %0, i16 addrspace(1)* %out
> + ret void
> +}
> +
> ;===------------------------------------------------------------------------===;
> ; Local Address Space
> ;===------------------------------------------------------------------------===;
> @@ -272,6 +292,26 @@ entry:
> ret void
> }
>
> +; FUNC-LABEL: @store_local_i64_i8
> +; EG-CHECK: LDS_BYTE_WRITE
> +; SI-CHECK: DS_WRITE_B8
> +define void @store_local_i64_i8(i8 addrspace(3)* %out, i64 %in) {
> +entry:
> + %0 = trunc i64 %in to i8
> + store i8 %0, i8 addrspace(3)* %out
> + ret void
> +}
> +
> +; FUNC-LABEL: @store_local_i64_i16
> +; EG-CHECK: LDS_SHORT_WRITE
> +; SI-CHECK: DS_WRITE_B16
> +define void @store_local_i64_i16(i16 addrspace(3)* %out, i64 %in) {
> +entry:
> + %0 = trunc i64 %in to i16
> + store i16 %0, i16 addrspace(3)* %out
> + ret void
> +}
> +
> ; The stores in this function are combined by the optimizer to create a
> ; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
> ; should not try to split the 64-bit store back into 2 32-bit stores.
LGTM
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