[llvm] r207753 - AArch64/ARM64: port basic disassembly tests to ARM64.
Tim Northover
tnorthover at apple.com
Thu May 1 05:29:57 PDT 2014
Author: tnorthover
Date: Thu May 1 07:29:56 2014
New Revision: 207753
URL: http://llvm.org/viewvc/llvm-project?rev=207753&view=rev
Log:
AArch64/ARM64: port basic disassembly tests to ARM64.
Modified:
llvm/trunk/test/MC/Disassembler/AArch64/a64-ignored-fields.txt
llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt
llvm/trunk/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt
llvm/trunk/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt
llvm/trunk/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt
llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt
llvm/trunk/test/MC/Disassembler/AArch64/trace-regs.txt
Modified: llvm/trunk/test/MC/Disassembler/AArch64/a64-ignored-fields.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/a64-ignored-fields.txt?rev=207753&r1=207752&r2=207753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/a64-ignored-fields.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/a64-ignored-fields.txt Thu May 1 07:29:56 2014
@@ -1,4 +1,5 @@
# RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=arm64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s
# The "Rm" bits are ignored, but the canonical representation has them filled
# with 0s. This is what we should produce even if the input bit-pattern had
Modified: llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt?rev=207753&r1=207752&r2=207753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt Thu May 1 07:29:56 2014
@@ -1,4 +1,5 @@
# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
#------------------------------------------------------------------------------
# Add/sub (immediate)
@@ -187,7 +188,7 @@
# CHECK: sub w3, w5, w7
# CHECK: sub wzr, w3, w5
-# CHECK: sub w20, wzr, w4
+# CHECK: {{sub w20, wzr, w4|neg w20, w4}}
# CHECK: sub w4, w6, wzr
# CHECK: sub w11, w13, w15
# CHECK: sub w9, w3, wzr, lsl #10
@@ -214,7 +215,7 @@
# CHECK: sub x3, x5, x7
# CHECK: sub xzr, x3, x5
-# CHECK: sub x20, xzr, x4
+# CHECK: {{sub x20, xzr, x4|neg x20, x4}}
# CHECK: sub x4, x6, xzr
# CHECK: sub x11, x13, x15
# CHECK: sub x9, x3, xzr, lsl #10
@@ -241,7 +242,7 @@
# CHECK: subs w3, w5, w7
# CHECK: cmp w3, w5
-# CHECK: subs w20, wzr, w4
+# CHECK: {{subs w20, wzr, w4|negs w20, w4}}
# CHECK: subs w4, w6, wzr
# CHECK: subs w11, w13, w15
# CHECK: subs w9, w3, wzr, lsl #10
@@ -268,7 +269,7 @@
# CHECK: subs x3, x5, x7
# CHECK: cmp x3, x5
-# CHECK: subs x20, xzr, x4
+# CHECK: {{subs x20, xzr, x4|negs x20, x4}}
# CHECK: subs x4, x6, xzr
# CHECK: subs x11, x13, x15
# CHECK: subs x9, x3, xzr, lsl #10
@@ -393,18 +394,18 @@
0x9f 0xde 0x95 0xeb
0xdf 0xfe 0x97 0xeb
-# CHECK: sub w29, wzr, w30
-# CHECK: sub w30, wzr, wzr
-# CHECK: sub wzr, wzr, w0
-# CHECK: sub w28, wzr, w27
-# CHECK: sub w26, wzr, w25, lsl #29
-# CHECK: sub w24, wzr, w23, lsl #31
-# CHECK: sub w22, wzr, w21, lsr #0
-# CHECK: sub w20, wzr, w19, lsr #1
-# CHECK: sub w18, wzr, w17, lsr #31
-# CHECK: sub w16, wzr, w15, asr #0
-# CHECK: sub w14, wzr, w13, asr #12
-# CHECK: sub w12, wzr, w11, asr #31
+# CHECK: {{sub w29, wzr|neg w29}}, w30
+# CHECK: {{sub w30, wzr|neg w30}}, wzr
+# CHECK: {{sub wzr, wzr|neg wzr}}, w0
+# CHECK: {{sub w28, wzr|neg w28}}, w27
+# CHECK: {{sub w26, wzr|neg w26}}, w25, lsl #29
+# CHECK: {{sub w24, wzr|neg w24}}, w23, lsl #31
+# CHECK: {{sub w22, wzr|neg w22}}, w21, lsr #0
+# CHECK: {{sub w20, wzr|neg w20}}, w19, lsr #1
+# CHECK: {{sub w18, wzr|neg w18}}, w17, lsr #31
+# CHECK: {{sub w16, wzr|neg w16}}, w15, asr #0
+# CHECK: {{sub w14, wzr|neg w14}}, w13, asr #12
+# CHECK: {{sub w12, wzr|neg w12}}, w11, asr #31
0xfd 0x3 0x1e 0x4b
0xfe 0x3 0x1f 0x4b
0xff 0x3 0x0 0x4b
@@ -418,18 +419,18 @@
0xee 0x33 0x8d 0x4b
0xec 0x7f 0x8b 0x4b
-# CHECK: sub x29, xzr, x30
-# CHECK: sub x30, xzr, xzr
-# CHECK: sub xzr, xzr, x0
-# CHECK: sub x28, xzr, x27
-# CHECK: sub x26, xzr, x25, lsl #29
-# CHECK: sub x24, xzr, x23, lsl #31
-# CHECK: sub x22, xzr, x21, lsr #0
-# CHECK: sub x20, xzr, x19, lsr #1
-# CHECK: sub x18, xzr, x17, lsr #31
-# CHECK: sub x16, xzr, x15, asr #0
-# CHECK: sub x14, xzr, x13, asr #12
-# CHECK: sub x12, xzr, x11, asr #31
+# CHECK: {{sub x29, xzr|neg x29}}, x30
+# CHECK: {{sub x30, xzr|neg x30}}, xzr
+# CHECK: {{sub xzr, xzr|neg xzr}}, x0
+# CHECK: {{sub x28, xzr|neg x28}}, x27
+# CHECK: {{sub x26, xzr|neg x26}}, x25, lsl #29
+# CHECK: {{sub x24, xzr|neg x24}}, x23, lsl #31
+# CHECK: {{sub x22, xzr|neg x22}}, x21, lsr #0
+# CHECK: {{sub x20, xzr|neg x20}}, x19, lsr #1
+# CHECK: {{sub x18, xzr|neg x18}}, x17, lsr #31
+# CHECK: {{sub x16, xzr|neg x16}}, x15, asr #0
+# CHECK: {{sub x14, xzr|neg x14}}, x13, asr #12
+# CHECK: {{sub x12, xzr|neg x12}}, x11, asr #31
0xfd 0x3 0x1e 0xcb
0xfe 0x3 0x1f 0xcb
0xff 0x3 0x0 0xcb
@@ -443,18 +444,18 @@
0xee 0x33 0x8d 0xcb
0xec 0x7f 0x8b 0xcb
-# CHECK: subs w29, wzr, w30
-# CHECK: subs w30, wzr, wzr
+# CHECK: {{subs w29, wzr|negs w29}}, w30
+# CHECK: {{subs w30, wzr|negs w30}}, wzr
# CHECK: cmp wzr, w0
-# CHECK: subs w28, wzr, w27
-# CHECK: subs w26, wzr, w25, lsl #29
-# CHECK: subs w24, wzr, w23, lsl #31
-# CHECK: subs w22, wzr, w21, lsr #0
-# CHECK: subs w20, wzr, w19, lsr #1
-# CHECK: subs w18, wzr, w17, lsr #31
-# CHECK: subs w16, wzr, w15, asr #0
-# CHECK: subs w14, wzr, w13, asr #12
-# CHECK: subs w12, wzr, w11, asr #31
+# CHECK: {{subs w28, wzr|negs w28}}, w27
+# CHECK: {{subs w26, wzr|negs w26}}, w25, lsl #29
+# CHECK: {{subs w24, wzr|negs w24}}, w23, lsl #31
+# CHECK: {{subs w22, wzr|negs w22}}, w21, lsr #0
+# CHECK: {{subs w20, wzr|negs w20}}, w19, lsr #1
+# CHECK: {{subs w18, wzr|negs w18}}, w17, lsr #31
+# CHECK: {{subs w16, wzr|negs w16}}, w15, asr #0
+# CHECK: {{subs w14, wzr|negs w14}}, w13, asr #12
+# CHECK: {{subs w12, wzr|negs w12}}, w11, asr #31
0xfd 0x3 0x1e 0x6b
0xfe 0x3 0x1f 0x6b
0xff 0x3 0x0 0x6b
@@ -468,18 +469,18 @@
0xee 0x33 0x8d 0x6b
0xec 0x7f 0x8b 0x6b
-# CHECK: subs x29, xzr, x30
-# CHECK: subs x30, xzr, xzr
+# CHECK: {{subs x29, xzr|negs x29}}, x30
+# CHECK: {{subs x30, xzr|negs x30}}, xzr
# CHECK: cmp xzr, x0
-# CHECK: subs x28, xzr, x27
-# CHECK: subs x26, xzr, x25, lsl #29
-# CHECK: subs x24, xzr, x23, lsl #31
-# CHECK: subs x22, xzr, x21, lsr #0
-# CHECK: subs x20, xzr, x19, lsr #1
-# CHECK: subs x18, xzr, x17, lsr #31
-# CHECK: subs x16, xzr, x15, asr #0
-# CHECK: subs x14, xzr, x13, asr #12
-# CHECK: subs x12, xzr, x11, asr #31
+# CHECK: {{subs x28, xzr|negs x28}}, x27
+# CHECK: {{subs x26, xzr|negs x26}}, x25, lsl #29
+# CHECK: {{subs x24, xzr|negs x24}}, x23, lsl #31
+# CHECK: {{subs x22, xzr|negs x22}}, x21, lsr #0
+# CHECK: {{subs x20, xzr|negs x20}}, x19, lsr #1
+# CHECK: {{subs x18, xzr|negs x18}}, x17, lsr #31
+# CHECK: {{subs x16, xzr|negs x16}}, x15, asr #0
+# CHECK: {{subs x14, xzr|negs x14}}, x13, asr #12
+# CHECK: {{subs x12, xzr|negs x12}}, x11, asr #31
0xfd 0x3 0x1e 0xeb
0xfe 0x3 0x1f 0xeb
0xff 0x3 0x0 0xeb
@@ -1243,22 +1244,22 @@
#------------------------------------------------------------------------------
# CHECK: svc #0
-# CHECK: svc #65535
+# CHECK: svc #{{65535|0xffff}}
0x1 0x0 0x0 0xd4
0xe1 0xff 0x1f 0xd4
-# CHECK: hvc #1
-# CHECK: smc #12000
-# CHECK: brk #12
-# CHECK: hlt #123
+# CHECK: hvc #{{1|0x1}}
+# CHECK: smc #{{12000|0x2ee0}}
+# CHECK: brk #{{12|0xc}}
+# CHECK: hlt #{{123|0x7b}}
0x22 0x0 0x0 0xd4
0x3 0xdc 0x5 0xd4
0x80 0x1 0x20 0xd4
0x60 0xf 0x40 0xd4
-# CHECK: dcps1 #42
-# CHECK: dcps2 #9
-# CHECK: dcps3 #1000
+# CHECK: dcps1 #{{42|0x2a}}
+# CHECK: dcps2 #{{9|0x9}}
+# CHECK: dcps3 #{{1000|0x3e8}}
0x41 0x5 0xa0 0xd4
0x22 0x1 0xa0 0xd4
0x3 0x7d 0xa0 0xd4
@@ -2353,23 +2354,23 @@
0xec 0xff 0xbf 0x3d
# CHECK: prfm pldl1keep, [sp, #8]
-# CHECK: prfm pldl1strm, [x3, #0]
+# CHECK: prfm pldl1strm, [x3{{(, #0)?}}]
# CHECK: prfm pldl2keep, [x5, #16]
-# CHECK: prfm pldl2strm, [x2, #0]
-# CHECK: prfm pldl3keep, [x5, #0]
-# CHECK: prfm pldl3strm, [x6, #0]
+# CHECK: prfm pldl2strm, [x2{{(, #0)?}}]
+# CHECK: prfm pldl3keep, [x5{{(, #0)?}}]
+# CHECK: prfm pldl3strm, [x6{{(, #0)?}}]
# CHECK: prfm plil1keep, [sp, #8]
-# CHECK: prfm plil1strm, [x3, #0]
+# CHECK: prfm plil1strm, [x3{{(, #0)?}}]
# CHECK: prfm plil2keep, [x5, #16]
-# CHECK: prfm plil2strm, [x2, #0]
-# CHECK: prfm plil3keep, [x5, #0]
-# CHECK: prfm plil3strm, [x6, #0]
+# CHECK: prfm plil2strm, [x2{{(, #0)?}}]
+# CHECK: prfm plil3keep, [x5{{(, #0)?}}]
+# CHECK: prfm plil3strm, [x6{{(, #0)?}}]
# CHECK: prfm pstl1keep, [sp, #8]
-# CHECK: prfm pstl1strm, [x3, #0]
+# CHECK: prfm pstl1strm, [x3{{(, #0)?}}]
# CHECK: prfm pstl2keep, [x5, #16]
-# CHECK: prfm pstl2strm, [x2, #0]
-# CHECK: prfm pstl3keep, [x5, #0]
-# CHECK: prfm pstl3strm, [x6, #0]
+# CHECK: prfm pstl2strm, [x2{{(, #0)?}}]
+# CHECK: prfm pstl3keep, [x5{{(, #0)?}}]
+# CHECK: prfm pstl3strm, [x6{{(, #0)?}}]
0xe0 0x07 0x80 0xf9
0x61 0x00 0x80 0xf9
0xa2 0x08 0x80 0xf9
@@ -2722,15 +2723,15 @@
0xff 0xc7 0x0 0x52
0x30 0xc6 0x1 0x52
-# CHECK: ands wzr, w18, #0xcccccccc
+# CHECK: {{ands wzr,|tst}} w18, #0xcccccccc
# CHECK: ands w19, w20, #0x33333333
# CHECK: ands w21, w22, #0x99999999
0x5f 0xe6 0x2 0x72
0x93 0xe6 0x0 0x72
0xd5 0xe6 0x1 0x72
-# CHECK: ands wzr, w3, #0xaaaaaaaa
-# CHECK: ands wzr, wzr, #0x55555555
+# CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa
+# CHECK: {{ands wzr,|tst}} wzr, #0x55555555
0x7f 0xf0 0x1 0x72
0xff 0xf3 0x0 0x72
@@ -2762,15 +2763,15 @@
0xff 0xc7 0x0 0xd2
0x30 0xc6 0x1 0xd2
-# CHECK: ands xzr, x18, #0xcccccccccccccccc
+# CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc
# CHECK: ands x19, x20, #0x3333333333333333
# CHECK: ands x21, x22, #0x9999999999999999
0x5f 0xe6 0x2 0xf2
0x93 0xe6 0x0 0xf2
0xd5 0xe6 0x1 0xf2
-# CHECK: ands xzr, x3, #0xaaaaaaaaaaaaaaaa
-# CHECK: ands xzr, xzr, #0x5555555555555555
+# CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa
+# CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555
0x7f 0xf0 0x1 0xf2
0xff 0xf3 0x0 0xf2
@@ -2858,15 +2859,15 @@
# limitation in InstAlias. Lots of the "mov[nz]" instructions should
# be "mov".
-# CHECK: movz w1, #65535
+# CHECK: movz w1, #{{65535|0xffff}}
# CHECK: movz w2, #0, lsl #16
-# CHECK: movn w2, #1234
+# CHECK: movn w2, #{{1234|0x4d2}}
0xe1 0xff 0x9f 0x52
0x2 0x0 0xa0 0x52
0x42 0x9a 0x80 0x12
-# CHECK: movz x2, #1234, lsl #32
-# CHECK: movk xzr, #4321, lsl #48
+# CHECK: movz x2, #{{1234|0x4d2}}, lsl #32
+# CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48
0x42 0x9a 0xc0 0xd2
0x3f 0x1c 0xe2 0xf2
@@ -2906,7 +2907,7 @@
#------------------------------------------------------------------------------
# CHECK: nop
-# CHECK: hint #127
+# CHECK: hint #{{127|0x7f}}
# CHECK: nop
# CHECK: yield
# CHECK: wfe
@@ -2998,9 +2999,9 @@
0xdf 0x3f 0x3 0xd5
0xdf 0x3c 0x3 0xd5
-# CHECK: msr spsel, #0
-# CHECK: msr daifset, #15
-# CHECK: msr daifclr, #12
+# CHECK: msr {{spsel|SPSEL}}, #0
+# CHECK: msr {{daifset|DAIFSET}}, #15
+# CHECK: msr {{daifclr|DAIFCLR}}, #12
0xbf 0x40 0x0 0xd5
0xdf 0x4f 0x3 0xd5
0xff 0x4c 0x3 0xd5
@@ -3014,21 +3015,21 @@
0xe9 0x59 0x2f 0xd5
0x41 0xff 0x28 0xd5
-# CHECK: sys #0, c7, c1, #0, xzr
-# CHECK: sys #0, c7, c5, #0, xzr
-# CHECK: sys #3, c7, c5, #1, x9
+# CHECK: {{sys #0, c7, c1, #0, xzr|ic ialluis}}
+# CHECK: {{sys #0, c7, c5, #0, xzr|ic iallu}}
+# CHECK: {{sys #3, c7, c5, #1|ic ivau}}, x9
0x1f 0x71 0x8 0xd5
0x1f 0x75 0x8 0xd5
0x29 0x75 0xb 0xd5
-# CHECK: sys #3, c7, c4, #1, x12
-# CHECK: sys #0, c7, c6, #1, xzr
-# CHECK: sys #0, c7, c6, #2, x2
-# CHECK: sys #3, c7, c10, #1, x9
-# CHECK: sys #0, c7, c10, #2, x10
-# CHECK: sys #3, c7, c11, #1, x0
-# CHECK: sys #3, c7, c14, #1, x3
-# CHECK: sys #0, c7, c14, #2, x30
+# CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12
+# CHECK: {{sys #0, c7, c6, #1|dc ivac}}, xzr
+# CHECK: {{sys #0, c7, c6, #2|dc isw}}, x2
+# CHECK: {{sys #3, c7, c10, #1|dc cvac}}, x9
+# CHECK: {{sys #0, c7, c10, #2|dc csw}}, x10
+# CHECK: {{sys #3, c7, c11, #1|dc cvau}}, x0
+# CHECK: {{sys #3, c7, c14, #1|dc civac}}, x3
+# CHECK: {{sys #0, c7, c14, #2|dc cisw}}, x30
0x2c 0x74 0xb 0xd5
0x3f 0x76 0x8 0xd5
0x42 0x76 0x8 0xd5
@@ -3039,559 +3040,559 @@
0x5e 0x7e 0x8 0xd5
-# CHECK: msr teecr32_el1, x12
-# CHECK: msr osdtrrx_el1, x12
-# CHECK: msr mdccint_el1, x12
-# CHECK: msr mdscr_el1, x12
-# CHECK: msr osdtrtx_el1, x12
-# CHECK: msr dbgdtr_el0, x12
-# CHECK: msr dbgdtrtx_el0, x12
-# CHECK: msr oseccr_el1, x12
-# CHECK: msr dbgvcr32_el2, x12
-# CHECK: msr dbgbvr0_el1, x12
-# CHECK: msr dbgbvr1_el1, x12
-# CHECK: msr dbgbvr2_el1, x12
-# CHECK: msr dbgbvr3_el1, x12
-# CHECK: msr dbgbvr4_el1, x12
-# CHECK: msr dbgbvr5_el1, x12
-# CHECK: msr dbgbvr6_el1, x12
-# CHECK: msr dbgbvr7_el1, x12
-# CHECK: msr dbgbvr8_el1, x12
-# CHECK: msr dbgbvr9_el1, x12
-# CHECK: msr dbgbvr10_el1, x12
-# CHECK: msr dbgbvr11_el1, x12
-# CHECK: msr dbgbvr12_el1, x12
-# CHECK: msr dbgbvr13_el1, x12
-# CHECK: msr dbgbvr14_el1, x12
-# CHECK: msr dbgbvr15_el1, x12
-# CHECK: msr dbgbcr0_el1, x12
-# CHECK: msr dbgbcr1_el1, x12
-# CHECK: msr dbgbcr2_el1, x12
-# CHECK: msr dbgbcr3_el1, x12
-# CHECK: msr dbgbcr4_el1, x12
-# CHECK: msr dbgbcr5_el1, x12
-# CHECK: msr dbgbcr6_el1, x12
-# CHECK: msr dbgbcr7_el1, x12
-# CHECK: msr dbgbcr8_el1, x12
-# CHECK: msr dbgbcr9_el1, x12
-# CHECK: msr dbgbcr10_el1, x12
-# CHECK: msr dbgbcr11_el1, x12
-# CHECK: msr dbgbcr12_el1, x12
-# CHECK: msr dbgbcr13_el1, x12
-# CHECK: msr dbgbcr14_el1, x12
-# CHECK: msr dbgbcr15_el1, x12
-# CHECK: msr dbgwvr0_el1, x12
-# CHECK: msr dbgwvr1_el1, x12
-# CHECK: msr dbgwvr2_el1, x12
-# CHECK: msr dbgwvr3_el1, x12
-# CHECK: msr dbgwvr4_el1, x12
-# CHECK: msr dbgwvr5_el1, x12
-# CHECK: msr dbgwvr6_el1, x12
-# CHECK: msr dbgwvr7_el1, x12
-# CHECK: msr dbgwvr8_el1, x12
-# CHECK: msr dbgwvr9_el1, x12
-# CHECK: msr dbgwvr10_el1, x12
-# CHECK: msr dbgwvr11_el1, x12
-# CHECK: msr dbgwvr12_el1, x12
-# CHECK: msr dbgwvr13_el1, x12
-# CHECK: msr dbgwvr14_el1, x12
-# CHECK: msr dbgwvr15_el1, x12
-# CHECK: msr dbgwcr0_el1, x12
-# CHECK: msr dbgwcr1_el1, x12
-# CHECK: msr dbgwcr2_el1, x12
-# CHECK: msr dbgwcr3_el1, x12
-# CHECK: msr dbgwcr4_el1, x12
-# CHECK: msr dbgwcr5_el1, x12
-# CHECK: msr dbgwcr6_el1, x12
-# CHECK: msr dbgwcr7_el1, x12
-# CHECK: msr dbgwcr8_el1, x12
-# CHECK: msr dbgwcr9_el1, x12
-# CHECK: msr dbgwcr10_el1, x12
-# CHECK: msr dbgwcr11_el1, x12
-# CHECK: msr dbgwcr12_el1, x12
-# CHECK: msr dbgwcr13_el1, x12
-# CHECK: msr dbgwcr14_el1, x12
-# CHECK: msr dbgwcr15_el1, x12
-# CHECK: msr teehbr32_el1, x12
-# CHECK: msr oslar_el1, x12
-# CHECK: msr osdlr_el1, x12
-# CHECK: msr dbgprcr_el1, x12
-# CHECK: msr dbgclaimset_el1, x12
-# CHECK: msr dbgclaimclr_el1, x12
-# CHECK: msr csselr_el1, x12
-# CHECK: msr vpidr_el2, x12
-# CHECK: msr vmpidr_el2, x12
-# CHECK: msr sctlr_el1, x12
-# CHECK: msr sctlr_el2, x12
-# CHECK: msr sctlr_el3, x12
-# CHECK: msr actlr_el1, x12
-# CHECK: msr actlr_el2, x12
-# CHECK: msr actlr_el3, x12
-# CHECK: msr cpacr_el1, x12
-# CHECK: msr hcr_el2, x12
-# CHECK: msr scr_el3, x12
-# CHECK: msr mdcr_el2, x12
-# CHECK: msr sder32_el3, x12
-# CHECK: msr cptr_el2, x12
-# CHECK: msr cptr_el3, x12
-# CHECK: msr hstr_el2, x12
-# CHECK: msr hacr_el2, x12
-# CHECK: msr mdcr_el3, x12
-# CHECK: msr ttbr0_el1, x12
-# CHECK: msr ttbr0_el2, x12
-# CHECK: msr ttbr0_el3, x12
-# CHECK: msr ttbr1_el1, x12
-# CHECK: msr tcr_el1, x12
-# CHECK: msr tcr_el2, x12
-# CHECK: msr tcr_el3, x12
-# CHECK: msr vttbr_el2, x12
-# CHECK: msr vtcr_el2, x12
-# CHECK: msr dacr32_el2, x12
-# CHECK: msr spsr_el1, x12
-# CHECK: msr spsr_el2, x12
-# CHECK: msr spsr_el3, x12
-# CHECK: msr elr_el1, x12
-# CHECK: msr elr_el2, x12
-# CHECK: msr elr_el3, x12
-# CHECK: msr sp_el0, x12
-# CHECK: msr sp_el1, x12
-# CHECK: msr sp_el2, x12
-# CHECK: msr spsel, x12
-# CHECK: msr nzcv, x12
-# CHECK: msr daif, x12
-# CHECK: msr currentel, x12
-# CHECK: msr spsr_irq, x12
-# CHECK: msr spsr_abt, x12
-# CHECK: msr spsr_und, x12
-# CHECK: msr spsr_fiq, x12
-# CHECK: msr fpcr, x12
-# CHECK: msr fpsr, x12
-# CHECK: msr dspsr_el0, x12
-# CHECK: msr dlr_el0, x12
-# CHECK: msr ifsr32_el2, x12
-# CHECK: msr afsr0_el1, x12
-# CHECK: msr afsr0_el2, x12
-# CHECK: msr afsr0_el3, x12
-# CHECK: msr afsr1_el1, x12
-# CHECK: msr afsr1_el2, x12
-# CHECK: msr afsr1_el3, x12
-# CHECK: msr esr_el1, x12
-# CHECK: msr esr_el2, x12
-# CHECK: msr esr_el3, x12
-# CHECK: msr fpexc32_el2, x12
-# CHECK: msr far_el1, x12
-# CHECK: msr far_el2, x12
-# CHECK: msr far_el3, x12
-# CHECK: msr hpfar_el2, x12
-# CHECK: msr par_el1, x12
-# CHECK: msr pmcr_el0, x12
-# CHECK: msr pmcntenset_el0, x12
-# CHECK: msr pmcntenclr_el0, x12
-# CHECK: msr pmovsclr_el0, x12
-# CHECK: msr pmselr_el0, x12
-# CHECK: msr pmccntr_el0, x12
-# CHECK: msr pmxevtyper_el0, x12
-# CHECK: msr pmxevcntr_el0, x12
-# CHECK: msr pmuserenr_el0, x12
-# CHECK: msr pmintenset_el1, x12
-# CHECK: msr pmintenclr_el1, x12
-# CHECK: msr pmovsset_el0, x12
-# CHECK: msr mair_el1, x12
-# CHECK: msr mair_el2, x12
-# CHECK: msr mair_el3, x12
-# CHECK: msr amair_el1, x12
-# CHECK: msr amair_el2, x12
-# CHECK: msr amair_el3, x12
-# CHECK: msr vbar_el1, x12
-# CHECK: msr vbar_el2, x12
-# CHECK: msr vbar_el3, x12
-# CHECK: msr rmr_el1, x12
-# CHECK: msr rmr_el2, x12
-# CHECK: msr rmr_el3, x12
-# CHECK: msr tpidr_el0, x12
-# CHECK: msr tpidr_el2, x12
-# CHECK: msr tpidr_el3, x12
-# CHECK: msr tpidrro_el0, x12
-# CHECK: msr tpidr_el1, x12
-# CHECK: msr cntfrq_el0, x12
-# CHECK: msr cntvoff_el2, x12
-# CHECK: msr cntkctl_el1, x12
-# CHECK: msr cnthctl_el2, x12
-# CHECK: msr cntp_tval_el0, x12
-# CHECK: msr cnthp_tval_el2, x12
-# CHECK: msr cntps_tval_el1, x12
-# CHECK: msr cntp_ctl_el0, x12
-# CHECK: msr cnthp_ctl_el2, x12
-# CHECK: msr cntps_ctl_el1, x12
-# CHECK: msr cntp_cval_el0, x12
-# CHECK: msr cnthp_cval_el2, x12
-# CHECK: msr cntps_cval_el1, x12
-# CHECK: msr cntv_tval_el0, x12
-# CHECK: msr cntv_ctl_el0, x12
-# CHECK: msr cntv_cval_el0, x12
-# CHECK: msr pmevcntr0_el0, x12
-# CHECK: msr pmevcntr1_el0, x12
-# CHECK: msr pmevcntr2_el0, x12
-# CHECK: msr pmevcntr3_el0, x12
-# CHECK: msr pmevcntr4_el0, x12
-# CHECK: msr pmevcntr5_el0, x12
-# CHECK: msr pmevcntr6_el0, x12
-# CHECK: msr pmevcntr7_el0, x12
-# CHECK: msr pmevcntr8_el0, x12
-# CHECK: msr pmevcntr9_el0, x12
-# CHECK: msr pmevcntr10_el0, x12
-# CHECK: msr pmevcntr11_el0, x12
-# CHECK: msr pmevcntr12_el0, x12
-# CHECK: msr pmevcntr13_el0, x12
-# CHECK: msr pmevcntr14_el0, x12
-# CHECK: msr pmevcntr15_el0, x12
-# CHECK: msr pmevcntr16_el0, x12
-# CHECK: msr pmevcntr17_el0, x12
-# CHECK: msr pmevcntr18_el0, x12
-# CHECK: msr pmevcntr19_el0, x12
-# CHECK: msr pmevcntr20_el0, x12
-# CHECK: msr pmevcntr21_el0, x12
-# CHECK: msr pmevcntr22_el0, x12
-# CHECK: msr pmevcntr23_el0, x12
-# CHECK: msr pmevcntr24_el0, x12
-# CHECK: msr pmevcntr25_el0, x12
-# CHECK: msr pmevcntr26_el0, x12
-# CHECK: msr pmevcntr27_el0, x12
-# CHECK: msr pmevcntr28_el0, x12
-# CHECK: msr pmevcntr29_el0, x12
-# CHECK: msr pmevcntr30_el0, x12
-# CHECK: msr pmccfiltr_el0, x12
-# CHECK: msr pmevtyper0_el0, x12
-# CHECK: msr pmevtyper1_el0, x12
-# CHECK: msr pmevtyper2_el0, x12
-# CHECK: msr pmevtyper3_el0, x12
-# CHECK: msr pmevtyper4_el0, x12
-# CHECK: msr pmevtyper5_el0, x12
-# CHECK: msr pmevtyper6_el0, x12
-# CHECK: msr pmevtyper7_el0, x12
-# CHECK: msr pmevtyper8_el0, x12
-# CHECK: msr pmevtyper9_el0, x12
-# CHECK: msr pmevtyper10_el0, x12
-# CHECK: msr pmevtyper11_el0, x12
-# CHECK: msr pmevtyper12_el0, x12
-# CHECK: msr pmevtyper13_el0, x12
-# CHECK: msr pmevtyper14_el0, x12
-# CHECK: msr pmevtyper15_el0, x12
-# CHECK: msr pmevtyper16_el0, x12
-# CHECK: msr pmevtyper17_el0, x12
-# CHECK: msr pmevtyper18_el0, x12
-# CHECK: msr pmevtyper19_el0, x12
-# CHECK: msr pmevtyper20_el0, x12
-# CHECK: msr pmevtyper21_el0, x12
-# CHECK: msr pmevtyper22_el0, x12
-# CHECK: msr pmevtyper23_el0, x12
-# CHECK: msr pmevtyper24_el0, x12
-# CHECK: msr pmevtyper25_el0, x12
-# CHECK: msr pmevtyper26_el0, x12
-# CHECK: msr pmevtyper27_el0, x12
-# CHECK: msr pmevtyper28_el0, x12
-# CHECK: msr pmevtyper29_el0, x12
-# CHECK: msr pmevtyper30_el0, x12
-# CHECK: mrs x9, teecr32_el1
-# CHECK: mrs x9, osdtrrx_el1
-# CHECK: mrs x9, mdccsr_el0
-# CHECK: mrs x9, mdccint_el1
-# CHECK: mrs x9, mdscr_el1
-# CHECK: mrs x9, osdtrtx_el1
-# CHECK: mrs x9, dbgdtr_el0
-# CHECK: mrs x9, dbgdtrrx_el0
-# CHECK: mrs x9, oseccr_el1
-# CHECK: mrs x9, dbgvcr32_el2
-# CHECK: mrs x9, dbgbvr0_el1
-# CHECK: mrs x9, dbgbvr1_el1
-# CHECK: mrs x9, dbgbvr2_el1
-# CHECK: mrs x9, dbgbvr3_el1
-# CHECK: mrs x9, dbgbvr4_el1
-# CHECK: mrs x9, dbgbvr5_el1
-# CHECK: mrs x9, dbgbvr6_el1
-# CHECK: mrs x9, dbgbvr7_el1
-# CHECK: mrs x9, dbgbvr8_el1
-# CHECK: mrs x9, dbgbvr9_el1
-# CHECK: mrs x9, dbgbvr10_el1
-# CHECK: mrs x9, dbgbvr11_el1
-# CHECK: mrs x9, dbgbvr12_el1
-# CHECK: mrs x9, dbgbvr13_el1
-# CHECK: mrs x9, dbgbvr14_el1
-# CHECK: mrs x9, dbgbvr15_el1
-# CHECK: mrs x9, dbgbcr0_el1
-# CHECK: mrs x9, dbgbcr1_el1
-# CHECK: mrs x9, dbgbcr2_el1
-# CHECK: mrs x9, dbgbcr3_el1
-# CHECK: mrs x9, dbgbcr4_el1
-# CHECK: mrs x9, dbgbcr5_el1
-# CHECK: mrs x9, dbgbcr6_el1
-# CHECK: mrs x9, dbgbcr7_el1
-# CHECK: mrs x9, dbgbcr8_el1
-# CHECK: mrs x9, dbgbcr9_el1
-# CHECK: mrs x9, dbgbcr10_el1
-# CHECK: mrs x9, dbgbcr11_el1
-# CHECK: mrs x9, dbgbcr12_el1
-# CHECK: mrs x9, dbgbcr13_el1
-# CHECK: mrs x9, dbgbcr14_el1
-# CHECK: mrs x9, dbgbcr15_el1
-# CHECK: mrs x9, dbgwvr0_el1
-# CHECK: mrs x9, dbgwvr1_el1
-# CHECK: mrs x9, dbgwvr2_el1
-# CHECK: mrs x9, dbgwvr3_el1
-# CHECK: mrs x9, dbgwvr4_el1
-# CHECK: mrs x9, dbgwvr5_el1
-# CHECK: mrs x9, dbgwvr6_el1
-# CHECK: mrs x9, dbgwvr7_el1
-# CHECK: mrs x9, dbgwvr8_el1
-# CHECK: mrs x9, dbgwvr9_el1
-# CHECK: mrs x9, dbgwvr10_el1
-# CHECK: mrs x9, dbgwvr11_el1
-# CHECK: mrs x9, dbgwvr12_el1
-# CHECK: mrs x9, dbgwvr13_el1
-# CHECK: mrs x9, dbgwvr14_el1
-# CHECK: mrs x9, dbgwvr15_el1
-# CHECK: mrs x9, dbgwcr0_el1
-# CHECK: mrs x9, dbgwcr1_el1
-# CHECK: mrs x9, dbgwcr2_el1
-# CHECK: mrs x9, dbgwcr3_el1
-# CHECK: mrs x9, dbgwcr4_el1
-# CHECK: mrs x9, dbgwcr5_el1
-# CHECK: mrs x9, dbgwcr6_el1
-# CHECK: mrs x9, dbgwcr7_el1
-# CHECK: mrs x9, dbgwcr8_el1
-# CHECK: mrs x9, dbgwcr9_el1
-# CHECK: mrs x9, dbgwcr10_el1
-# CHECK: mrs x9, dbgwcr11_el1
-# CHECK: mrs x9, dbgwcr12_el1
-# CHECK: mrs x9, dbgwcr13_el1
-# CHECK: mrs x9, dbgwcr14_el1
-# CHECK: mrs x9, dbgwcr15_el1
-# CHECK: mrs x9, mdrar_el1
-# CHECK: mrs x9, teehbr32_el1
-# CHECK: mrs x9, oslsr_el1
-# CHECK: mrs x9, osdlr_el1
-# CHECK: mrs x9, dbgprcr_el1
-# CHECK: mrs x9, dbgclaimset_el1
-# CHECK: mrs x9, dbgclaimclr_el1
-# CHECK: mrs x9, dbgauthstatus_el1
-# CHECK: mrs x9, midr_el1
-# CHECK: mrs x9, ccsidr_el1
-# CHECK: mrs x9, csselr_el1
-# CHECK: mrs x9, vpidr_el2
-# CHECK: mrs x9, clidr_el1
-# CHECK: mrs x9, ctr_el0
-# CHECK: mrs x9, mpidr_el1
-# CHECK: mrs x9, vmpidr_el2
-# CHECK: mrs x9, revidr_el1
-# CHECK: mrs x9, aidr_el1
-# CHECK: mrs x9, dczid_el0
-# CHECK: mrs x9, id_pfr0_el1
-# CHECK: mrs x9, id_pfr1_el1
-# CHECK: mrs x9, id_dfr0_el1
-# CHECK: mrs x9, id_afr0_el1
-# CHECK: mrs x9, id_mmfr0_el1
-# CHECK: mrs x9, id_mmfr1_el1
-# CHECK: mrs x9, id_mmfr2_el1
-# CHECK: mrs x9, id_mmfr3_el1
-# CHECK: mrs x9, id_isar0_el1
-# CHECK: mrs x9, id_isar1_el1
-# CHECK: mrs x9, id_isar2_el1
-# CHECK: mrs x9, id_isar3_el1
-# CHECK: mrs x9, id_isar4_el1
-# CHECK: mrs x9, id_isar5_el1
-# CHECK: mrs x9, mvfr0_el1
-# CHECK: mrs x9, mvfr1_el1
-# CHECK: mrs x9, mvfr2_el1
-# CHECK: mrs x9, id_aa64pfr0_el1
-# CHECK: mrs x9, id_aa64pfr1_el1
-# CHECK: mrs x9, id_aa64dfr0_el1
-# CHECK: mrs x9, id_aa64dfr1_el1
-# CHECK: mrs x9, id_aa64afr0_el1
-# CHECK: mrs x9, id_aa64afr1_el1
-# CHECK: mrs x9, id_aa64isar0_el1
-# CHECK: mrs x9, id_aa64isar1_el1
-# CHECK: mrs x9, id_aa64mmfr0_el1
-# CHECK: mrs x9, id_aa64mmfr1_el1
-# CHECK: mrs x9, sctlr_el1
-# CHECK: mrs x9, sctlr_el2
-# CHECK: mrs x9, sctlr_el3
-# CHECK: mrs x9, actlr_el1
-# CHECK: mrs x9, actlr_el2
-# CHECK: mrs x9, actlr_el3
-# CHECK: mrs x9, cpacr_el1
-# CHECK: mrs x9, hcr_el2
-# CHECK: mrs x9, scr_el3
-# CHECK: mrs x9, mdcr_el2
-# CHECK: mrs x9, sder32_el3
-# CHECK: mrs x9, cptr_el2
-# CHECK: mrs x9, cptr_el3
-# CHECK: mrs x9, hstr_el2
-# CHECK: mrs x9, hacr_el2
-# CHECK: mrs x9, mdcr_el3
-# CHECK: mrs x9, ttbr0_el1
-# CHECK: mrs x9, ttbr0_el2
-# CHECK: mrs x9, ttbr0_el3
-# CHECK: mrs x9, ttbr1_el1
-# CHECK: mrs x9, tcr_el1
-# CHECK: mrs x9, tcr_el2
-# CHECK: mrs x9, tcr_el3
-# CHECK: mrs x9, vttbr_el2
-# CHECK: mrs x9, vtcr_el2
-# CHECK: mrs x9, dacr32_el2
-# CHECK: mrs x9, spsr_el1
-# CHECK: mrs x9, spsr_el2
-# CHECK: mrs x9, spsr_el3
-# CHECK: mrs x9, elr_el1
-# CHECK: mrs x9, elr_el2
-# CHECK: mrs x9, elr_el3
-# CHECK: mrs x9, sp_el0
-# CHECK: mrs x9, sp_el1
-# CHECK: mrs x9, sp_el2
-# CHECK: mrs x9, spsel
-# CHECK: mrs x9, nzcv
-# CHECK: mrs x9, daif
-# CHECK: mrs x9, currentel
-# CHECK: mrs x9, spsr_irq
-# CHECK: mrs x9, spsr_abt
-# CHECK: mrs x9, spsr_und
-# CHECK: mrs x9, spsr_fiq
-# CHECK: mrs x9, fpcr
-# CHECK: mrs x9, fpsr
-# CHECK: mrs x9, dspsr_el0
-# CHECK: mrs x9, dlr_el0
-# CHECK: mrs x9, ifsr32_el2
-# CHECK: mrs x9, afsr0_el1
-# CHECK: mrs x9, afsr0_el2
-# CHECK: mrs x9, afsr0_el3
-# CHECK: mrs x9, afsr1_el1
-# CHECK: mrs x9, afsr1_el2
-# CHECK: mrs x9, afsr1_el3
-# CHECK: mrs x9, esr_el1
-# CHECK: mrs x9, esr_el2
-# CHECK: mrs x9, esr_el3
-# CHECK: mrs x9, fpexc32_el2
-# CHECK: mrs x9, far_el1
-# CHECK: mrs x9, far_el2
-# CHECK: mrs x9, far_el3
-# CHECK: mrs x9, hpfar_el2
-# CHECK: mrs x9, par_el1
-# CHECK: mrs x9, pmcr_el0
-# CHECK: mrs x9, pmcntenset_el0
-# CHECK: mrs x9, pmcntenclr_el0
-# CHECK: mrs x9, pmovsclr_el0
-# CHECK: mrs x9, pmselr_el0
-# CHECK: mrs x9, pmceid0_el0
-# CHECK: mrs x9, pmceid1_el0
-# CHECK: mrs x9, pmccntr_el0
-# CHECK: mrs x9, pmxevtyper_el0
-# CHECK: mrs x9, pmxevcntr_el0
-# CHECK: mrs x9, pmuserenr_el0
-# CHECK: mrs x9, pmintenset_el1
-# CHECK: mrs x9, pmintenclr_el1
-# CHECK: mrs x9, pmovsset_el0
-# CHECK: mrs x9, mair_el1
-# CHECK: mrs x9, mair_el2
-# CHECK: mrs x9, mair_el3
-# CHECK: mrs x9, amair_el1
-# CHECK: mrs x9, amair_el2
-# CHECK: mrs x9, amair_el3
-# CHECK: mrs x9, vbar_el1
-# CHECK: mrs x9, vbar_el2
-# CHECK: mrs x9, vbar_el3
-# CHECK: mrs x9, rvbar_el1
-# CHECK: mrs x9, rvbar_el2
-# CHECK: mrs x9, rvbar_el3
-# CHECK: mrs x9, rmr_el1
-# CHECK: mrs x9, rmr_el2
-# CHECK: mrs x9, rmr_el3
-# CHECK: mrs x9, isr_el1
-# CHECK: mrs x9, contextidr_el1
-# CHECK: mrs x9, tpidr_el0
-# CHECK: mrs x9, tpidr_el2
-# CHECK: mrs x9, tpidr_el3
-# CHECK: mrs x9, tpidrro_el0
-# CHECK: mrs x9, tpidr_el1
-# CHECK: mrs x9, cntfrq_el0
-# CHECK: mrs x9, cntpct_el0
-# CHECK: mrs x9, cntvct_el0
-# CHECK: mrs x9, cntvoff_el2
-# CHECK: mrs x9, cntkctl_el1
-# CHECK: mrs x9, cnthctl_el2
-# CHECK: mrs x9, cntp_tval_el0
-# CHECK: mrs x9, cnthp_tval_el2
-# CHECK: mrs x9, cntps_tval_el1
-# CHECK: mrs x9, cntp_ctl_el0
-# CHECK: mrs x9, cnthp_ctl_el2
-# CHECK: mrs x9, cntps_ctl_el1
-# CHECK: mrs x9, cntp_cval_el0
-# CHECK: mrs x9, cnthp_cval_el2
-# CHECK: mrs x9, cntps_cval_el1
-# CHECK: mrs x9, cntv_tval_el0
-# CHECK: mrs x9, cntv_ctl_el0
-# CHECK: mrs x9, cntv_cval_el0
-# CHECK: mrs x9, pmevcntr0_el0
-# CHECK: mrs x9, pmevcntr1_el0
-# CHECK: mrs x9, pmevcntr2_el0
-# CHECK: mrs x9, pmevcntr3_el0
-# CHECK: mrs x9, pmevcntr4_el0
-# CHECK: mrs x9, pmevcntr5_el0
-# CHECK: mrs x9, pmevcntr6_el0
-# CHECK: mrs x9, pmevcntr7_el0
-# CHECK: mrs x9, pmevcntr8_el0
-# CHECK: mrs x9, pmevcntr9_el0
-# CHECK: mrs x9, pmevcntr10_el0
-# CHECK: mrs x9, pmevcntr11_el0
-# CHECK: mrs x9, pmevcntr12_el0
-# CHECK: mrs x9, pmevcntr13_el0
-# CHECK: mrs x9, pmevcntr14_el0
-# CHECK: mrs x9, pmevcntr15_el0
-# CHECK: mrs x9, pmevcntr16_el0
-# CHECK: mrs x9, pmevcntr17_el0
-# CHECK: mrs x9, pmevcntr18_el0
-# CHECK: mrs x9, pmevcntr19_el0
-# CHECK: mrs x9, pmevcntr20_el0
-# CHECK: mrs x9, pmevcntr21_el0
-# CHECK: mrs x9, pmevcntr22_el0
-# CHECK: mrs x9, pmevcntr23_el0
-# CHECK: mrs x9, pmevcntr24_el0
-# CHECK: mrs x9, pmevcntr25_el0
-# CHECK: mrs x9, pmevcntr26_el0
-# CHECK: mrs x9, pmevcntr27_el0
-# CHECK: mrs x9, pmevcntr28_el0
-# CHECK: mrs x9, pmevcntr29_el0
-# CHECK: mrs x9, pmevcntr30_el0
-# CHECK: mrs x9, pmccfiltr_el0
-# CHECK: mrs x9, pmevtyper0_el0
-# CHECK: mrs x9, pmevtyper1_el0
-# CHECK: mrs x9, pmevtyper2_el0
-# CHECK: mrs x9, pmevtyper3_el0
-# CHECK: mrs x9, pmevtyper4_el0
-# CHECK: mrs x9, pmevtyper5_el0
-# CHECK: mrs x9, pmevtyper6_el0
-# CHECK: mrs x9, pmevtyper7_el0
-# CHECK: mrs x9, pmevtyper8_el0
-# CHECK: mrs x9, pmevtyper9_el0
-# CHECK: mrs x9, pmevtyper10_el0
-# CHECK: mrs x9, pmevtyper11_el0
-# CHECK: mrs x9, pmevtyper12_el0
-# CHECK: mrs x9, pmevtyper13_el0
-# CHECK: mrs x9, pmevtyper14_el0
-# CHECK: mrs x9, pmevtyper15_el0
-# CHECK: mrs x9, pmevtyper16_el0
-# CHECK: mrs x9, pmevtyper17_el0
-# CHECK: mrs x9, pmevtyper18_el0
-# CHECK: mrs x9, pmevtyper19_el0
-# CHECK: mrs x9, pmevtyper20_el0
-# CHECK: mrs x9, pmevtyper21_el0
-# CHECK: mrs x9, pmevtyper22_el0
-# CHECK: mrs x9, pmevtyper23_el0
-# CHECK: mrs x9, pmevtyper24_el0
-# CHECK: mrs x9, pmevtyper25_el0
-# CHECK: mrs x9, pmevtyper26_el0
-# CHECK: mrs x9, pmevtyper27_el0
-# CHECK: mrs x9, pmevtyper28_el0
-# CHECK: mrs x9, pmevtyper29_el0
-# CHECK: mrs x9, pmevtyper30_el0
+# CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12
+# CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12
+# CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12
+# CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12
+# CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12
+# CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12
+# CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12
+# CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12
+# CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12
+# CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12
+# CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12
+# CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12
+# CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12
+# CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12
+# CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12
+# CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12
+# CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12
+# CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12
+# CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12
+# CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12
+# CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12
+# CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12
+# CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12
+# CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12
+# CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12
+# CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12
+# CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12
+# CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12
+# CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12
+# CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12
+# CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12
+# CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12
+# CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12
+# CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12
+# CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12
+# CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12
+# CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12
+# CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12
+# CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12
+# CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12
+# CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12
+# CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12
+# CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12
+# CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12
+# CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12
+# CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12
+# CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12
+# CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12
+# CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12
+# CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12
+# CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12
+# CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12
+# CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12
+# CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12
+# CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12
+# CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12
+# CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12
+# CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12
+# CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12
+# CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12
+# CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12
+# CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12
+# CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12
+# CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12
+# CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12
+# CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12
+# CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12
+# CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12
+# CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12
+# CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12
+# CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12
+# CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12
+# CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12
+# CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12
+# CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12
+# CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12
+# CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12
+# CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12
+# CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12
+# CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12
+# CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12
+# CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12
+# CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12
+# CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12
+# CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12
+# CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12
+# CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12
+# CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12
+# CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12
+# CHECK: msr {{hcr_el2|HCR_EL2}}, x12
+# CHECK: msr {{scr_el3|SCR_EL3}}, x12
+# CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12
+# CHECK: msr {{sder32_el3|SDER32_EL3}}, x12
+# CHECK: msr {{cptr_el2|CPTR_EL2}}, x12
+# CHECK: msr {{cptr_el3|CPTR_EL3}}, x12
+# CHECK: msr {{hstr_el2|HSTR_EL2}}, x12
+# CHECK: msr {{hacr_el2|HACR_EL2}}, x12
+# CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12
+# CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12
+# CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12
+# CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12
+# CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12
+# CHECK: msr {{tcr_el1|TCR_EL1}}, x12
+# CHECK: msr {{tcr_el2|TCR_EL2}}, x12
+# CHECK: msr {{tcr_el3|TCR_EL3}}, x12
+# CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12
+# CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12
+# CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12
+# CHECK: msr {{spsr_el1|SPSR_EL1}}, x12
+# CHECK: msr {{spsr_el2|SPSR_EL2}}, x12
+# CHECK: msr {{spsr_el3|SPSR_EL3}}, x12
+# CHECK: msr {{elr_el1|ELR_EL1}}, x12
+# CHECK: msr {{elr_el2|ELR_EL2}}, x12
+# CHECK: msr {{elr_el3|ELR_EL3}}, x12
+# CHECK: msr {{sp_el0|SP_EL0}}, x12
+# CHECK: msr {{sp_el1|SP_EL1}}, x12
+# CHECK: msr {{sp_el2|SP_EL2}}, x12
+# CHECK: msr {{spsel|SPSEL}}, x12
+# CHECK: msr {{nzcv|NZCV}}, x12
+# CHECK: msr {{daif|DAIF}}, x12
+# CHECK: msr {{currentel|CURRENTEL}}, x12
+# CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12
+# CHECK: msr {{spsr_abt|SPSR_ABT}}, x12
+# CHECK: msr {{spsr_und|SPSR_UND}}, x12
+# CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12
+# CHECK: msr {{fpcr|FPCR}}, x12
+# CHECK: msr {{fpsr|FPSR}}, x12
+# CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12
+# CHECK: msr {{dlr_el0|DLR_EL0}}, x12
+# CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12
+# CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12
+# CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12
+# CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12
+# CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12
+# CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12
+# CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12
+# CHECK: msr {{esr_el1|ESR_EL1}}, x12
+# CHECK: msr {{esr_el2|ESR_EL2}}, x12
+# CHECK: msr {{esr_el3|ESR_EL3}}, x12
+# CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12
+# CHECK: msr {{far_el1|FAR_EL1}}, x12
+# CHECK: msr {{far_el2|FAR_EL2}}, x12
+# CHECK: msr {{far_el3|FAR_EL3}}, x12
+# CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12
+# CHECK: msr {{par_el1|PAR_EL1}}, x12
+# CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12
+# CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12
+# CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12
+# CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12
+# CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12
+# CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12
+# CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12
+# CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12
+# CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12
+# CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12
+# CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
+# CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12
+# CHECK: msr {{mair_el1|MAIR_EL1}}, x12
+# CHECK: msr {{mair_el2|MAIR_EL2}}, x12
+# CHECK: msr {{mair_el3|MAIR_EL3}}, x12
+# CHECK: msr {{amair_el1|AMAIR_EL1}}, x12
+# CHECK: msr {{amair_el2|AMAIR_EL2}}, x12
+# CHECK: msr {{amair_el3|AMAIR_EL3}}, x12
+# CHECK: msr {{vbar_el1|VBAR_EL1}}, x12
+# CHECK: msr {{vbar_el2|VBAR_EL2}}, x12
+# CHECK: msr {{vbar_el3|VBAR_EL3}}, x12
+# CHECK: msr {{rmr_el1|RMR_EL1}}, x12
+# CHECK: msr {{rmr_el2|RMR_EL2}}, x12
+# CHECK: msr {{rmr_el3|RMR_EL3}}, x12
+# CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12
+# CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12
+# CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12
+# CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12
+# CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12
+# CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12
+# CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12
+# CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12
+# CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12
+# CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12
+# CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12
+# CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12
+# CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12
+# CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12
+# CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12
+# CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12
+# CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12
+# CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12
+# CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12
+# CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12
+# CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12
+# CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12
+# CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12
+# CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12
+# CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12
+# CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12
+# CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12
+# CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12
+# CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12
+# CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12
+# CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12
+# CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12
+# CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12
+# CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12
+# CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12
+# CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12
+# CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12
+# CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12
+# CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12
+# CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12
+# CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12
+# CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12
+# CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12
+# CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12
+# CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12
+# CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12
+# CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12
+# CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12
+# CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12
+# CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12
+# CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12
+# CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12
+# CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12
+# CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12
+# CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12
+# CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12
+# CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12
+# CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12
+# CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12
+# CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12
+# CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12
+# CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12
+# CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12
+# CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12
+# CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12
+# CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12
+# CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12
+# CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12
+# CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12
+# CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12
+# CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12
+# CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12
+# CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12
+# CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12
+# CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12
+# CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12
+# CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12
+# CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12
+# CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12
+# CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12
+# CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12
+# CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12
+# CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12
+# CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12
+# CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}}
+# CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}}
+# CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}}
+# CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}}
+# CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}}
+# CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}}
+# CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}}
+# CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}}
+# CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}}
+# CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}}
+# CHECK: mrs x9, {{dbgbvr0_el1|DBGBVR0_EL1}}
+# CHECK: mrs x9, {{dbgbvr1_el1|DBGBVR1_EL1}}
+# CHECK: mrs x9, {{dbgbvr2_el1|DBGBVR2_EL1}}
+# CHECK: mrs x9, {{dbgbvr3_el1|DBGBVR3_EL1}}
+# CHECK: mrs x9, {{dbgbvr4_el1|DBGBVR4_EL1}}
+# CHECK: mrs x9, {{dbgbvr5_el1|DBGBVR5_EL1}}
+# CHECK: mrs x9, {{dbgbvr6_el1|DBGBVR6_EL1}}
+# CHECK: mrs x9, {{dbgbvr7_el1|DBGBVR7_EL1}}
+# CHECK: mrs x9, {{dbgbvr8_el1|DBGBVR8_EL1}}
+# CHECK: mrs x9, {{dbgbvr9_el1|DBGBVR9_EL1}}
+# CHECK: mrs x9, {{dbgbvr10_el1|DBGBVR10_EL1}}
+# CHECK: mrs x9, {{dbgbvr11_el1|DBGBVR11_EL1}}
+# CHECK: mrs x9, {{dbgbvr12_el1|DBGBVR12_EL1}}
+# CHECK: mrs x9, {{dbgbvr13_el1|DBGBVR13_EL1}}
+# CHECK: mrs x9, {{dbgbvr14_el1|DBGBVR14_EL1}}
+# CHECK: mrs x9, {{dbgbvr15_el1|DBGBVR15_EL1}}
+# CHECK: mrs x9, {{dbgbcr0_el1|DBGBCR0_EL1}}
+# CHECK: mrs x9, {{dbgbcr1_el1|DBGBCR1_EL1}}
+# CHECK: mrs x9, {{dbgbcr2_el1|DBGBCR2_EL1}}
+# CHECK: mrs x9, {{dbgbcr3_el1|DBGBCR3_EL1}}
+# CHECK: mrs x9, {{dbgbcr4_el1|DBGBCR4_EL1}}
+# CHECK: mrs x9, {{dbgbcr5_el1|DBGBCR5_EL1}}
+# CHECK: mrs x9, {{dbgbcr6_el1|DBGBCR6_EL1}}
+# CHECK: mrs x9, {{dbgbcr7_el1|DBGBCR7_EL1}}
+# CHECK: mrs x9, {{dbgbcr8_el1|DBGBCR8_EL1}}
+# CHECK: mrs x9, {{dbgbcr9_el1|DBGBCR9_EL1}}
+# CHECK: mrs x9, {{dbgbcr10_el1|DBGBCR10_EL1}}
+# CHECK: mrs x9, {{dbgbcr11_el1|DBGBCR11_EL1}}
+# CHECK: mrs x9, {{dbgbcr12_el1|DBGBCR12_EL1}}
+# CHECK: mrs x9, {{dbgbcr13_el1|DBGBCR13_EL1}}
+# CHECK: mrs x9, {{dbgbcr14_el1|DBGBCR14_EL1}}
+# CHECK: mrs x9, {{dbgbcr15_el1|DBGBCR15_EL1}}
+# CHECK: mrs x9, {{dbgwvr0_el1|DBGWVR0_EL1}}
+# CHECK: mrs x9, {{dbgwvr1_el1|DBGWVR1_EL1}}
+# CHECK: mrs x9, {{dbgwvr2_el1|DBGWVR2_EL1}}
+# CHECK: mrs x9, {{dbgwvr3_el1|DBGWVR3_EL1}}
+# CHECK: mrs x9, {{dbgwvr4_el1|DBGWVR4_EL1}}
+# CHECK: mrs x9, {{dbgwvr5_el1|DBGWVR5_EL1}}
+# CHECK: mrs x9, {{dbgwvr6_el1|DBGWVR6_EL1}}
+# CHECK: mrs x9, {{dbgwvr7_el1|DBGWVR7_EL1}}
+# CHECK: mrs x9, {{dbgwvr8_el1|DBGWVR8_EL1}}
+# CHECK: mrs x9, {{dbgwvr9_el1|DBGWVR9_EL1}}
+# CHECK: mrs x9, {{dbgwvr10_el1|DBGWVR10_EL1}}
+# CHECK: mrs x9, {{dbgwvr11_el1|DBGWVR11_EL1}}
+# CHECK: mrs x9, {{dbgwvr12_el1|DBGWVR12_EL1}}
+# CHECK: mrs x9, {{dbgwvr13_el1|DBGWVR13_EL1}}
+# CHECK: mrs x9, {{dbgwvr14_el1|DBGWVR14_EL1}}
+# CHECK: mrs x9, {{dbgwvr15_el1|DBGWVR15_EL1}}
+# CHECK: mrs x9, {{dbgwcr0_el1|DBGWCR0_EL1}}
+# CHECK: mrs x9, {{dbgwcr1_el1|DBGWCR1_EL1}}
+# CHECK: mrs x9, {{dbgwcr2_el1|DBGWCR2_EL1}}
+# CHECK: mrs x9, {{dbgwcr3_el1|DBGWCR3_EL1}}
+# CHECK: mrs x9, {{dbgwcr4_el1|DBGWCR4_EL1}}
+# CHECK: mrs x9, {{dbgwcr5_el1|DBGWCR5_EL1}}
+# CHECK: mrs x9, {{dbgwcr6_el1|DBGWCR6_EL1}}
+# CHECK: mrs x9, {{dbgwcr7_el1|DBGWCR7_EL1}}
+# CHECK: mrs x9, {{dbgwcr8_el1|DBGWCR8_EL1}}
+# CHECK: mrs x9, {{dbgwcr9_el1|DBGWCR9_EL1}}
+# CHECK: mrs x9, {{dbgwcr10_el1|DBGWCR10_EL1}}
+# CHECK: mrs x9, {{dbgwcr11_el1|DBGWCR11_EL1}}
+# CHECK: mrs x9, {{dbgwcr12_el1|DBGWCR12_EL1}}
+# CHECK: mrs x9, {{dbgwcr13_el1|DBGWCR13_EL1}}
+# CHECK: mrs x9, {{dbgwcr14_el1|DBGWCR14_EL1}}
+# CHECK: mrs x9, {{dbgwcr15_el1|DBGWCR15_EL1}}
+# CHECK: mrs x9, {{mdrar_el1|MDRAR_EL1}}
+# CHECK: mrs x9, {{teehbr32_el1|TEEHBR32_EL1}}
+# CHECK: mrs x9, {{oslsr_el1|OSLSR_EL1}}
+# CHECK: mrs x9, {{osdlr_el1|OSDLR_EL1}}
+# CHECK: mrs x9, {{dbgprcr_el1|DBGPRCR_EL1}}
+# CHECK: mrs x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}}
+# CHECK: mrs x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}
+# CHECK: mrs x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}}
+# CHECK: mrs x9, {{midr_el1|MIDR_EL1}}
+# CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}}
+# CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}}
+# CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}}
+# CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}}
+# CHECK: mrs x9, {{ctr_el0|CTR_EL0}}
+# CHECK: mrs x9, {{mpidr_el1|MPIDR_EL1}}
+# CHECK: mrs x9, {{vmpidr_el2|VMPIDR_EL2}}
+# CHECK: mrs x9, {{revidr_el1|REVIDR_EL1}}
+# CHECK: mrs x9, {{aidr_el1|AIDR_EL1}}
+# CHECK: mrs x9, {{dczid_el0|DCZID_EL0}}
+# CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}}
+# CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}}
+# CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}}
+# CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}}
+# CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}
+# CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}
+# CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}
+# CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}
+# CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}}
+# CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}}
+# CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}}
+# CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}}
+# CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}}
+# CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}}
+# CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}}
+# CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}}
+# CHECK: mrs x9, {{mvfr2_el1|MVFR2_EL1}}
+# CHECK: mrs x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}}
+# CHECK: mrs x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}}
+# CHECK: mrs x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}}
+# CHECK: mrs x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}}
+# CHECK: mrs x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}}
+# CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}
+# CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}
+# CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}
+# CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}
+# CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}
+# CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}}
+# CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}}
+# CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}}
+# CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}}
+# CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}}
+# CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}}
+# CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}}
+# CHECK: mrs x9, {{hcr_el2|HCR_EL2}}
+# CHECK: mrs x9, {{scr_el3|SCR_EL3}}
+# CHECK: mrs x9, {{mdcr_el2|MDCR_EL2}}
+# CHECK: mrs x9, {{sder32_el3|SDER32_EL3}}
+# CHECK: mrs x9, {{cptr_el2|CPTR_EL2}}
+# CHECK: mrs x9, {{cptr_el3|CPTR_EL3}}
+# CHECK: mrs x9, {{hstr_el2|HSTR_EL2}}
+# CHECK: mrs x9, {{hacr_el2|HACR_EL2}}
+# CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}}
+# CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}}
+# CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}}
+# CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}}
+# CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}}
+# CHECK: mrs x9, {{tcr_el1|TCR_EL1}}
+# CHECK: mrs x9, {{tcr_el2|TCR_EL2}}
+# CHECK: mrs x9, {{tcr_el3|TCR_EL3}}
+# CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}}
+# CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}}
+# CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}}
+# CHECK: mrs x9, {{spsr_el1|SPSR_EL1}}
+# CHECK: mrs x9, {{spsr_el2|SPSR_EL2}}
+# CHECK: mrs x9, {{spsr_el3|SPSR_EL3}}
+# CHECK: mrs x9, {{elr_el1|ELR_EL1}}
+# CHECK: mrs x9, {{elr_el2|ELR_EL2}}
+# CHECK: mrs x9, {{elr_el3|ELR_EL3}}
+# CHECK: mrs x9, {{sp_el0|SP_EL0}}
+# CHECK: mrs x9, {{sp_el1|SP_EL1}}
+# CHECK: mrs x9, {{sp_el2|SP_EL2}}
+# CHECK: mrs x9, {{spsel|SPSEL}}
+# CHECK: mrs x9, {{nzcv|NZCV}}
+# CHECK: mrs x9, {{daif|DAIF}}
+# CHECK: mrs x9, {{currentel|CURRENTEL}}
+# CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}}
+# CHECK: mrs x9, {{spsr_abt|SPSR_ABT}}
+# CHECK: mrs x9, {{spsr_und|SPSR_UND}}
+# CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}}
+# CHECK: mrs x9, {{fpcr|FPCR}}
+# CHECK: mrs x9, {{fpsr|FPSR}}
+# CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}}
+# CHECK: mrs x9, {{dlr_el0|DLR_EL0}}
+# CHECK: mrs x9, {{ifsr32_el2|IFSR32_EL2}}
+# CHECK: mrs x9, {{afsr0_el1|AFSR0_EL1}}
+# CHECK: mrs x9, {{afsr0_el2|AFSR0_EL2}}
+# CHECK: mrs x9, {{afsr0_el3|AFSR0_EL3}}
+# CHECK: mrs x9, {{afsr1_el1|AFSR1_EL1}}
+# CHECK: mrs x9, {{afsr1_el2|AFSR1_EL2}}
+# CHECK: mrs x9, {{afsr1_el3|AFSR1_EL3}}
+# CHECK: mrs x9, {{esr_el1|ESR_EL1}}
+# CHECK: mrs x9, {{esr_el2|ESR_EL2}}
+# CHECK: mrs x9, {{esr_el3|ESR_EL3}}
+# CHECK: mrs x9, {{fpexc32_el2|FPEXC32_EL2}}
+# CHECK: mrs x9, {{far_el1|FAR_EL1}}
+# CHECK: mrs x9, {{far_el2|FAR_EL2}}
+# CHECK: mrs x9, {{far_el3|FAR_EL3}}
+# CHECK: mrs x9, {{hpfar_el2|HPFAR_EL2}}
+# CHECK: mrs x9, {{par_el1|PAR_EL1}}
+# CHECK: mrs x9, {{pmcr_el0|PMCR_EL0}}
+# CHECK: mrs x9, {{pmcntenset_el0|PMCNTENSET_EL0}}
+# CHECK: mrs x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}}
+# CHECK: mrs x9, {{pmovsclr_el0|PMOVSCLR_EL0}}
+# CHECK: mrs x9, {{pmselr_el0|PMSELR_EL0}}
+# CHECK: mrs x9, {{pmceid0_el0|PMCEID0_EL0}}
+# CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}}
+# CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}}
+# CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}}
+# CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}}
+# CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}}
+# CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}}
+# CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}}
+# CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}}
+# CHECK: mrs x9, {{mair_el1|MAIR_EL1}}
+# CHECK: mrs x9, {{mair_el2|MAIR_EL2}}
+# CHECK: mrs x9, {{mair_el3|MAIR_EL3}}
+# CHECK: mrs x9, {{amair_el1|AMAIR_EL1}}
+# CHECK: mrs x9, {{amair_el2|AMAIR_EL2}}
+# CHECK: mrs x9, {{amair_el3|AMAIR_EL3}}
+# CHECK: mrs x9, {{vbar_el1|VBAR_EL1}}
+# CHECK: mrs x9, {{vbar_el2|VBAR_EL2}}
+# CHECK: mrs x9, {{vbar_el3|VBAR_EL3}}
+# CHECK: mrs x9, {{rvbar_el1|RVBAR_EL1}}
+# CHECK: mrs x9, {{rvbar_el2|RVBAR_EL2}}
+# CHECK: mrs x9, {{rvbar_el3|RVBAR_EL3}}
+# CHECK: mrs x9, {{rmr_el1|RMR_EL1}}
+# CHECK: mrs x9, {{rmr_el2|RMR_EL2}}
+# CHECK: mrs x9, {{rmr_el3|RMR_EL3}}
+# CHECK: mrs x9, {{isr_el1|ISR_EL1}}
+# CHECK: mrs x9, {{contextidr_el1|CONTEXTIDR_EL1}}
+# CHECK: mrs x9, {{tpidr_el0|TPIDR_EL0}}
+# CHECK: mrs x9, {{tpidr_el2|TPIDR_EL2}}
+# CHECK: mrs x9, {{tpidr_el3|TPIDR_EL3}}
+# CHECK: mrs x9, {{tpidrro_el0|TPIDRRO_EL0}}
+# CHECK: mrs x9, {{tpidr_el1|TPIDR_EL1}}
+# CHECK: mrs x9, {{cntfrq_el0|CNTFRQ_EL0}}
+# CHECK: mrs x9, {{cntpct_el0|CNTPCT_EL0}}
+# CHECK: mrs x9, {{cntvct_el0|CNTVCT_EL0}}
+# CHECK: mrs x9, {{cntvoff_el2|CNTVOFF_EL2}}
+# CHECK: mrs x9, {{cntkctl_el1|CNTKCTL_EL1}}
+# CHECK: mrs x9, {{cnthctl_el2|CNTHCTL_EL2}}
+# CHECK: mrs x9, {{cntp_tval_el0|CNTP_TVAL_EL0}}
+# CHECK: mrs x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}}
+# CHECK: mrs x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}}
+# CHECK: mrs x9, {{cntp_ctl_el0|CNTP_CTL_EL0}}
+# CHECK: mrs x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}}
+# CHECK: mrs x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}}
+# CHECK: mrs x9, {{cntp_cval_el0|CNTP_CVAL_EL0}}
+# CHECK: mrs x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}}
+# CHECK: mrs x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}}
+# CHECK: mrs x9, {{cntv_tval_el0|CNTV_TVAL_EL0}}
+# CHECK: mrs x9, {{cntv_ctl_el0|CNTV_CTL_EL0}}
+# CHECK: mrs x9, {{cntv_cval_el0|CNTV_CVAL_EL0}}
+# CHECK: mrs x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}}
+# CHECK: mrs x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}}
+# CHECK: mrs x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}}
+# CHECK: mrs x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}}
+# CHECK: mrs x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}}
+# CHECK: mrs x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}}
+# CHECK: mrs x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}}
+# CHECK: mrs x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}}
+# CHECK: mrs x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}}
+# CHECK: mrs x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}}
+# CHECK: mrs x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}}
+# CHECK: mrs x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}}
+# CHECK: mrs x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}}
+# CHECK: mrs x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}}
+# CHECK: mrs x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}}
+# CHECK: mrs x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}}
+# CHECK: mrs x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}}
+# CHECK: mrs x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}}
+# CHECK: mrs x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}}
+# CHECK: mrs x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}}
+# CHECK: mrs x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}}
+# CHECK: mrs x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}}
+# CHECK: mrs x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}}
+# CHECK: mrs x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}}
+# CHECK: mrs x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}}
+# CHECK: mrs x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}}
+# CHECK: mrs x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}}
+# CHECK: mrs x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}}
+# CHECK: mrs x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}}
+# CHECK: mrs x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}}
+# CHECK: mrs x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}}
+# CHECK: mrs x9, {{pmccfiltr_el0|PMCCFILTR_EL0}}
+# CHECK: mrs x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}}
+# CHECK: mrs x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}}
+# CHECK: mrs x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}}
+# CHECK: mrs x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}}
+# CHECK: mrs x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}}
+# CHECK: mrs x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}}
+# CHECK: mrs x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}}
+# CHECK: mrs x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}}
+# CHECK: mrs x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}}
+# CHECK: mrs x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}}
+# CHECK: mrs x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}}
+# CHECK: mrs x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}}
+# CHECK: mrs x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}}
+# CHECK: mrs x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}}
+# CHECK: mrs x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}}
+# CHECK: mrs x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}}
+# CHECK: mrs x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}}
+# CHECK: mrs x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}}
+# CHECK: mrs x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}}
+# CHECK: mrs x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}}
+# CHECK: mrs x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}}
+# CHECK: mrs x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}}
+# CHECK: mrs x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}}
+# CHECK: mrs x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}}
+# CHECK: mrs x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}}
+# CHECK: mrs x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}}
+# CHECK: mrs x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}}
+# CHECK: mrs x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}}
+# CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}}
+# CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}}
+# CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}}
0xc 0x0 0x12 0xd5
0x4c 0x0 0x10 0xd5
@@ -4147,10 +4148,10 @@
0xa9 0xef 0x3b 0xd5
0xc9 0xef 0x3b 0xd5
-# CHECK: mrs x12, s3_7_c15_c1_5
-# CHECK: mrs x13, s3_2_c11_c15_7
-# CHECK: msr s3_0_c15_c0_0, x12
-# CHECK: msr s3_7_c11_c13_7, x5
+# CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
+# CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}
+# CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12
+# CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5
0xac 0xf1 0x3f 0xd5
0xed 0xbf 0x3a 0xd5
0x0c 0xf0 0x18 0xd5
Modified: llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt?rev=207753&r1=207752&r2=207753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt Thu May 1 07:29:56 2014
@@ -1,222 +1,223 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s
0x8 0xcc 0x38 0xd5
-# CHECK: mrs x8, icc_iar1_el1
+# CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}}
0x1a 0xc8 0x38 0xd5
-# CHECK: mrs x26, icc_iar0_el1
+# CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}}
0x42 0xcc 0x38 0xd5
-# CHECK: mrs x2, icc_hppir1_el1
+# CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}}
0x51 0xc8 0x38 0xd5
-# CHECK: mrs x17, icc_hppir0_el1
+# CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}}
0x7d 0xcb 0x38 0xd5
-# CHECK: mrs x29, icc_rpr_el1
+# CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}}
0x24 0xcb 0x3c 0xd5
-# CHECK: mrs x4, ich_vtr_el2
+# CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}}
0x78 0xcb 0x3c 0xd5
-# CHECK: mrs x24, ich_eisr_el2
+# CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}}
0xa9 0xcb 0x3c 0xd5
-# CHECK: mrs x9, ich_elsr_el2
+# CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}}
0x78 0xcc 0x38 0xd5
-# CHECK: mrs x24, icc_bpr1_el1
+# CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}}
0x6e 0xc8 0x38 0xd5
-# CHECK: mrs x14, icc_bpr0_el1
+# CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}}
0x13 0x46 0x38 0xd5
-# CHECK: mrs x19, icc_pmr_el1
+# CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}}
0x97 0xcc 0x38 0xd5
-# CHECK: mrs x23, icc_ctlr_el1
+# CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}}
0x94 0xcc 0x3e 0xd5
-# CHECK: mrs x20, icc_ctlr_el3
+# CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}}
0xbc 0xcc 0x38 0xd5
-# CHECK: mrs x28, icc_sre_el1
+# CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}}
0xb9 0xc9 0x3c 0xd5
-# CHECK: mrs x25, icc_sre_el2
+# CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}}
0xa8 0xcc 0x3e 0xd5
-# CHECK: mrs x8, icc_sre_el3
+# CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}}
0xd6 0xcc 0x38 0xd5
-# CHECK: mrs x22, icc_igrpen0_el1
+# CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}
0xe5 0xcc 0x38 0xd5
-# CHECK: mrs x5, icc_igrpen1_el1
+# CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}
0xe7 0xcc 0x3e 0xd5
-# CHECK: mrs x7, icc_igrpen1_el3
+# CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}
0x16 0xcd 0x38 0xd5
-# CHECK: mrs x22, icc_seien_el1
+# CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}}
0x84 0xc8 0x38 0xd5
-# CHECK: mrs x4, icc_ap0r0_el1
+# CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}}
0xab 0xc8 0x38 0xd5
-# CHECK: mrs x11, icc_ap0r1_el1
+# CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}}
0xdb 0xc8 0x38 0xd5
-# CHECK: mrs x27, icc_ap0r2_el1
+# CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}}
0xf5 0xc8 0x38 0xd5
-# CHECK: mrs x21, icc_ap0r3_el1
+# CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}}
0x2 0xc9 0x38 0xd5
-# CHECK: mrs x2, icc_ap1r0_el1
+# CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}}
0x35 0xc9 0x38 0xd5
-# CHECK: mrs x21, icc_ap1r1_el1
+# CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}}
0x4a 0xc9 0x38 0xd5
-# CHECK: mrs x10, icc_ap1r2_el1
+# CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}}
0x7b 0xc9 0x38 0xd5
-# CHECK: mrs x27, icc_ap1r3_el1
+# CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}}
0x14 0xc8 0x3c 0xd5
-# CHECK: mrs x20, ich_ap0r0_el2
+# CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}}
0x35 0xc8 0x3c 0xd5
-# CHECK: mrs x21, ich_ap0r1_el2
+# CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}}
0x45 0xc8 0x3c 0xd5
-# CHECK: mrs x5, ich_ap0r2_el2
+# CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}}
0x64 0xc8 0x3c 0xd5
-# CHECK: mrs x4, ich_ap0r3_el2
+# CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}}
0xf 0xc9 0x3c 0xd5
-# CHECK: mrs x15, ich_ap1r0_el2
+# CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}}
0x2c 0xc9 0x3c 0xd5
-# CHECK: mrs x12, ich_ap1r1_el2
+# CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}}
0x5b 0xc9 0x3c 0xd5
-# CHECK: mrs x27, ich_ap1r2_el2
+# CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}}
0x74 0xc9 0x3c 0xd5
-# CHECK: mrs x20, ich_ap1r3_el2
+# CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}}
0xa 0xcb 0x3c 0xd5
-# CHECK: mrs x10, ich_hcr_el2
+# CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}}
0x5b 0xcb 0x3c 0xd5
-# CHECK: mrs x27, ich_misr_el2
+# CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}}
0xe6 0xcb 0x3c 0xd5
-# CHECK: mrs x6, ich_vmcr_el2
+# CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}}
0x93 0xc9 0x3c 0xd5
-# CHECK: mrs x19, ich_vseir_el2
+# CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}}
0x3 0xcc 0x3c 0xd5
-# CHECK: mrs x3, ich_lr0_el2
+# CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}}
0x21 0xcc 0x3c 0xd5
-# CHECK: mrs x1, ich_lr1_el2
+# CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}}
0x56 0xcc 0x3c 0xd5
-# CHECK: mrs x22, ich_lr2_el2
+# CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}}
0x75 0xcc 0x3c 0xd5
-# CHECK: mrs x21, ich_lr3_el2
+# CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}}
0x86 0xcc 0x3c 0xd5
-# CHECK: mrs x6, ich_lr4_el2
+# CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}}
0xaa 0xcc 0x3c 0xd5
-# CHECK: mrs x10, ich_lr5_el2
+# CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}}
0xcb 0xcc 0x3c 0xd5
-# CHECK: mrs x11, ich_lr6_el2
+# CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}}
0xec 0xcc 0x3c 0xd5
-# CHECK: mrs x12, ich_lr7_el2
+# CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}}
0x0 0xcd 0x3c 0xd5
-# CHECK: mrs x0, ich_lr8_el2
+# CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}}
0x35 0xcd 0x3c 0xd5
-# CHECK: mrs x21, ich_lr9_el2
+# CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}}
0x4d 0xcd 0x3c 0xd5
-# CHECK: mrs x13, ich_lr10_el2
+# CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}}
0x7a 0xcd 0x3c 0xd5
-# CHECK: mrs x26, ich_lr11_el2
+# CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}}
0x81 0xcd 0x3c 0xd5
-# CHECK: mrs x1, ich_lr12_el2
+# CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}}
0xa8 0xcd 0x3c 0xd5
-# CHECK: mrs x8, ich_lr13_el2
+# CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}}
0xc2 0xcd 0x3c 0xd5
-# CHECK: mrs x2, ich_lr14_el2
+# CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}}
0xe8 0xcd 0x3c 0xd5
-# CHECK: mrs x8, ich_lr15_el2
+# CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}}
0x3b 0xcc 0x18 0xd5
-# CHECK: msr icc_eoir1_el1, x27
+# CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27
0x25 0xc8 0x18 0xd5
-# CHECK: msr icc_eoir0_el1, x5
+# CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5
0x2d 0xcb 0x18 0xd5
-# CHECK: msr icc_dir_el1, x13
+# CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13
0xb5 0xcb 0x18 0xd5
-# CHECK: msr icc_sgi1r_el1, x21
+# CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21
0xd9 0xcb 0x18 0xd5
-# CHECK: msr icc_asgi1r_el1, x25
+# CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25
0xfc 0xcb 0x18 0xd5
-# CHECK: msr icc_sgi0r_el1, x28
+# CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28
0x67 0xcc 0x18 0xd5
-# CHECK: msr icc_bpr1_el1, x7
+# CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7
0x69 0xc8 0x18 0xd5
-# CHECK: msr icc_bpr0_el1, x9
+# CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9
0x1d 0x46 0x18 0xd5
-# CHECK: msr icc_pmr_el1, x29
+# CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29
0x98 0xcc 0x18 0xd5
-# CHECK: msr icc_ctlr_el1, x24
+# CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24
0x80 0xcc 0x1e 0xd5
-# CHECK: msr icc_ctlr_el3, x0
+# CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0
0xa2 0xcc 0x18 0xd5
-# CHECK: msr icc_sre_el1, x2
+# CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x2
0xa5 0xc9 0x1c 0xd5
-# CHECK: msr icc_sre_el2, x5
+# CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x5
0xaa 0xcc 0x1e 0xd5
-# CHECK: msr icc_sre_el3, x10
+# CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x10
0xd6 0xcc 0x18 0xd5
-# CHECK: msr icc_igrpen0_el1, x22
+# CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22
0xeb 0xcc 0x18 0xd5
-# CHECK: msr icc_igrpen1_el1, x11
+# CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11
0xe8 0xcc 0x1e 0xd5
-# CHECK: msr icc_igrpen1_el3, x8
+# CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8
0x4 0xcd 0x18 0xd5
-# CHECK: msr icc_seien_el1, x4
+# CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4
0x9b 0xc8 0x18 0xd5
-# CHECK: msr icc_ap0r0_el1, x27
+# CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27
0xa5 0xc8 0x18 0xd5
-# CHECK: msr icc_ap0r1_el1, x5
+# CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5
0xd4 0xc8 0x18 0xd5
-# CHECK: msr icc_ap0r2_el1, x20
+# CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20
0xe0 0xc8 0x18 0xd5
-# CHECK: msr icc_ap0r3_el1, x0
+# CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0
0x2 0xc9 0x18 0xd5
-# CHECK: msr icc_ap1r0_el1, x2
+# CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2
0x3d 0xc9 0x18 0xd5
-# CHECK: msr icc_ap1r1_el1, x29
+# CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29
0x57 0xc9 0x18 0xd5
-# CHECK: msr icc_ap1r2_el1, x23
+# CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23
0x6b 0xc9 0x18 0xd5
-# CHECK: msr icc_ap1r3_el1, x11
+# CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11
0x2 0xc8 0x1c 0xd5
-# CHECK: msr ich_ap0r0_el2, x2
+# CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2
0x3b 0xc8 0x1c 0xd5
-# CHECK: msr ich_ap0r1_el2, x27
+# CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27
0x47 0xc8 0x1c 0xd5
-# CHECK: msr ich_ap0r2_el2, x7
+# CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7
0x61 0xc8 0x1c 0xd5
-# CHECK: msr ich_ap0r3_el2, x1
+# CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1
0x7 0xc9 0x1c 0xd5
-# CHECK: msr ich_ap1r0_el2, x7
+# CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7
0x2c 0xc9 0x1c 0xd5
-# CHECK: msr ich_ap1r1_el2, x12
+# CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12
0x4e 0xc9 0x1c 0xd5
-# CHECK: msr ich_ap1r2_el2, x14
+# CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14
0x6d 0xc9 0x1c 0xd5
-# CHECK: msr ich_ap1r3_el2, x13
+# CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13
0x1 0xcb 0x1c 0xd5
-# CHECK: msr ich_hcr_el2, x1
+# CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1
0x4a 0xcb 0x1c 0xd5
-# CHECK: msr ich_misr_el2, x10
+# CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10
0xf8 0xcb 0x1c 0xd5
-# CHECK: msr ich_vmcr_el2, x24
+# CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24
0x9d 0xc9 0x1c 0xd5
-# CHECK: msr ich_vseir_el2, x29
+# CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29
0x1a 0xcc 0x1c 0xd5
-# CHECK: msr ich_lr0_el2, x26
+# CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26
0x29 0xcc 0x1c 0xd5
-# CHECK: msr ich_lr1_el2, x9
+# CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9
0x52 0xcc 0x1c 0xd5
-# CHECK: msr ich_lr2_el2, x18
+# CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18
0x7a 0xcc 0x1c 0xd5
-# CHECK: msr ich_lr3_el2, x26
+# CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26
0x96 0xcc 0x1c 0xd5
-# CHECK: msr ich_lr4_el2, x22
+# CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22
0xba 0xcc 0x1c 0xd5
-# CHECK: msr ich_lr5_el2, x26
+# CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26
0xdb 0xcc 0x1c 0xd5
-# CHECK: msr ich_lr6_el2, x27
+# CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27
0xe8 0xcc 0x1c 0xd5
-# CHECK: msr ich_lr7_el2, x8
+# CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8
0x11 0xcd 0x1c 0xd5
-# CHECK: msr ich_lr8_el2, x17
+# CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17
0x33 0xcd 0x1c 0xd5
-# CHECK: msr ich_lr9_el2, x19
+# CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19
0x51 0xcd 0x1c 0xd5
-# CHECK: msr ich_lr10_el2, x17
+# CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17
0x65 0xcd 0x1c 0xd5
-# CHECK: msr ich_lr11_el2, x5
+# CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5
0x9d 0xcd 0x1c 0xd5
-# CHECK: msr ich_lr12_el2, x29
+# CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29
0xa2 0xcd 0x1c 0xd5
-# CHECK: msr ich_lr13_el2, x2
+# CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2
0xcd 0xcd 0x1c 0xd5
-# CHECK: msr ich_lr14_el2, x13
+# CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13
0xfb 0xcd 0x1c 0xd5
-# CHECK: msr ich_lr15_el2, x27
+# CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27
Modified: llvm/trunk/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt?rev=207753&r1=207752&r2=207753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt Thu May 1 07:29:56 2014
@@ -1,4 +1,5 @@
# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -triple=arm64 -disassemble < %s 2>&1 | FileCheck %s
# Stores are OK.
0xe0 0x83 0x00 0xa9
Modified: llvm/trunk/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt?rev=207753&r1=207752&r2=207753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt Thu May 1 07:29:56 2014
@@ -1,4 +1,5 @@
# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
# None of these instructions should be classified as unpredictable:
Modified: llvm/trunk/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt?rev=207753&r1=207752&r2=207753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt Thu May 1 07:29:56 2014
@@ -1,4 +1,5 @@
# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
# None of these instructions should be classified as unpredictable:
Modified: llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt?rev=207753&r1=207752&r2=207753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt Thu May 1 07:29:56 2014
@@ -1,4 +1,5 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s
#------------------------------------------------------------------------------
# Vector Integer Add/Sub
@@ -87,7 +88,7 @@
# Vector Bitwise OR - immedidate
#------------------------------------------------------------------------------
# CHECK: movi v31.4s, #0xff, lsl #24
-# CHECK: mvni v0.2s, #0x0
+# CHECK: mvni v0.2s, #{{0x0|0}}
# CHECK: bic v15.4h, #0xf, lsl #8
# CHECK: orr v16.8h, #0x1f
0xff 0x67 0x07 0x4f
@@ -246,31 +247,31 @@
#----------------------------------------------------------------------
# Vector Compare Mask Equal to Zero (Integer)
#----------------------------------------------------------------------
-# CHECK: cmeq v31.16b, v15.16b, #0x0
+# CHECK: cmeq v31.16b, v15.16b, #{{0x0|0}}
0xff 0x99 0x20 0x4e
#----------------------------------------------------------------------
# Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
#----------------------------------------------------------------------
-# CHECK: cmge v3.8b, v15.8b, #0x0
+# CHECK: cmge v3.8b, v15.8b, #{{0x0|0}}
0xe3 0x89 0x20 0x2e
#----------------------------------------------------------------------
# Vector Compare Mask Greater Than Zero (Signed Integer)
#----------------------------------------------------------------------
-# CHECK: cmgt v22.2s, v9.2s, #0x0
+# CHECK: cmgt v22.2s, v9.2s, #{{0x0|0}}
0x36 0x89 0xa0 0x0e
#----------------------------------------------------------------------
# Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
#----------------------------------------------------------------------
-# CHECK: cmle v5.2d, v14.2d, #0x0
+# CHECK: cmle v5.2d, v14.2d, #{{0x0|0}}
0xc5 0x99 0xe0 0x6e
#----------------------------------------------------------------------
# Vector Compare Mask Less Than Zero (Signed Integer)
#----------------------------------------------------------------------
-# CHECK: cmlt v13.8h, v11.8h, #0x0
+# CHECK: cmlt v13.8h, v11.8h, #{{0x0|0}}
0x6d 0xa9 0x60 0x4e
#----------------------------------------------------------------------
@@ -1559,7 +1560,7 @@
#----------------------------------------------------------------------
# Scalar Compare Bitwise Equal To Zero
#----------------------------------------------------------------------
-# CHECK: cmeq d20, d21, #0x0
+# CHECK: cmeq d20, d21, #{{0x0|0}}
0xb4,0x9a,0xe0,0x5e
#----------------------------------------------------------------------
@@ -1578,7 +1579,7 @@
#----------------------------------------------------------------------
# Scalar Compare Signed Greather Than Or Equal To Zero
#----------------------------------------------------------------------
-# CHECK: cmge d20, d21, #0x0
+# CHECK: cmge d20, d21, #{{0x0|0}}
0xb4,0x8a,0xe0,0x7e
#----------------------------------------------------------------------
@@ -1596,19 +1597,19 @@
#----------------------------------------------------------------------
# Scalar Compare Signed Greater Than Zero
#----------------------------------------------------------------------
-# CHECK: cmgt d20, d21, #0x0
+# CHECK: cmgt d20, d21, #{{0x0|0}}
0xb4,0x8a,0xe0,0x5e
#----------------------------------------------------------------------
# Scalar Compare Signed Less Than Or Equal To Zero
#----------------------------------------------------------------------
-# CHECK: cmle d20, d21, #0x0
+# CHECK: cmle d20, d21, #{{0x0|0}}
0xb4,0x9a,0xe0,0x7e
#----------------------------------------------------------------------
# Scalar Compare Less Than Zero
#----------------------------------------------------------------------
-# CHECK: cmlt d20, d21, #0x0
+# CHECK: cmlt d20, d21, #{{0x0|0}}
0xb4,0xaa,0xe0,0x5e
#----------------------------------------------------------------------
@@ -2167,8 +2168,8 @@
#----------------------------------------------------------------------
0x20,0x18,0x02,0x2e
0x20,0x18,0x02,0x6e
-# CHECK: ext v0.8b, v1.8b, v2.8b, #0x3
-# CHECK: ext v0.16b, v1.16b, v2.16b, #0x3
+# CHECK: ext v0.8b, v1.8b, v2.8b, #{{0x3|3}}
+# CHECK: ext v0.16b, v1.16b, v2.16b, #{{0x3|3}}
#----------------------------------------------------------------------
# unzip with 3 same vectors to get primary result
@@ -2481,10 +2482,10 @@
#----------------------------------------------------------------------
#Duplicate element (scalar)
#----------------------------------------------------------------------
-# CHECK: dup b0, v0.b[15]
-# CHECK: dup h2, v31.h[5]
-# CHECK: dup s17, v2.s[2]
-# CHECK: dup d6, v12.d[1]
+# CHECK: {{dup|mov}} b0, v0.b[15]
+# CHECK: {{dup|mov}} h2, v31.h[5]
+# CHECK: {{dup|mov}} s17, v2.s[2]
+# CHECK: {{dup|mov}} d6, v12.d[1]
0x00 0x04 0x1f 0x5e
0xe2 0x07 0x16 0x5e
0x51 0x04 0x14 0x5e
Modified: llvm/trunk/test/MC/Disassembler/AArch64/trace-regs.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/trace-regs.txt?rev=207753&r1=207752&r2=207753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/trace-regs.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/trace-regs.txt Thu May 1 07:29:56 2014
@@ -1,736 +1,737 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s
0x8 0x3 0x31 0xd5
-# CHECK: mrs x8, trcstatr
+# CHECK: mrs x8, {{trcstatr|TRCSTATR}}
0xc9 0x0 0x31 0xd5
-# CHECK: mrs x9, trcidr8
+# CHECK: mrs x9, {{trcidr8|TRCIDR8}}
0xcb 0x1 0x31 0xd5
-# CHECK: mrs x11, trcidr9
+# CHECK: mrs x11, {{trcidr9|TRCIDR9}}
0xd9 0x2 0x31 0xd5
-# CHECK: mrs x25, trcidr10
+# CHECK: mrs x25, {{trcidr10|TRCIDR10}}
0xc7 0x3 0x31 0xd5
-# CHECK: mrs x7, trcidr11
+# CHECK: mrs x7, {{trcidr11|TRCIDR11}}
0xc7 0x4 0x31 0xd5
-# CHECK: mrs x7, trcidr12
+# CHECK: mrs x7, {{trcidr12|TRCIDR12}}
0xc6 0x5 0x31 0xd5
-# CHECK: mrs x6, trcidr13
+# CHECK: mrs x6, {{trcidr13|TRCIDR13}}
0xfb 0x8 0x31 0xd5
-# CHECK: mrs x27, trcidr0
+# CHECK: mrs x27, {{trcidr0|TRCIDR0}}
0xfd 0x9 0x31 0xd5
-# CHECK: mrs x29, trcidr1
+# CHECK: mrs x29, {{trcidr1|TRCIDR1}}
0xe4 0xa 0x31 0xd5
-# CHECK: mrs x4, trcidr2
+# CHECK: mrs x4, {{trcidr2|TRCIDR2}}
0xe8 0xb 0x31 0xd5
-# CHECK: mrs x8, trcidr3
+# CHECK: mrs x8, {{trcidr3|TRCIDR3}}
0xef 0xc 0x31 0xd5
-# CHECK: mrs x15, trcidr4
+# CHECK: mrs x15, {{trcidr4|TRCIDR4}}
0xf4 0xd 0x31 0xd5
-# CHECK: mrs x20, trcidr5
+# CHECK: mrs x20, {{trcidr5|TRCIDR5}}
0xe6 0xe 0x31 0xd5
-# CHECK: mrs x6, trcidr6
+# CHECK: mrs x6, {{trcidr6|TRCIDR6}}
0xe6 0xf 0x31 0xd5
-# CHECK: mrs x6, trcidr7
+# CHECK: mrs x6, {{trcidr7|TRCIDR7}}
0x98 0x11 0x31 0xd5
-# CHECK: mrs x24, trcoslsr
+# CHECK: mrs x24, {{trcoslsr|TRCOSLSR}}
0x92 0x15 0x31 0xd5
-# CHECK: mrs x18, trcpdsr
+# CHECK: mrs x18, {{trcpdsr|TRCPDSR}}
0xdc 0x7a 0x31 0xd5
-# CHECK: mrs x28, trcdevaff0
+# CHECK: mrs x28, {{trcdevaff0|TRCDEVAFF0}}
0xc5 0x7b 0x31 0xd5
-# CHECK: mrs x5, trcdevaff1
+# CHECK: mrs x5, {{trcdevaff1|TRCDEVAFF1}}
0xc5 0x7d 0x31 0xd5
-# CHECK: mrs x5, trclsr
+# CHECK: mrs x5, {{trclsr|TRCLSR}}
0xcb 0x7e 0x31 0xd5
-# CHECK: mrs x11, trcauthstatus
+# CHECK: mrs x11, {{trcauthstatus|TRCAUTHSTATUS}}
0xcd 0x7f 0x31 0xd5
-# CHECK: mrs x13, trcdevarch
+# CHECK: mrs x13, {{trcdevarch|TRCDEVARCH}}
0xf2 0x72 0x31 0xd5
-# CHECK: mrs x18, trcdevid
+# CHECK: mrs x18, {{trcdevid|TRCDEVID}}
0xf6 0x73 0x31 0xd5
-# CHECK: mrs x22, trcdevtype
+# CHECK: mrs x22, {{trcdevtype|TRCDEVTYPE}}
0xee 0x74 0x31 0xd5
-# CHECK: mrs x14, trcpidr4
+# CHECK: mrs x14, {{trcpidr4|TRCPIDR4}}
0xe5 0x75 0x31 0xd5
-# CHECK: mrs x5, trcpidr5
+# CHECK: mrs x5, {{trcpidr5|TRCPIDR5}}
0xe5 0x76 0x31 0xd5
-# CHECK: mrs x5, trcpidr6
+# CHECK: mrs x5, {{trcpidr6|TRCPIDR6}}
0xe9 0x77 0x31 0xd5
-# CHECK: mrs x9, trcpidr7
+# CHECK: mrs x9, {{trcpidr7|TRCPIDR7}}
0xef 0x78 0x31 0xd5
-# CHECK: mrs x15, trcpidr0
+# CHECK: mrs x15, {{trcpidr0|TRCPIDR0}}
0xe6 0x79 0x31 0xd5
-# CHECK: mrs x6, trcpidr1
+# CHECK: mrs x6, {{trcpidr1|TRCPIDR1}}
0xeb 0x7a 0x31 0xd5
-# CHECK: mrs x11, trcpidr2
+# CHECK: mrs x11, {{trcpidr2|TRCPIDR2}}
0xf4 0x7b 0x31 0xd5
-# CHECK: mrs x20, trcpidr3
+# CHECK: mrs x20, {{trcpidr3|TRCPIDR3}}
0xf1 0x7c 0x31 0xd5
-# CHECK: mrs x17, trccidr0
+# CHECK: mrs x17, {{trccidr0|TRCCIDR0}}
0xe2 0x7d 0x31 0xd5
-# CHECK: mrs x2, trccidr1
+# CHECK: mrs x2, {{trccidr1|TRCCIDR1}}
0xf4 0x7e 0x31 0xd5
-# CHECK: mrs x20, trccidr2
+# CHECK: mrs x20, {{trccidr2|TRCCIDR2}}
0xe4 0x7f 0x31 0xd5
-# CHECK: mrs x4, trccidr3
+# CHECK: mrs x4, {{trccidr3|TRCCIDR3}}
0xb 0x1 0x31 0xd5
-# CHECK: mrs x11, trcprgctlr
+# CHECK: mrs x11, {{trcprgctlr|TRCPRGCTLR}}
0x17 0x2 0x31 0xd5
-# CHECK: mrs x23, trcprocselr
+# CHECK: mrs x23, {{trcprocselr|TRCPROCSELR}}
0xd 0x4 0x31 0xd5
-# CHECK: mrs x13, trcconfigr
+# CHECK: mrs x13, {{trcconfigr|TRCCONFIGR}}
0x17 0x6 0x31 0xd5
-# CHECK: mrs x23, trcauxctlr
+# CHECK: mrs x23, {{trcauxctlr|TRCAUXCTLR}}
0x9 0x8 0x31 0xd5
-# CHECK: mrs x9, trceventctl0r
+# CHECK: mrs x9, {{trceventctl0r|TRCEVENTCTL0R}}
0x10 0x9 0x31 0xd5
-# CHECK: mrs x16, trceventctl1r
+# CHECK: mrs x16, {{trceventctl1r|TRCEVENTCTL1R}}
0x4 0xb 0x31 0xd5
-# CHECK: mrs x4, trcstallctlr
+# CHECK: mrs x4, {{trcstallctlr|TRCSTALLCTLR}}
0xe 0xc 0x31 0xd5
-# CHECK: mrs x14, trctsctlr
+# CHECK: mrs x14, {{trctsctlr|TRCTSCTLR}}
0x18 0xd 0x31 0xd5
-# CHECK: mrs x24, trcsyncpr
+# CHECK: mrs x24, {{trcsyncpr|TRCSYNCPR}}
0x1c 0xe 0x31 0xd5
-# CHECK: mrs x28, trcccctlr
+# CHECK: mrs x28, {{trcccctlr|TRCCCCTLR}}
0xf 0xf 0x31 0xd5
-# CHECK: mrs x15, trcbbctlr
+# CHECK: mrs x15, {{trcbbctlr|TRCBBCTLR}}
0x21 0x0 0x31 0xd5
-# CHECK: mrs x1, trctraceidr
+# CHECK: mrs x1, {{trctraceidr|TRCTRACEIDR}}
0x34 0x1 0x31 0xd5
-# CHECK: mrs x20, trcqctlr
+# CHECK: mrs x20, {{trcqctlr|TRCQCTLR}}
0x42 0x0 0x31 0xd5
-# CHECK: mrs x2, trcvictlr
+# CHECK: mrs x2, {{trcvictlr|TRCVICTLR}}
0x4c 0x1 0x31 0xd5
-# CHECK: mrs x12, trcviiectlr
+# CHECK: mrs x12, {{trcviiectlr|TRCVIIECTLR}}
0x50 0x2 0x31 0xd5
-# CHECK: mrs x16, trcvissctlr
+# CHECK: mrs x16, {{trcvissctlr|TRCVISSCTLR}}
0x48 0x3 0x31 0xd5
-# CHECK: mrs x8, trcvipcssctlr
+# CHECK: mrs x8, {{trcvipcssctlr|TRCVIPCSSCTLR}}
0x5b 0x8 0x31 0xd5
-# CHECK: mrs x27, trcvdctlr
+# CHECK: mrs x27, {{trcvdctlr|TRCVDCTLR}}
0x49 0x9 0x31 0xd5
-# CHECK: mrs x9, trcvdsacctlr
+# CHECK: mrs x9, {{trcvdsacctlr|TRCVDSACCTLR}}
0x40 0xa 0x31 0xd5
-# CHECK: mrs x0, trcvdarcctlr
+# CHECK: mrs x0, {{trcvdarcctlr|TRCVDARCCTLR}}
0x8d 0x0 0x31 0xd5
-# CHECK: mrs x13, trcseqevr0
+# CHECK: mrs x13, {{trcseqevr0|TRCSEQEVR0}}
0x8b 0x1 0x31 0xd5
-# CHECK: mrs x11, trcseqevr1
+# CHECK: mrs x11, {{trcseqevr1|TRCSEQEVR1}}
0x9a 0x2 0x31 0xd5
-# CHECK: mrs x26, trcseqevr2
+# CHECK: mrs x26, {{trcseqevr2|TRCSEQEVR2}}
0x8e 0x6 0x31 0xd5
-# CHECK: mrs x14, trcseqrstevr
+# CHECK: mrs x14, {{trcseqrstevr|TRCSEQRSTEVR}}
0x84 0x7 0x31 0xd5
-# CHECK: mrs x4, trcseqstr
+# CHECK: mrs x4, {{trcseqstr|TRCSEQSTR}}
0x91 0x8 0x31 0xd5
-# CHECK: mrs x17, trcextinselr
+# CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR}}
0xb5 0x0 0x31 0xd5
-# CHECK: mrs x21, trccntrldvr0
+# CHECK: mrs x21, {{trccntrldvr0|TRCCNTRLDVR0}}
0xaa 0x1 0x31 0xd5
-# CHECK: mrs x10, trccntrldvr1
+# CHECK: mrs x10, {{trccntrldvr1|TRCCNTRLDVR1}}
0xb4 0x2 0x31 0xd5
-# CHECK: mrs x20, trccntrldvr2
+# CHECK: mrs x20, {{trccntrldvr2|TRCCNTRLDVR2}}
0xa5 0x3 0x31 0xd5
-# CHECK: mrs x5, trccntrldvr3
+# CHECK: mrs x5, {{trccntrldvr3|TRCCNTRLDVR3}}
0xb1 0x4 0x31 0xd5
-# CHECK: mrs x17, trccntctlr0
+# CHECK: mrs x17, {{trccntctlr0|TRCCNTCTLR0}}
0xa1 0x5 0x31 0xd5
-# CHECK: mrs x1, trccntctlr1
+# CHECK: mrs x1, {{trccntctlr1|TRCCNTCTLR1}}
0xb1 0x6 0x31 0xd5
-# CHECK: mrs x17, trccntctlr2
+# CHECK: mrs x17, {{trccntctlr2|TRCCNTCTLR2}}
0xa6 0x7 0x31 0xd5
-# CHECK: mrs x6, trccntctlr3
+# CHECK: mrs x6, {{trccntctlr3|TRCCNTCTLR3}}
0xbc 0x8 0x31 0xd5
-# CHECK: mrs x28, trccntvr0
+# CHECK: mrs x28, {{trccntvr0|TRCCNTVR0}}
0xb7 0x9 0x31 0xd5
-# CHECK: mrs x23, trccntvr1
+# CHECK: mrs x23, {{trccntvr1|TRCCNTVR1}}
0xa9 0xa 0x31 0xd5
-# CHECK: mrs x9, trccntvr2
+# CHECK: mrs x9, {{trccntvr2|TRCCNTVR2}}
0xa6 0xb 0x31 0xd5
-# CHECK: mrs x6, trccntvr3
+# CHECK: mrs x6, {{trccntvr3|TRCCNTVR3}}
0xf8 0x0 0x31 0xd5
-# CHECK: mrs x24, trcimspec0
+# CHECK: mrs x24, {{trcimspec0|TRCIMSPEC0}}
0xf8 0x1 0x31 0xd5
-# CHECK: mrs x24, trcimspec1
+# CHECK: mrs x24, {{trcimspec1|TRCIMSPEC1}}
0xef 0x2 0x31 0xd5
-# CHECK: mrs x15, trcimspec2
+# CHECK: mrs x15, {{trcimspec2|TRCIMSPEC2}}
0xea 0x3 0x31 0xd5
-# CHECK: mrs x10, trcimspec3
+# CHECK: mrs x10, {{trcimspec3|TRCIMSPEC3}}
0xfd 0x4 0x31 0xd5
-# CHECK: mrs x29, trcimspec4
+# CHECK: mrs x29, {{trcimspec4|TRCIMSPEC4}}
0xf2 0x5 0x31 0xd5
-# CHECK: mrs x18, trcimspec5
+# CHECK: mrs x18, {{trcimspec5|TRCIMSPEC5}}
0xfd 0x6 0x31 0xd5
-# CHECK: mrs x29, trcimspec6
+# CHECK: mrs x29, {{trcimspec6|TRCIMSPEC6}}
0xe2 0x7 0x31 0xd5
-# CHECK: mrs x2, trcimspec7
+# CHECK: mrs x2, {{trcimspec7|TRCIMSPEC7}}
0x8 0x12 0x31 0xd5
-# CHECK: mrs x8, trcrsctlr2
+# CHECK: mrs x8, {{trcrsctlr2|TRCRSCTLR2}}
0x0 0x13 0x31 0xd5
-# CHECK: mrs x0, trcrsctlr3
+# CHECK: mrs x0, {{trcrsctlr3|TRCRSCTLR3}}
0xc 0x14 0x31 0xd5
-# CHECK: mrs x12, trcrsctlr4
+# CHECK: mrs x12, {{trcrsctlr4|TRCRSCTLR4}}
0x1a 0x15 0x31 0xd5
-# CHECK: mrs x26, trcrsctlr5
+# CHECK: mrs x26, {{trcrsctlr5|TRCRSCTLR5}}
0x1d 0x16 0x31 0xd5
-# CHECK: mrs x29, trcrsctlr6
+# CHECK: mrs x29, {{trcrsctlr6|TRCRSCTLR6}}
0x11 0x17 0x31 0xd5
-# CHECK: mrs x17, trcrsctlr7
+# CHECK: mrs x17, {{trcrsctlr7|TRCRSCTLR7}}
0x0 0x18 0x31 0xd5
-# CHECK: mrs x0, trcrsctlr8
+# CHECK: mrs x0, {{trcrsctlr8|TRCRSCTLR8}}
0x1 0x19 0x31 0xd5
-# CHECK: mrs x1, trcrsctlr9
+# CHECK: mrs x1, {{trcrsctlr9|TRCRSCTLR9}}
0x11 0x1a 0x31 0xd5
-# CHECK: mrs x17, trcrsctlr10
+# CHECK: mrs x17, {{trcrsctlr10|TRCRSCTLR10}}
0x15 0x1b 0x31 0xd5
-# CHECK: mrs x21, trcrsctlr11
+# CHECK: mrs x21, {{trcrsctlr11|TRCRSCTLR11}}
0x1 0x1c 0x31 0xd5
-# CHECK: mrs x1, trcrsctlr12
+# CHECK: mrs x1, {{trcrsctlr12|TRCRSCTLR12}}
0x8 0x1d 0x31 0xd5
-# CHECK: mrs x8, trcrsctlr13
+# CHECK: mrs x8, {{trcrsctlr13|TRCRSCTLR13}}
0x18 0x1e 0x31 0xd5
-# CHECK: mrs x24, trcrsctlr14
+# CHECK: mrs x24, {{trcrsctlr14|TRCRSCTLR14}}
0x0 0x1f 0x31 0xd5
-# CHECK: mrs x0, trcrsctlr15
+# CHECK: mrs x0, {{trcrsctlr15|TRCRSCTLR15}}
0x22 0x10 0x31 0xd5
-# CHECK: mrs x2, trcrsctlr16
+# CHECK: mrs x2, {{trcrsctlr16|TRCRSCTLR16}}
0x3d 0x11 0x31 0xd5
-# CHECK: mrs x29, trcrsctlr17
+# CHECK: mrs x29, {{trcrsctlr17|TRCRSCTLR17}}
0x36 0x12 0x31 0xd5
-# CHECK: mrs x22, trcrsctlr18
+# CHECK: mrs x22, {{trcrsctlr18|TRCRSCTLR18}}
0x26 0x13 0x31 0xd5
-# CHECK: mrs x6, trcrsctlr19
+# CHECK: mrs x6, {{trcrsctlr19|TRCRSCTLR19}}
0x3a 0x14 0x31 0xd5
-# CHECK: mrs x26, trcrsctlr20
+# CHECK: mrs x26, {{trcrsctlr20|TRCRSCTLR20}}
0x3a 0x15 0x31 0xd5
-# CHECK: mrs x26, trcrsctlr21
+# CHECK: mrs x26, {{trcrsctlr21|TRCRSCTLR21}}
0x24 0x16 0x31 0xd5
-# CHECK: mrs x4, trcrsctlr22
+# CHECK: mrs x4, {{trcrsctlr22|TRCRSCTLR22}}
0x2c 0x17 0x31 0xd5
-# CHECK: mrs x12, trcrsctlr23
+# CHECK: mrs x12, {{trcrsctlr23|TRCRSCTLR23}}
0x21 0x18 0x31 0xd5
-# CHECK: mrs x1, trcrsctlr24
+# CHECK: mrs x1, {{trcrsctlr24|TRCRSCTLR24}}
0x20 0x19 0x31 0xd5
-# CHECK: mrs x0, trcrsctlr25
+# CHECK: mrs x0, {{trcrsctlr25|TRCRSCTLR25}}
0x31 0x1a 0x31 0xd5
-# CHECK: mrs x17, trcrsctlr26
+# CHECK: mrs x17, {{trcrsctlr26|TRCRSCTLR26}}
0x28 0x1b 0x31 0xd5
-# CHECK: mrs x8, trcrsctlr27
+# CHECK: mrs x8, {{trcrsctlr27|TRCRSCTLR27}}
0x2a 0x1c 0x31 0xd5
-# CHECK: mrs x10, trcrsctlr28
+# CHECK: mrs x10, {{trcrsctlr28|TRCRSCTLR28}}
0x39 0x1d 0x31 0xd5
-# CHECK: mrs x25, trcrsctlr29
+# CHECK: mrs x25, {{trcrsctlr29|TRCRSCTLR29}}
0x2c 0x1e 0x31 0xd5
-# CHECK: mrs x12, trcrsctlr30
+# CHECK: mrs x12, {{trcrsctlr30|TRCRSCTLR30}}
0x2b 0x1f 0x31 0xd5
-# CHECK: mrs x11, trcrsctlr31
+# CHECK: mrs x11, {{trcrsctlr31|TRCRSCTLR31}}
0x52 0x10 0x31 0xd5
-# CHECK: mrs x18, trcssccr0
+# CHECK: mrs x18, {{trcssccr0|TRCSSCCR0}}
0x4c 0x11 0x31 0xd5
-# CHECK: mrs x12, trcssccr1
+# CHECK: mrs x12, {{trcssccr1|TRCSSCCR1}}
0x43 0x12 0x31 0xd5
-# CHECK: mrs x3, trcssccr2
+# CHECK: mrs x3, {{trcssccr2|TRCSSCCR2}}
0x42 0x13 0x31 0xd5
-# CHECK: mrs x2, trcssccr3
+# CHECK: mrs x2, {{trcssccr3|TRCSSCCR3}}
0x55 0x14 0x31 0xd5
-# CHECK: mrs x21, trcssccr4
+# CHECK: mrs x21, {{trcssccr4|TRCSSCCR4}}
0x4a 0x15 0x31 0xd5
-# CHECK: mrs x10, trcssccr5
+# CHECK: mrs x10, {{trcssccr5|TRCSSCCR5}}
0x56 0x16 0x31 0xd5
-# CHECK: mrs x22, trcssccr6
+# CHECK: mrs x22, {{trcssccr6|TRCSSCCR6}}
0x57 0x17 0x31 0xd5
-# CHECK: mrs x23, trcssccr7
+# CHECK: mrs x23, {{trcssccr7|TRCSSCCR7}}
0x57 0x18 0x31 0xd5
-# CHECK: mrs x23, trcsscsr0
+# CHECK: mrs x23, {{trcsscsr0|TRCSSCSR0}}
0x53 0x19 0x31 0xd5
-# CHECK: mrs x19, trcsscsr1
+# CHECK: mrs x19, {{trcsscsr1|TRCSSCSR1}}
0x59 0x1a 0x31 0xd5
-# CHECK: mrs x25, trcsscsr2
+# CHECK: mrs x25, {{trcsscsr2|TRCSSCSR2}}
0x51 0x1b 0x31 0xd5
-# CHECK: mrs x17, trcsscsr3
+# CHECK: mrs x17, {{trcsscsr3|TRCSSCSR3}}
0x53 0x1c 0x31 0xd5
-# CHECK: mrs x19, trcsscsr4
+# CHECK: mrs x19, {{trcsscsr4|TRCSSCSR4}}
0x4b 0x1d 0x31 0xd5
-# CHECK: mrs x11, trcsscsr5
+# CHECK: mrs x11, {{trcsscsr5|TRCSSCSR5}}
0x45 0x1e 0x31 0xd5
-# CHECK: mrs x5, trcsscsr6
+# CHECK: mrs x5, {{trcsscsr6|TRCSSCSR6}}
0x49 0x1f 0x31 0xd5
-# CHECK: mrs x9, trcsscsr7
+# CHECK: mrs x9, {{trcsscsr7|TRCSSCSR7}}
0x9a 0x14 0x31 0xd5
-# CHECK: mrs x26, trcpdcr
+# CHECK: mrs x26, {{trcpdcr|TRCPDCR}}
0x8 0x20 0x31 0xd5
-# CHECK: mrs x8, trcacvr0
+# CHECK: mrs x8, {{trcacvr0|TRCACVR0}}
0xf 0x22 0x31 0xd5
-# CHECK: mrs x15, trcacvr1
+# CHECK: mrs x15, {{trcacvr1|TRCACVR1}}
0x13 0x24 0x31 0xd5
-# CHECK: mrs x19, trcacvr2
+# CHECK: mrs x19, {{trcacvr2|TRCACVR2}}
0x8 0x26 0x31 0xd5
-# CHECK: mrs x8, trcacvr3
+# CHECK: mrs x8, {{trcacvr3|TRCACVR3}}
0x1c 0x28 0x31 0xd5
-# CHECK: mrs x28, trcacvr4
+# CHECK: mrs x28, {{trcacvr4|TRCACVR4}}
0x3 0x2a 0x31 0xd5
-# CHECK: mrs x3, trcacvr5
+# CHECK: mrs x3, {{trcacvr5|TRCACVR5}}
0x19 0x2c 0x31 0xd5
-# CHECK: mrs x25, trcacvr6
+# CHECK: mrs x25, {{trcacvr6|TRCACVR6}}
0x18 0x2e 0x31 0xd5
-# CHECK: mrs x24, trcacvr7
+# CHECK: mrs x24, {{trcacvr7|TRCACVR7}}
0x26 0x20 0x31 0xd5
-# CHECK: mrs x6, trcacvr8
+# CHECK: mrs x6, {{trcacvr8|TRCACVR8}}
0x23 0x22 0x31 0xd5
-# CHECK: mrs x3, trcacvr9
+# CHECK: mrs x3, {{trcacvr9|TRCACVR9}}
0x38 0x24 0x31 0xd5
-# CHECK: mrs x24, trcacvr10
+# CHECK: mrs x24, {{trcacvr10|TRCACVR10}}
0x23 0x26 0x31 0xd5
-# CHECK: mrs x3, trcacvr11
+# CHECK: mrs x3, {{trcacvr11|TRCACVR11}}
0x2c 0x28 0x31 0xd5
-# CHECK: mrs x12, trcacvr12
+# CHECK: mrs x12, {{trcacvr12|TRCACVR12}}
0x29 0x2a 0x31 0xd5
-# CHECK: mrs x9, trcacvr13
+# CHECK: mrs x9, {{trcacvr13|TRCACVR13}}
0x2e 0x2c 0x31 0xd5
-# CHECK: mrs x14, trcacvr14
+# CHECK: mrs x14, {{trcacvr14|TRCACVR14}}
0x23 0x2e 0x31 0xd5
-# CHECK: mrs x3, trcacvr15
+# CHECK: mrs x3, {{trcacvr15|TRCACVR15}}
0x55 0x20 0x31 0xd5
-# CHECK: mrs x21, trcacatr0
+# CHECK: mrs x21, {{trcacatr0|TRCACATR0}}
0x5a 0x22 0x31 0xd5
-# CHECK: mrs x26, trcacatr1
+# CHECK: mrs x26, {{trcacatr1|TRCACATR1}}
0x48 0x24 0x31 0xd5
-# CHECK: mrs x8, trcacatr2
+# CHECK: mrs x8, {{trcacatr2|TRCACATR2}}
0x56 0x26 0x31 0xd5
-# CHECK: mrs x22, trcacatr3
+# CHECK: mrs x22, {{trcacatr3|TRCACATR3}}
0x46 0x28 0x31 0xd5
-# CHECK: mrs x6, trcacatr4
+# CHECK: mrs x6, {{trcacatr4|TRCACATR4}}
0x5d 0x2a 0x31 0xd5
-# CHECK: mrs x29, trcacatr5
+# CHECK: mrs x29, {{trcacatr5|TRCACATR5}}
0x45 0x2c 0x31 0xd5
-# CHECK: mrs x5, trcacatr6
+# CHECK: mrs x5, {{trcacatr6|TRCACATR6}}
0x52 0x2e 0x31 0xd5
-# CHECK: mrs x18, trcacatr7
+# CHECK: mrs x18, {{trcacatr7|TRCACATR7}}
0x62 0x20 0x31 0xd5
-# CHECK: mrs x2, trcacatr8
+# CHECK: mrs x2, {{trcacatr8|TRCACATR8}}
0x73 0x22 0x31 0xd5
-# CHECK: mrs x19, trcacatr9
+# CHECK: mrs x19, {{trcacatr9|TRCACATR9}}
0x6d 0x24 0x31 0xd5
-# CHECK: mrs x13, trcacatr10
+# CHECK: mrs x13, {{trcacatr10|TRCACATR10}}
0x79 0x26 0x31 0xd5
-# CHECK: mrs x25, trcacatr11
+# CHECK: mrs x25, {{trcacatr11|TRCACATR11}}
0x72 0x28 0x31 0xd5
-# CHECK: mrs x18, trcacatr12
+# CHECK: mrs x18, {{trcacatr12|TRCACATR12}}
0x7d 0x2a 0x31 0xd5
-# CHECK: mrs x29, trcacatr13
+# CHECK: mrs x29, {{trcacatr13|TRCACATR13}}
0x69 0x2c 0x31 0xd5
-# CHECK: mrs x9, trcacatr14
+# CHECK: mrs x9, {{trcacatr14|TRCACATR14}}
0x72 0x2e 0x31 0xd5
-# CHECK: mrs x18, trcacatr15
+# CHECK: mrs x18, {{trcacatr15|TRCACATR15}}
0x9d 0x20 0x31 0xd5
-# CHECK: mrs x29, trcdvcvr0
+# CHECK: mrs x29, {{trcdvcvr0|TRCDVCVR0}}
0x8f 0x24 0x31 0xd5
-# CHECK: mrs x15, trcdvcvr1
+# CHECK: mrs x15, {{trcdvcvr1|TRCDVCVR1}}
0x8f 0x28 0x31 0xd5
-# CHECK: mrs x15, trcdvcvr2
+# CHECK: mrs x15, {{trcdvcvr2|TRCDVCVR2}}
0x8f 0x2c 0x31 0xd5
-# CHECK: mrs x15, trcdvcvr3
+# CHECK: mrs x15, {{trcdvcvr3|TRCDVCVR3}}
0xb3 0x20 0x31 0xd5
-# CHECK: mrs x19, trcdvcvr4
+# CHECK: mrs x19, {{trcdvcvr4|TRCDVCVR4}}
0xb6 0x24 0x31 0xd5
-# CHECK: mrs x22, trcdvcvr5
+# CHECK: mrs x22, {{trcdvcvr5|TRCDVCVR5}}
0xbb 0x28 0x31 0xd5
-# CHECK: mrs x27, trcdvcvr6
+# CHECK: mrs x27, {{trcdvcvr6|TRCDVCVR6}}
0xa1 0x2c 0x31 0xd5
-# CHECK: mrs x1, trcdvcvr7
+# CHECK: mrs x1, {{trcdvcvr7|TRCDVCVR7}}
0xdd 0x20 0x31 0xd5
-# CHECK: mrs x29, trcdvcmr0
+# CHECK: mrs x29, {{trcdvcmr0|TRCDVCMR0}}
0xc9 0x24 0x31 0xd5
-# CHECK: mrs x9, trcdvcmr1
+# CHECK: mrs x9, {{trcdvcmr1|TRCDVCMR1}}
0xc1 0x28 0x31 0xd5
-# CHECK: mrs x1, trcdvcmr2
+# CHECK: mrs x1, {{trcdvcmr2|TRCDVCMR2}}
0xc2 0x2c 0x31 0xd5
-# CHECK: mrs x2, trcdvcmr3
+# CHECK: mrs x2, {{trcdvcmr3|TRCDVCMR3}}
0xe5 0x20 0x31 0xd5
-# CHECK: mrs x5, trcdvcmr4
+# CHECK: mrs x5, {{trcdvcmr4|TRCDVCMR4}}
0xf5 0x24 0x31 0xd5
-# CHECK: mrs x21, trcdvcmr5
+# CHECK: mrs x21, {{trcdvcmr5|TRCDVCMR5}}
0xe5 0x28 0x31 0xd5
-# CHECK: mrs x5, trcdvcmr6
+# CHECK: mrs x5, {{trcdvcmr6|TRCDVCMR6}}
0xe1 0x2c 0x31 0xd5
-# CHECK: mrs x1, trcdvcmr7
+# CHECK: mrs x1, {{trcdvcmr7|TRCDVCMR7}}
0x15 0x30 0x31 0xd5
-# CHECK: mrs x21, trccidcvr0
+# CHECK: mrs x21, {{trccidcvr0|TRCCIDCVR0}}
0x18 0x32 0x31 0xd5
-# CHECK: mrs x24, trccidcvr1
+# CHECK: mrs x24, {{trccidcvr1|TRCCIDCVR1}}
0x18 0x34 0x31 0xd5
-# CHECK: mrs x24, trccidcvr2
+# CHECK: mrs x24, {{trccidcvr2|TRCCIDCVR2}}
0xc 0x36 0x31 0xd5
-# CHECK: mrs x12, trccidcvr3
+# CHECK: mrs x12, {{trccidcvr3|TRCCIDCVR3}}
0xa 0x38 0x31 0xd5
-# CHECK: mrs x10, trccidcvr4
+# CHECK: mrs x10, {{trccidcvr4|TRCCIDCVR4}}
0x9 0x3a 0x31 0xd5
-# CHECK: mrs x9, trccidcvr5
+# CHECK: mrs x9, {{trccidcvr5|TRCCIDCVR5}}
0x6 0x3c 0x31 0xd5
-# CHECK: mrs x6, trccidcvr6
+# CHECK: mrs x6, {{trccidcvr6|TRCCIDCVR6}}
0x14 0x3e 0x31 0xd5
-# CHECK: mrs x20, trccidcvr7
+# CHECK: mrs x20, {{trccidcvr7|TRCCIDCVR7}}
0x34 0x30 0x31 0xd5
-# CHECK: mrs x20, trcvmidcvr0
+# CHECK: mrs x20, {{trcvmidcvr0|TRCVMIDCVR0}}
0x34 0x32 0x31 0xd5
-# CHECK: mrs x20, trcvmidcvr1
+# CHECK: mrs x20, {{trcvmidcvr1|TRCVMIDCVR1}}
0x3a 0x34 0x31 0xd5
-# CHECK: mrs x26, trcvmidcvr2
+# CHECK: mrs x26, {{trcvmidcvr2|TRCVMIDCVR2}}
0x21 0x36 0x31 0xd5
-# CHECK: mrs x1, trcvmidcvr3
+# CHECK: mrs x1, {{trcvmidcvr3|TRCVMIDCVR3}}
0x2e 0x38 0x31 0xd5
-# CHECK: mrs x14, trcvmidcvr4
+# CHECK: mrs x14, {{trcvmidcvr4|TRCVMIDCVR4}}
0x3b 0x3a 0x31 0xd5
-# CHECK: mrs x27, trcvmidcvr5
+# CHECK: mrs x27, {{trcvmidcvr5|TRCVMIDCVR5}}
0x3d 0x3c 0x31 0xd5
-# CHECK: mrs x29, trcvmidcvr6
+# CHECK: mrs x29, {{trcvmidcvr6|TRCVMIDCVR6}}
0x31 0x3e 0x31 0xd5
-# CHECK: mrs x17, trcvmidcvr7
+# CHECK: mrs x17, {{trcvmidcvr7|TRCVMIDCVR7}}
0x4a 0x30 0x31 0xd5
-# CHECK: mrs x10, trccidcctlr0
+# CHECK: mrs x10, {{trccidcctlr0|TRCCIDCCTLR0}}
0x44 0x31 0x31 0xd5
-# CHECK: mrs x4, trccidcctlr1
+# CHECK: mrs x4, {{trccidcctlr1|TRCCIDCCTLR1}}
0x49 0x32 0x31 0xd5
-# CHECK: mrs x9, trcvmidcctlr0
+# CHECK: mrs x9, {{trcvmidcctlr0|TRCVMIDCCTLR0}}
0x4b 0x33 0x31 0xd5
-# CHECK: mrs x11, trcvmidcctlr1
+# CHECK: mrs x11, {{trcvmidcctlr1|TRCVMIDCCTLR1}}
0x96 0x70 0x31 0xd5
-# CHECK: mrs x22, trcitctrl
+# CHECK: mrs x22, {{trcitctrl|TRCITCTRL}}
0xd7 0x78 0x31 0xd5
-# CHECK: mrs x23, trcclaimset
+# CHECK: mrs x23, {{trcclaimset|TRCCLAIMSET}}
0xce 0x79 0x31 0xd5
-# CHECK: mrs x14, trcclaimclr
+# CHECK: mrs x14, {{trcclaimclr|TRCCLAIMCLR}}
0x9c 0x10 0x11 0xd5
-# CHECK: msr trcoslar, x28
+# CHECK: msr {{trcoslar|TRCOSLAR}}, x28
0xce 0x7c 0x11 0xd5
-# CHECK: msr trclar, x14
+# CHECK: msr {{trclar|TRCLAR}}, x14
0xa 0x1 0x11 0xd5
-# CHECK: msr trcprgctlr, x10
+# CHECK: msr {{trcprgctlr|TRCPRGCTLR}}, x10
0x1b 0x2 0x11 0xd5
-# CHECK: msr trcprocselr, x27
+# CHECK: msr {{trcprocselr|TRCPROCSELR}}, x27
0x18 0x4 0x11 0xd5
-# CHECK: msr trcconfigr, x24
+# CHECK: msr {{trcconfigr|TRCCONFIGR}}, x24
0x8 0x6 0x11 0xd5
-# CHECK: msr trcauxctlr, x8
+# CHECK: msr {{trcauxctlr|TRCAUXCTLR}}, x8
0x10 0x8 0x11 0xd5
-# CHECK: msr trceventctl0r, x16
+# CHECK: msr {{trceventctl0r|TRCEVENTCTL0R}}, x16
0x1b 0x9 0x11 0xd5
-# CHECK: msr trceventctl1r, x27
+# CHECK: msr {{trceventctl1r|TRCEVENTCTL1R}}, x27
0x1a 0xb 0x11 0xd5
-# CHECK: msr trcstallctlr, x26
+# CHECK: msr {{trcstallctlr|TRCSTALLCTLR}}, x26
0x0 0xc 0x11 0xd5
-# CHECK: msr trctsctlr, x0
+# CHECK: msr {{trctsctlr|TRCTSCTLR}}, x0
0xe 0xd 0x11 0xd5
-# CHECK: msr trcsyncpr, x14
+# CHECK: msr {{trcsyncpr|TRCSYNCPR}}, x14
0x8 0xe 0x11 0xd5
-# CHECK: msr trcccctlr, x8
+# CHECK: msr {{trcccctlr|TRCCCCTLR}}, x8
0x6 0xf 0x11 0xd5
-# CHECK: msr trcbbctlr, x6
+# CHECK: msr {{trcbbctlr|TRCBBCTLR}}, x6
0x37 0x0 0x11 0xd5
-# CHECK: msr trctraceidr, x23
+# CHECK: msr {{trctraceidr|TRCTRACEIDR}}, x23
0x25 0x1 0x11 0xd5
-# CHECK: msr trcqctlr, x5
+# CHECK: msr {{trcqctlr|TRCQCTLR}}, x5
0x40 0x0 0x11 0xd5
-# CHECK: msr trcvictlr, x0
+# CHECK: msr {{trcvictlr|TRCVICTLR}}, x0
0x40 0x1 0x11 0xd5
-# CHECK: msr trcviiectlr, x0
+# CHECK: msr {{trcviiectlr|TRCVIIECTLR}}, x0
0x41 0x2 0x11 0xd5
-# CHECK: msr trcvissctlr, x1
+# CHECK: msr {{trcvissctlr|TRCVISSCTLR}}, x1
0x40 0x3 0x11 0xd5
-# CHECK: msr trcvipcssctlr, x0
+# CHECK: msr {{trcvipcssctlr|TRCVIPCSSCTLR}}, x0
0x47 0x8 0x11 0xd5
-# CHECK: msr trcvdctlr, x7
+# CHECK: msr {{trcvdctlr|TRCVDCTLR}}, x7
0x52 0x9 0x11 0xd5
-# CHECK: msr trcvdsacctlr, x18
+# CHECK: msr {{trcvdsacctlr|TRCVDSACCTLR}}, x18
0x58 0xa 0x11 0xd5
-# CHECK: msr trcvdarcctlr, x24
+# CHECK: msr {{trcvdarcctlr|TRCVDARCCTLR}}, x24
0x9c 0x0 0x11 0xd5
-# CHECK: msr trcseqevr0, x28
+# CHECK: msr {{trcseqevr0|TRCSEQEVR0}}, x28
0x95 0x1 0x11 0xd5
-# CHECK: msr trcseqevr1, x21
+# CHECK: msr {{trcseqevr1|TRCSEQEVR1}}, x21
0x90 0x2 0x11 0xd5
-# CHECK: msr trcseqevr2, x16
+# CHECK: msr {{trcseqevr2|TRCSEQEVR2}}, x16
0x90 0x6 0x11 0xd5
-# CHECK: msr trcseqrstevr, x16
+# CHECK: msr {{trcseqrstevr|TRCSEQRSTEVR}}, x16
0x99 0x7 0x11 0xd5
-# CHECK: msr trcseqstr, x25
+# CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25
0x9d 0x8 0x11 0xd5
-# CHECK: msr trcextinselr, x29
+# CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29
0xb4 0x0 0x11 0xd5
-# CHECK: msr trccntrldvr0, x20
+# CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20
0xb4 0x1 0x11 0xd5
-# CHECK: msr trccntrldvr1, x20
+# CHECK: msr {{trccntrldvr1|TRCCNTRLDVR1}}, x20
0xb6 0x2 0x11 0xd5
-# CHECK: msr trccntrldvr2, x22
+# CHECK: msr {{trccntrldvr2|TRCCNTRLDVR2}}, x22
0xac 0x3 0x11 0xd5
-# CHECK: msr trccntrldvr3, x12
+# CHECK: msr {{trccntrldvr3|TRCCNTRLDVR3}}, x12
0xb4 0x4 0x11 0xd5
-# CHECK: msr trccntctlr0, x20
+# CHECK: msr {{trccntctlr0|TRCCNTCTLR0}}, x20
0xa4 0x5 0x11 0xd5
-# CHECK: msr trccntctlr1, x4
+# CHECK: msr {{trccntctlr1|TRCCNTCTLR1}}, x4
0xa8 0x6 0x11 0xd5
-# CHECK: msr trccntctlr2, x8
+# CHECK: msr {{trccntctlr2|TRCCNTCTLR2}}, x8
0xb0 0x7 0x11 0xd5
-# CHECK: msr trccntctlr3, x16
+# CHECK: msr {{trccntctlr3|TRCCNTCTLR3}}, x16
0xa5 0x8 0x11 0xd5
-# CHECK: msr trccntvr0, x5
+# CHECK: msr {{trccntvr0|TRCCNTVR0}}, x5
0xbb 0x9 0x11 0xd5
-# CHECK: msr trccntvr1, x27
+# CHECK: msr {{trccntvr1|TRCCNTVR1}}, x27
0xb5 0xa 0x11 0xd5
-# CHECK: msr trccntvr2, x21
+# CHECK: msr {{trccntvr2|TRCCNTVR2}}, x21
0xa8 0xb 0x11 0xd5
-# CHECK: msr trccntvr3, x8
+# CHECK: msr {{trccntvr3|TRCCNTVR3}}, x8
0xe6 0x0 0x11 0xd5
-# CHECK: msr trcimspec0, x6
+# CHECK: msr {{trcimspec0|TRCIMSPEC0}}, x6
0xfb 0x1 0x11 0xd5
-# CHECK: msr trcimspec1, x27
+# CHECK: msr {{trcimspec1|TRCIMSPEC1}}, x27
0xf7 0x2 0x11 0xd5
-# CHECK: msr trcimspec2, x23
+# CHECK: msr {{trcimspec2|TRCIMSPEC2}}, x23
0xef 0x3 0x11 0xd5
-# CHECK: msr trcimspec3, x15
+# CHECK: msr {{trcimspec3|TRCIMSPEC3}}, x15
0xed 0x4 0x11 0xd5
-# CHECK: msr trcimspec4, x13
+# CHECK: msr {{trcimspec4|TRCIMSPEC4}}, x13
0xf9 0x5 0x11 0xd5
-# CHECK: msr trcimspec5, x25
+# CHECK: msr {{trcimspec5|TRCIMSPEC5}}, x25
0xf3 0x6 0x11 0xd5
-# CHECK: msr trcimspec6, x19
+# CHECK: msr {{trcimspec6|TRCIMSPEC6}}, x19
0xfb 0x7 0x11 0xd5
-# CHECK: msr trcimspec7, x27
+# CHECK: msr {{trcimspec7|TRCIMSPEC7}}, x27
0x4 0x12 0x11 0xd5
-# CHECK: msr trcrsctlr2, x4
+# CHECK: msr {{trcrsctlr2|TRCRSCTLR2}}, x4
0x0 0x13 0x11 0xd5
-# CHECK: msr trcrsctlr3, x0
+# CHECK: msr {{trcrsctlr3|TRCRSCTLR3}}, x0
0x15 0x14 0x11 0xd5
-# CHECK: msr trcrsctlr4, x21
+# CHECK: msr {{trcrsctlr4|TRCRSCTLR4}}, x21
0x8 0x15 0x11 0xd5
-# CHECK: msr trcrsctlr5, x8
+# CHECK: msr {{trcrsctlr5|TRCRSCTLR5}}, x8
0x14 0x16 0x11 0xd5
-# CHECK: msr trcrsctlr6, x20
+# CHECK: msr {{trcrsctlr6|TRCRSCTLR6}}, x20
0xb 0x17 0x11 0xd5
-# CHECK: msr trcrsctlr7, x11
+# CHECK: msr {{trcrsctlr7|TRCRSCTLR7}}, x11
0x12 0x18 0x11 0xd5
-# CHECK: msr trcrsctlr8, x18
+# CHECK: msr {{trcrsctlr8|TRCRSCTLR8}}, x18
0x18 0x19 0x11 0xd5
-# CHECK: msr trcrsctlr9, x24
+# CHECK: msr {{trcrsctlr9|TRCRSCTLR9}}, x24
0xf 0x1a 0x11 0xd5
-# CHECK: msr trcrsctlr10, x15
+# CHECK: msr {{trcrsctlr10|TRCRSCTLR10}}, x15
0x15 0x1b 0x11 0xd5
-# CHECK: msr trcrsctlr11, x21
+# CHECK: msr {{trcrsctlr11|TRCRSCTLR11}}, x21
0x4 0x1c 0x11 0xd5
-# CHECK: msr trcrsctlr12, x4
+# CHECK: msr {{trcrsctlr12|TRCRSCTLR12}}, x4
0x1c 0x1d 0x11 0xd5
-# CHECK: msr trcrsctlr13, x28
+# CHECK: msr {{trcrsctlr13|TRCRSCTLR13}}, x28
0x3 0x1e 0x11 0xd5
-# CHECK: msr trcrsctlr14, x3
+# CHECK: msr {{trcrsctlr14|TRCRSCTLR14}}, x3
0x14 0x1f 0x11 0xd5
-# CHECK: msr trcrsctlr15, x20
+# CHECK: msr {{trcrsctlr15|TRCRSCTLR15}}, x20
0x2c 0x10 0x11 0xd5
-# CHECK: msr trcrsctlr16, x12
+# CHECK: msr {{trcrsctlr16|TRCRSCTLR16}}, x12
0x31 0x11 0x11 0xd5
-# CHECK: msr trcrsctlr17, x17
+# CHECK: msr {{trcrsctlr17|TRCRSCTLR17}}, x17
0x2a 0x12 0x11 0xd5
-# CHECK: msr trcrsctlr18, x10
+# CHECK: msr {{trcrsctlr18|TRCRSCTLR18}}, x10
0x2b 0x13 0x11 0xd5
-# CHECK: msr trcrsctlr19, x11
+# CHECK: msr {{trcrsctlr19|TRCRSCTLR19}}, x11
0x23 0x14 0x11 0xd5
-# CHECK: msr trcrsctlr20, x3
+# CHECK: msr {{trcrsctlr20|TRCRSCTLR20}}, x3
0x32 0x15 0x11 0xd5
-# CHECK: msr trcrsctlr21, x18
+# CHECK: msr {{trcrsctlr21|TRCRSCTLR21}}, x18
0x3a 0x16 0x11 0xd5
-# CHECK: msr trcrsctlr22, x26
+# CHECK: msr {{trcrsctlr22|TRCRSCTLR22}}, x26
0x25 0x17 0x11 0xd5
-# CHECK: msr trcrsctlr23, x5
+# CHECK: msr {{trcrsctlr23|TRCRSCTLR23}}, x5
0x39 0x18 0x11 0xd5
-# CHECK: msr trcrsctlr24, x25
+# CHECK: msr {{trcrsctlr24|TRCRSCTLR24}}, x25
0x25 0x19 0x11 0xd5
-# CHECK: msr trcrsctlr25, x5
+# CHECK: msr {{trcrsctlr25|TRCRSCTLR25}}, x5
0x24 0x1a 0x11 0xd5
-# CHECK: msr trcrsctlr26, x4
+# CHECK: msr {{trcrsctlr26|TRCRSCTLR26}}, x4
0x34 0x1b 0x11 0xd5
-# CHECK: msr trcrsctlr27, x20
+# CHECK: msr {{trcrsctlr27|TRCRSCTLR27}}, x20
0x25 0x1c 0x11 0xd5
-# CHECK: msr trcrsctlr28, x5
+# CHECK: msr {{trcrsctlr28|TRCRSCTLR28}}, x5
0x2a 0x1d 0x11 0xd5
-# CHECK: msr trcrsctlr29, x10
+# CHECK: msr {{trcrsctlr29|TRCRSCTLR29}}, x10
0x38 0x1e 0x11 0xd5
-# CHECK: msr trcrsctlr30, x24
+# CHECK: msr {{trcrsctlr30|TRCRSCTLR30}}, x24
0x34 0x1f 0x11 0xd5
-# CHECK: msr trcrsctlr31, x20
+# CHECK: msr {{trcrsctlr31|TRCRSCTLR31}}, x20
0x57 0x10 0x11 0xd5
-# CHECK: msr trcssccr0, x23
+# CHECK: msr {{trcssccr0|TRCSSCCR0}}, x23
0x5b 0x11 0x11 0xd5
-# CHECK: msr trcssccr1, x27
+# CHECK: msr {{trcssccr1|TRCSSCCR1}}, x27
0x5b 0x12 0x11 0xd5
-# CHECK: msr trcssccr2, x27
+# CHECK: msr {{trcssccr2|TRCSSCCR2}}, x27
0x46 0x13 0x11 0xd5
-# CHECK: msr trcssccr3, x6
+# CHECK: msr {{trcssccr3|TRCSSCCR3}}, x6
0x43 0x14 0x11 0xd5
-# CHECK: msr trcssccr4, x3
+# CHECK: msr {{trcssccr4|TRCSSCCR4}}, x3
0x4c 0x15 0x11 0xd5
-# CHECK: msr trcssccr5, x12
+# CHECK: msr {{trcssccr5|TRCSSCCR5}}, x12
0x47 0x16 0x11 0xd5
-# CHECK: msr trcssccr6, x7
+# CHECK: msr {{trcssccr6|TRCSSCCR6}}, x7
0x46 0x17 0x11 0xd5
-# CHECK: msr trcssccr7, x6
+# CHECK: msr {{trcssccr7|TRCSSCCR7}}, x6
0x54 0x18 0x11 0xd5
-# CHECK: msr trcsscsr0, x20
+# CHECK: msr {{trcsscsr0|TRCSSCSR0}}, x20
0x51 0x19 0x11 0xd5
-# CHECK: msr trcsscsr1, x17
+# CHECK: msr {{trcsscsr1|TRCSSCSR1}}, x17
0x4b 0x1a 0x11 0xd5
-# CHECK: msr trcsscsr2, x11
+# CHECK: msr {{trcsscsr2|TRCSSCSR2}}, x11
0x44 0x1b 0x11 0xd5
-# CHECK: msr trcsscsr3, x4
+# CHECK: msr {{trcsscsr3|TRCSSCSR3}}, x4
0x4e 0x1c 0x11 0xd5
-# CHECK: msr trcsscsr4, x14
+# CHECK: msr {{trcsscsr4|TRCSSCSR4}}, x14
0x56 0x1d 0x11 0xd5
-# CHECK: msr trcsscsr5, x22
+# CHECK: msr {{trcsscsr5|TRCSSCSR5}}, x22
0x43 0x1e 0x11 0xd5
-# CHECK: msr trcsscsr6, x3
+# CHECK: msr {{trcsscsr6|TRCSSCSR6}}, x3
0x4b 0x1f 0x11 0xd5
-# CHECK: msr trcsscsr7, x11
+# CHECK: msr {{trcsscsr7|TRCSSCSR7}}, x11
0x83 0x14 0x11 0xd5
-# CHECK: msr trcpdcr, x3
+# CHECK: msr {{trcpdcr|TRCPDCR}}, x3
0x6 0x20 0x11 0xd5
-# CHECK: msr trcacvr0, x6
+# CHECK: msr {{trcacvr0|TRCACVR0}}, x6
0x14 0x22 0x11 0xd5
-# CHECK: msr trcacvr1, x20
+# CHECK: msr {{trcacvr1|TRCACVR1}}, x20
0x19 0x24 0x11 0xd5
-# CHECK: msr trcacvr2, x25
+# CHECK: msr {{trcacvr2|TRCACVR2}}, x25
0x1 0x26 0x11 0xd5
-# CHECK: msr trcacvr3, x1
+# CHECK: msr {{trcacvr3|TRCACVR3}}, x1
0x1c 0x28 0x11 0xd5
-# CHECK: msr trcacvr4, x28
+# CHECK: msr {{trcacvr4|TRCACVR4}}, x28
0xf 0x2a 0x11 0xd5
-# CHECK: msr trcacvr5, x15
+# CHECK: msr {{trcacvr5|TRCACVR5}}, x15
0x19 0x2c 0x11 0xd5
-# CHECK: msr trcacvr6, x25
+# CHECK: msr {{trcacvr6|TRCACVR6}}, x25
0xc 0x2e 0x11 0xd5
-# CHECK: msr trcacvr7, x12
+# CHECK: msr {{trcacvr7|TRCACVR7}}, x12
0x25 0x20 0x11 0xd5
-# CHECK: msr trcacvr8, x5
+# CHECK: msr {{trcacvr8|TRCACVR8}}, x5
0x39 0x22 0x11 0xd5
-# CHECK: msr trcacvr9, x25
+# CHECK: msr {{trcacvr9|TRCACVR9}}, x25
0x2d 0x24 0x11 0xd5
-# CHECK: msr trcacvr10, x13
+# CHECK: msr {{trcacvr10|TRCACVR10}}, x13
0x2a 0x26 0x11 0xd5
-# CHECK: msr trcacvr11, x10
+# CHECK: msr {{trcacvr11|TRCACVR11}}, x10
0x33 0x28 0x11 0xd5
-# CHECK: msr trcacvr12, x19
+# CHECK: msr {{trcacvr12|TRCACVR12}}, x19
0x2a 0x2a 0x11 0xd5
-# CHECK: msr trcacvr13, x10
+# CHECK: msr {{trcacvr13|TRCACVR13}}, x10
0x33 0x2c 0x11 0xd5
-# CHECK: msr trcacvr14, x19
+# CHECK: msr {{trcacvr14|TRCACVR14}}, x19
0x22 0x2e 0x11 0xd5
-# CHECK: msr trcacvr15, x2
+# CHECK: msr {{trcacvr15|TRCACVR15}}, x2
0x4f 0x20 0x11 0xd5
-# CHECK: msr trcacatr0, x15
+# CHECK: msr {{trcacatr0|TRCACATR0}}, x15
0x4d 0x22 0x11 0xd5
-# CHECK: msr trcacatr1, x13
+# CHECK: msr {{trcacatr1|TRCACATR1}}, x13
0x48 0x24 0x11 0xd5
-# CHECK: msr trcacatr2, x8
+# CHECK: msr {{trcacatr2|TRCACATR2}}, x8
0x41 0x26 0x11 0xd5
-# CHECK: msr trcacatr3, x1
+# CHECK: msr {{trcacatr3|TRCACATR3}}, x1
0x4b 0x28 0x11 0xd5
-# CHECK: msr trcacatr4, x11
+# CHECK: msr {{trcacatr4|TRCACATR4}}, x11
0x48 0x2a 0x11 0xd5
-# CHECK: msr trcacatr5, x8
+# CHECK: msr {{trcacatr5|TRCACATR5}}, x8
0x58 0x2c 0x11 0xd5
-# CHECK: msr trcacatr6, x24
+# CHECK: msr {{trcacatr6|TRCACATR6}}, x24
0x46 0x2e 0x11 0xd5
-# CHECK: msr trcacatr7, x6
+# CHECK: msr {{trcacatr7|TRCACATR7}}, x6
0x77 0x20 0x11 0xd5
-# CHECK: msr trcacatr8, x23
+# CHECK: msr {{trcacatr8|TRCACATR8}}, x23
0x65 0x22 0x11 0xd5
-# CHECK: msr trcacatr9, x5
+# CHECK: msr {{trcacatr9|TRCACATR9}}, x5
0x6b 0x24 0x11 0xd5
-# CHECK: msr trcacatr10, x11
+# CHECK: msr {{trcacatr10|TRCACATR10}}, x11
0x6b 0x26 0x11 0xd5
-# CHECK: msr trcacatr11, x11
+# CHECK: msr {{trcacatr11|TRCACATR11}}, x11
0x63 0x28 0x11 0xd5
-# CHECK: msr trcacatr12, x3
+# CHECK: msr {{trcacatr12|TRCACATR12}}, x3
0x7c 0x2a 0x11 0xd5
-# CHECK: msr trcacatr13, x28
+# CHECK: msr {{trcacatr13|TRCACATR13}}, x28
0x79 0x2c 0x11 0xd5
-# CHECK: msr trcacatr14, x25
+# CHECK: msr {{trcacatr14|TRCACATR14}}, x25
0x64 0x2e 0x11 0xd5
-# CHECK: msr trcacatr15, x4
+# CHECK: msr {{trcacatr15|TRCACATR15}}, x4
0x86 0x20 0x11 0xd5
-# CHECK: msr trcdvcvr0, x6
+# CHECK: msr {{trcdvcvr0|TRCDVCVR0}}, x6
0x83 0x24 0x11 0xd5
-# CHECK: msr trcdvcvr1, x3
+# CHECK: msr {{trcdvcvr1|TRCDVCVR1}}, x3
0x85 0x28 0x11 0xd5
-# CHECK: msr trcdvcvr2, x5
+# CHECK: msr {{trcdvcvr2|TRCDVCVR2}}, x5
0x8b 0x2c 0x11 0xd5
-# CHECK: msr trcdvcvr3, x11
+# CHECK: msr {{trcdvcvr3|TRCDVCVR3}}, x11
0xa9 0x20 0x11 0xd5
-# CHECK: msr trcdvcvr4, x9
+# CHECK: msr {{trcdvcvr4|TRCDVCVR4}}, x9
0xae 0x24 0x11 0xd5
-# CHECK: msr trcdvcvr5, x14
+# CHECK: msr {{trcdvcvr5|TRCDVCVR5}}, x14
0xaa 0x28 0x11 0xd5
-# CHECK: msr trcdvcvr6, x10
+# CHECK: msr {{trcdvcvr6|TRCDVCVR6}}, x10
0xac 0x2c 0x11 0xd5
-# CHECK: msr trcdvcvr7, x12
+# CHECK: msr {{trcdvcvr7|TRCDVCVR7}}, x12
0xc8 0x20 0x11 0xd5
-# CHECK: msr trcdvcmr0, x8
+# CHECK: msr {{trcdvcmr0|TRCDVCMR0}}, x8
0xc8 0x24 0x11 0xd5
-# CHECK: msr trcdvcmr1, x8
+# CHECK: msr {{trcdvcmr1|TRCDVCMR1}}, x8
0xd6 0x28 0x11 0xd5
-# CHECK: msr trcdvcmr2, x22
+# CHECK: msr {{trcdvcmr2|TRCDVCMR2}}, x22
0xd6 0x2c 0x11 0xd5
-# CHECK: msr trcdvcmr3, x22
+# CHECK: msr {{trcdvcmr3|TRCDVCMR3}}, x22
0xe5 0x20 0x11 0xd5
-# CHECK: msr trcdvcmr4, x5
+# CHECK: msr {{trcdvcmr4|TRCDVCMR4}}, x5
0xf0 0x24 0x11 0xd5
-# CHECK: msr trcdvcmr5, x16
+# CHECK: msr {{trcdvcmr5|TRCDVCMR5}}, x16
0xfb 0x28 0x11 0xd5
-# CHECK: msr trcdvcmr6, x27
+# CHECK: msr {{trcdvcmr6|TRCDVCMR6}}, x27
0xf5 0x2c 0x11 0xd5
-# CHECK: msr trcdvcmr7, x21
+# CHECK: msr {{trcdvcmr7|TRCDVCMR7}}, x21
0x8 0x30 0x11 0xd5
-# CHECK: msr trccidcvr0, x8
+# CHECK: msr {{trccidcvr0|TRCCIDCVR0}}, x8
0x6 0x32 0x11 0xd5
-# CHECK: msr trccidcvr1, x6
+# CHECK: msr {{trccidcvr1|TRCCIDCVR1}}, x6
0x9 0x34 0x11 0xd5
-# CHECK: msr trccidcvr2, x9
+# CHECK: msr {{trccidcvr2|TRCCIDCVR2}}, x9
0x8 0x36 0x11 0xd5
-# CHECK: msr trccidcvr3, x8
+# CHECK: msr {{trccidcvr3|TRCCIDCVR3}}, x8
0x3 0x38 0x11 0xd5
-# CHECK: msr trccidcvr4, x3
+# CHECK: msr {{trccidcvr4|TRCCIDCVR4}}, x3
0x15 0x3a 0x11 0xd5
-# CHECK: msr trccidcvr5, x21
+# CHECK: msr {{trccidcvr5|TRCCIDCVR5}}, x21
0xc 0x3c 0x11 0xd5
-# CHECK: msr trccidcvr6, x12
+# CHECK: msr {{trccidcvr6|TRCCIDCVR6}}, x12
0x7 0x3e 0x11 0xd5
-# CHECK: msr trccidcvr7, x7
+# CHECK: msr {{trccidcvr7|TRCCIDCVR7}}, x7
0x24 0x30 0x11 0xd5
-# CHECK: msr trcvmidcvr0, x4
+# CHECK: msr {{trcvmidcvr0|TRCVMIDCVR0}}, x4
0x23 0x32 0x11 0xd5
-# CHECK: msr trcvmidcvr1, x3
+# CHECK: msr {{trcvmidcvr1|TRCVMIDCVR1}}, x3
0x29 0x34 0x11 0xd5
-# CHECK: msr trcvmidcvr2, x9
+# CHECK: msr {{trcvmidcvr2|TRCVMIDCVR2}}, x9
0x31 0x36 0x11 0xd5
-# CHECK: msr trcvmidcvr3, x17
+# CHECK: msr {{trcvmidcvr3|TRCVMIDCVR3}}, x17
0x2e 0x38 0x11 0xd5
-# CHECK: msr trcvmidcvr4, x14
+# CHECK: msr {{trcvmidcvr4|TRCVMIDCVR4}}, x14
0x2c 0x3a 0x11 0xd5
-# CHECK: msr trcvmidcvr5, x12
+# CHECK: msr {{trcvmidcvr5|TRCVMIDCVR5}}, x12
0x2a 0x3c 0x11 0xd5
-# CHECK: msr trcvmidcvr6, x10
+# CHECK: msr {{trcvmidcvr6|TRCVMIDCVR6}}, x10
0x23 0x3e 0x11 0xd5
-# CHECK: msr trcvmidcvr7, x3
+# CHECK: msr {{trcvmidcvr7|TRCVMIDCVR7}}, x3
0x4e 0x30 0x11 0xd5
-# CHECK: msr trccidcctlr0, x14
+# CHECK: msr {{trccidcctlr0|TRCCIDCCTLR0}}, x14
0x56 0x31 0x11 0xd5
-# CHECK: msr trccidcctlr1, x22
+# CHECK: msr {{trccidcctlr1|TRCCIDCCTLR1}}, x22
0x48 0x32 0x11 0xd5
-# CHECK: msr trcvmidcctlr0, x8
+# CHECK: msr {{trcvmidcctlr0|TRCVMIDCCTLR0}}, x8
0x4f 0x33 0x11 0xd5
-# CHECK: msr trcvmidcctlr1, x15
+# CHECK: msr {{trcvmidcctlr1|TRCVMIDCCTLR1}}, x15
0x81 0x70 0x11 0xd5
-# CHECK: msr trcitctrl, x1
+# CHECK: msr {{trcitctrl|TRCITCTRL}}, x1
0xc7 0x78 0x11 0xd5
-# CHECK: msr trcclaimset, x7
+# CHECK: msr {{trcclaimset|TRCCLAIMSET}}, x7
0xdd 0x79 0x11 0xd5
-# CHECK: msr trcclaimclr, x29
+# CHECK: msr {{trcclaimclr|TRCCLAIMCLR}}, x29
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