[llvm] r207657 - [mips] Add instruction alias (sll and srl).
Matheus Almeida
matheus.almeida at imgtec.com
Wed Apr 30 08:23:04 PDT 2014
Author: matheusalmeida
Date: Wed Apr 30 10:23:04 2014
New Revision: 207657
URL: http://llvm.org/viewvc/llvm-project?rev=207657&view=rev
Log:
[mips] Add instruction alias (sll and srl).
Summary:
The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of sllv/srlv $rd, $rt, $rs.
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D3483
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/mips1/valid.s
llvm/trunk/test/MC/Mips/mips2/valid.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips32/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Apr 30 10:23:04 2014
@@ -1246,6 +1246,8 @@ def : InstAlias<"tgeu $rs, $rt", (TGEU
def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : InstAlias<"sll $rd, $rt, $rs",
+ (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : InstAlias<"sub, $rd, $rs, $imm",
(ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
def : InstAlias<"sub $rs, $imm",
@@ -1256,6 +1258,8 @@ def : InstAlias<"subu, $rd, $rs, $imm",
def : InstAlias<"subu $rs, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
0>;
+def : InstAlias<"srl $rd, $rt, $rs",
+ (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
//===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Mips/mips1/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid.s?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid.s Wed Apr 30 10:23:04 2014
@@ -67,6 +67,7 @@
sh $t6,-6704($t7)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ sll $a3,$zero,$t1 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$t1 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
sllv $a3,$zero,$t1 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
@@ -79,6 +80,7 @@
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
Modified: llvm/trunk/test/MC/Mips/mips2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid.s?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid.s Wed Apr 30 10:23:04 2014
@@ -79,6 +79,7 @@
sh $t6,-6704($t7)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ sll $a3,$zero,$t1 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$t1 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
sllv $a3,$zero,$t1 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
@@ -93,6 +94,7 @@
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Wed Apr 30 10:23:04 2014
@@ -130,6 +130,7 @@
sh $t6,-6704($t7)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$9 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
@@ -144,6 +145,7 @@
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
Modified: llvm/trunk/test/MC/Mips/mips32/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid.s?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid.s Wed Apr 30 10:23:04 2014
@@ -103,6 +103,7 @@
sh $t6,-6704($t7)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ sll $a3,$zero,$t1 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$t1 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
sllv $a3,$zero,$t1 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
@@ -117,6 +118,7 @@
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Wed Apr 30 10:23:04 2014
@@ -129,6 +129,7 @@
sh $t6,-6704($t7)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ sll $a3,$zero,$t1 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$t1 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
sllv $a3,$zero,$t1 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
@@ -143,6 +144,7 @@
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Wed Apr 30 10:23:04 2014
@@ -146,6 +146,7 @@
sh $t6,-6704($t7)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$9 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
@@ -160,6 +161,7 @@
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Wed Apr 30 10:23:04 2014
@@ -146,6 +146,7 @@
sh $t6,-6704($t7)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$9 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
@@ -160,6 +161,7 @@
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Wed Apr 30 10:23:04 2014
@@ -159,6 +159,7 @@
sh $t6,-6704($t7)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$9 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
@@ -173,6 +174,7 @@
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=207657&r1=207656&r2=207657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Wed Apr 30 10:23:04 2014
@@ -183,6 +183,7 @@
sh $t6,-6704($t7)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$9 # CHECK: sllv $7, $7, $9 # encoding: [0x01,0x27,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
@@ -197,6 +198,7 @@
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ srl $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $t9,$a0 # CHECK: srlv $25, $25, $4 # encoding: [0x00,0x99,0xc8,0x06]
srlv $t9,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
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