[llvm] r207648 - ARM64: use 32-bit operations for uxtb & uxth

[Tim Northover]

Author: tnorthover
Date: Wed Apr 30 08:37:02 2014
New Revision: 207648

URL: http://llvm.org/viewvc/llvm-project?rev=207648&view=rev
Log:
ARM64: use 32-bit operations for uxtb & uxth

Testing will be enabled shortly with basic-a64-instructions.s

Modified:
    llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
    llvm/trunk/test/MC/ARM64/aliases.s

Modified: llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp?rev=207648&r1=207647&r2=207648&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp Wed Apr 30 08:37:02 2014
@@ -4196,9 +4196,8 @@ bool ARM64AsmParser::MatchAndEmitInstruc
       delete Op;
     }
   }
-  // FIXME: Likewise for [su]xt[bh] with a Xd dst operand
-  else if (NumOperands == 3 &&
-           (Tok == "sxtb" || Tok == "uxtb" || Tok == "sxth" || Tok == "uxth")) {
+  // FIXME: Likewise for sxt[bh] with a Xd dst operand
+  else if (NumOperands == 3 && (Tok == "sxtb" || Tok == "sxth")) {
     ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
     if (Op->isReg() &&
         ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
@@ -4212,6 +4211,23 @@ bool ARM64AsmParser::MatchAndEmitInstruc
                                               Op->getEndLoc(), getContext());
         delete Op;
       }
+    }
+  }
+  // FIXME: Likewise for uxt[bh] with a Xd dst operand
+  else if (NumOperands == 3 && (Tok == "uxtb" || Tok == "uxth")) {
+    ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
+    if (Op->isReg() &&
+        ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
+            Op->getReg())) {
+      // The source register can be Wn here, but the matcher expects a
+      // GPR32. Twiddle it here if necessary.
+      ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
+      if (Op->isReg()) {
+        unsigned Reg = getWRegFromXReg(Op->getReg());
+        Operands[1] = ARM64Operand::CreateReg(Reg, false, Op->getStartLoc(),
+                                              Op->getEndLoc(), getContext());
+        delete Op;
+      }
     }
   }
 

Modified: llvm/trunk/test/MC/ARM64/aliases.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/aliases.s?rev=207648&r1=207647&r2=207648&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/aliases.s (original)
+++ llvm/trunk/test/MC/ARM64/aliases.s Wed Apr 30 08:37:02 2014
@@ -249,8 +249,8 @@ foo:
 ; CHECK: sxtb x1, w2
 ; CHECK: sxth x1, w2
 ; CHECK: sxtw x1, w2
-; CHECK: ubfx x1, x2, #0, #8
-; CHECK: ubfx x1, x2, #0, #16
+; CHECK: uxtb w1, w2
+; CHECK: uxth w1, w2
 ; CHECK: ubfx x1, x2, #0, #32
 
 ;-----------------------------------------------------------------------------