[llvm] r207515 - AArch64: Mark vector long multiplication as expand.

[Benjamin Kramer]

Author: d0k
Date: Tue Apr 29 04:37:54 2014
New Revision: 207515

URL: http://llvm.org/viewvc/llvm-project?rev=207515&view=rev
Log:
AArch64: Mark vector long multiplication as expand.

There are no patterns for this. This was already fixed for ARM64 but I forgot
to apply it to AArch64 too.

Added:
    llvm/trunk/test/CodeGen/AArch64/neon-idiv.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=207515&r1=207514&r2=207515&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Apr 29 04:37:54 2014
@@ -514,6 +514,11 @@ AArch64TargetLowering::AArch64TargetLowe
                 > VT1.getVectorElementType().getSizeInBits())
           setTruncStoreAction(VT, VT1, Expand);
       }
+
+      setOperationAction(ISD::MULHS, VT, Expand);
+      setOperationAction(ISD::SMUL_LOHI, VT, Expand);
+      setOperationAction(ISD::MULHU, VT, Expand);
+      setOperationAction(ISD::UMUL_LOHI, VT, Expand);
     }
 
     // There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply.

Added: llvm/trunk/test/CodeGen/AArch64/neon-idiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-idiv.ll?rev=207515&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-idiv.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/neon-idiv.ll Tue Apr 29 04:37:54 2014
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
+; RUN: llc -mtriple=arm64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
+
+define <4 x i32> @test1(<4 x i32> %a) {
+  %rem = srem <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
+  ret <4 x i32> %rem
+; CHECK-LABEL: test1
+; FIXME: Can we lower this more efficiently?
+; CHECK: mul
+; CHECK: mul
+; CHECK: mul
+; CHECK: mul
+}
+