[llvm] r207423 - [ARM64] Fix an issue where we were always assuming a copy was coming from a D subregister.

[Chad Rosier]

Author: mcrosier
Date: Mon Apr 28 11:21:50 2014
New Revision: 207423

URL: http://llvm.org/viewvc/llvm-project?rev=207423&view=rev
Log:
[ARM64] Fix an issue where we were always assuming a copy was coming from a D subregister.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp
    llvm/trunk/test/CodeGen/ARM64/AdvSIMD-Scalar.ll

Modified: llvm/trunk/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp?rev=207423&r1=207422&r2=207423&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp Mon Apr 28 11:21:50 2014
@@ -90,7 +90,7 @@ public:
   virtual bool runOnMachineFunction(MachineFunction &F);
 
   const char *getPassName() const {
-    return "AdvSIMD scalar operation optimization";
+    return "AdvSIMD Scalar Operation Optimization";
   }
 
   virtual void getAnalysisUsage(AnalysisUsage &AU) const {
@@ -117,7 +117,7 @@ static bool isFPR64(unsigned Reg, unsign
             SubReg == 0) ||
            (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM64::FPR128RegClass) &&
             SubReg == ARM64::dsub);
-  // Physical register references just check the regist class directly.
+  // Physical register references just check the register class directly.
   return (ARM64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
          (ARM64::FPR128RegClass.contains(Reg) && SubReg == ARM64::dsub);
 }
@@ -148,7 +148,7 @@ static unsigned getSrcFromCopy(const Mac
                 MRI) &&
         isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
                 MRI)) {
-      SubReg = ARM64::dsub;
+      SubReg = MI->getOperand(1).getSubReg();
       return MI->getOperand(1).getReg();
     }
   }

Modified: llvm/trunk/test/CodeGen/ARM64/AdvSIMD-Scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/AdvSIMD-Scalar.ll?rev=207423&r1=207422&r2=207423&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/AdvSIMD-Scalar.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/AdvSIMD-Scalar.ll Mon Apr 28 11:21:50 2014
@@ -1,10 +1,15 @@
 ; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -arm64-simd-scalar=true -asm-verbose=false | FileCheck %s
-;
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=generic -arm64-simd-scalar=true -asm-verbose=false | FileCheck %s -check-prefix=GENERIC
+
 define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
 ; CHECK-LABEL: bar:
 ; CHECK: add.2d	v[[REG:[0-9]+]], v0, v1
 ; CHECK: add	d[[REG3:[0-9]+]], d[[REG]], d1
 ; CHECK: sub	d[[REG2:[0-9]+]], d[[REG]], d1
+; GENERIC-LABEL: bar:
+; GENERIC: add	v[[REG:[0-9]+]].2d, v0.2d, v1.2d
+; GENERIC: add	d[[REG3:[0-9]+]], d[[REG]], d1
+; GENERIC: sub	d[[REG2:[0-9]+]], d[[REG]], d1
   %add = add <2 x i64> %a, %b
   %vgetq_lane = extractelement <2 x i64> %add, i32 0
   %vgetq_lane2 = extractelement <2 x i64> %b, i32 0
@@ -19,6 +24,9 @@ define double @subdd_su64(<2 x i64> %a,
 ; CHECK-LABEL: subdd_su64:
 ; CHECK: sub d0, d1, d0
 ; CHECK-NEXT: ret
+; GENERIC-LABEL: subdd_su64:
+; GENERIC: sub d0, d1, d0
+; GENERIC-NEXT: ret
   %vecext = extractelement <2 x i64> %a, i32 0
   %vecext1 = extractelement <2 x i64> %b, i32 0
   %sub.i = sub nsw i64 %vecext1, %vecext
@@ -30,9 +38,30 @@ define double @vaddd_su64(<2 x i64> %a,
 ; CHECK-LABEL: vaddd_su64:
 ; CHECK: add d0, d1, d0
 ; CHECK-NEXT: ret
+; GENERIC-LABEL: vaddd_su64:
+; GENERIC: add d0, d1, d0
+; GENERIC-NEXT: ret
   %vecext = extractelement <2 x i64> %a, i32 0
   %vecext1 = extractelement <2 x i64> %b, i32 0
   %add.i = add nsw i64 %vecext1, %vecext
   %retval = bitcast i64 %add.i to double
   ret double %retval
 }
+
+; sub MI doesn't access dsub register.
+define double @add_sub_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
+; CHECK-LABEL: add_sub_su64:
+; CHECK: add d0, d1, d0
+; CHECK: sub d0, {{d[0-9]+}}, d0
+; CHECK-NEXT: ret
+; GENERIC-LABEL: add_sub_su64:
+; GENERIC: add d0, d1, d0
+; GENERIC: sub d0, {{d[0-9]+}}, d0
+; GENERIC-NEXT: ret
+  %vecext = extractelement <2 x i64> %a, i32 0
+  %vecext1 = extractelement <2 x i64> %b, i32 0
+  %add.i = add i64 %vecext1, %vecext
+  %sub.i = sub i64 0, %add.i
+  %retval = bitcast i64 %sub.i to double
+  ret double %retval
+}