[llvm] r207247 - Make sure that DSUB does not duplicate the pattern of DSUBU

Reed Kotler rkotler at mips.com
Fri Apr 25 11:05:00 PDT 2014

Author: rkotler
Date: Fri Apr 25 13:05:00 2014
New Revision: 207247

URL: http://llvm.org/viewvc/llvm-project?rev=207247&view=rev
Make sure that DSUB does not duplicate the pattern of DSUBU

Test Plan:
Run test suite to make sure there is no regression.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3497


Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=207247&r1=207246&r2=207247&view=diff
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Fri Apr 25 13:05:00 2014
@@ -86,7 +86,7 @@ def DADDu  : ArithLogicR<"daddu", GPR64O
                               ADD_FM<0, 0x2d>;
 def DSUBu  : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
                               ADD_FM<0, 0x2f>;
-def DSUB   : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0, 0x2e>;
+def DSUB   : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>;
 let isCodeGenOnly = 1 in {
 def SLT64  : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;

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