[PATCH] AArch64: Implement big endian bit-conversion for NEON types

James Molloy james.molloy at arm.com
Thu Apr 24 07:17:54 PDT 2014

Hi Christian,

I'm confused about this patch.

1) You're testing 64-bit vector-to-scalar (and vice versa), but not 64-bit vector-to-vector. In fact, you've modified the vector-to-vector patterns for 128bit but not for 64-bit.
2) You're not predicating all the patterns I think you should be. For example: "def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;". This is a 32-bit to 16-bit vector conversion, so surely requires a pair of REVs. The only exceptions to this should be:
  a) Identity conversions, which are vNfX <-> vNiX
  b) Single-lane-to-scalar; v1fX <-> fX  | v1iX <-> iX
  c) Multi-lane-to-scalar; vNfX <-> f(X*N). These require predicating, but only require one REV not two.

Do you think I'm mistaken here? I did "switch off" for half the review thread and am still playing catchup.




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