[llvm] r206875 - AArch64/ARM64: mark fmul intrinsic as commutative.
Tim Northover
tnorthover at apple.com
Tue Apr 22 03:10:14 PDT 2014
Author: tnorthover
Date: Tue Apr 22 05:10:14 2014
New Revision: 206875
URL: http://llvm.org/viewvc/llvm-project?rev=206875&view=rev
Log:
AArch64/ARM64: mark fmul intrinsic as commutative.
This gives DAG patterns matching indexed patterns where either side is an
indexed vector.
Added:
llvm/trunk/test/CodeGen/ARM64/aarch64-neon-scalar-by-elem-mul.ll
- copied, changed from r206874, llvm/trunk/test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsARM64.td
llvm/trunk/test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll
Modified: llvm/trunk/include/llvm/IR/IntrinsicsARM64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsARM64.td?rev=206875&r1=206874&r2=206875&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsARM64.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsARM64.td Tue Apr 22 05:10:14 2014
@@ -189,7 +189,9 @@ let Properties = [IntrNoMem] in {
Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
// Vector Extending Multiply
- def int_arm64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic;
+ def int_arm64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic {
+ let Properties = [IntrNoMem, Commutative];
+ }
// Vector Saturating Doubling Long Multiply
def int_arm64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
Modified: llvm/trunk/test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll?rev=206875&r1=206874&r2=206875&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll Tue Apr 22 05:10:14 2014
@@ -1,5 +1,5 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
-
+; arm64 has separate copy due to intrinsics (aarch64-neon-scalar-by-elem-mul.ll)
define float @test_fmul_lane_ss2S(float %a, <2 x float> %v) {
; CHECK: test_fmul_lane_ss2S
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
Copied: llvm/trunk/test/CodeGen/ARM64/aarch64-neon-scalar-by-elem-mul.ll (from r206874, llvm/trunk/test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/aarch64-neon-scalar-by-elem-mul.ll?p2=llvm/trunk/test/CodeGen/ARM64/aarch64-neon-scalar-by-elem-mul.ll&p1=llvm/trunk/test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll&r1=206874&r2=206875&rev=206875&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/aarch64-neon-scalar-by-elem-mul.ll Tue Apr 22 05:10:14 2014
@@ -1,7 +1,7 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
define float @test_fmul_lane_ss2S(float %a, <2 x float> %v) {
- ; CHECK: test_fmul_lane_ss2S
+ ; CHECK-LABEL: test_fmul_lane_ss2S
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp1 = extractelement <2 x float> %v, i32 1
%tmp2 = fmul float %a, %tmp1;
@@ -9,7 +9,7 @@ define float @test_fmul_lane_ss2S(float
}
define float @test_fmul_lane_ss2S_swap(float %a, <2 x float> %v) {
- ; CHECK: test_fmul_lane_ss2S_swap
+ ; CHECK-LABEL: test_fmul_lane_ss2S_swap
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp1 = extractelement <2 x float> %v, i32 1
%tmp2 = fmul float %tmp1, %a;
@@ -18,7 +18,7 @@ define float @test_fmul_lane_ss2S_swap(f
define float @test_fmul_lane_ss4S(float %a, <4 x float> %v) {
- ; CHECK: test_fmul_lane_ss4S
+ ; CHECK-LABEL: test_fmul_lane_ss4S
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = fmul float %a, %tmp1;
@@ -26,7 +26,7 @@ define float @test_fmul_lane_ss4S(float
}
define float @test_fmul_lane_ss4S_swap(float %a, <4 x float> %v) {
- ; CHECK: test_fmul_lane_ss4S_swap
+ ; CHECK-LABEL: test_fmul_lane_ss4S_swap
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = fmul float %tmp1, %a;
@@ -35,8 +35,8 @@ define float @test_fmul_lane_ss4S_swap(f
define double @test_fmul_lane_ddD(double %a, <1 x double> %v) {
- ; CHECK: test_fmul_lane_ddD
- ; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+ ; CHECK-LABEL: test_fmul_lane_ddD
+ ; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+.d\[0]|d[0-9]+}}
%tmp1 = extractelement <1 x double> %v, i32 0
%tmp2 = fmul double %a, %tmp1;
ret double %tmp2;
@@ -45,7 +45,7 @@ define double @test_fmul_lane_ddD(double
define double @test_fmul_lane_dd2D(double %a, <2 x double> %v) {
- ; CHECK: test_fmul_lane_dd2D
+ ; CHECK-LABEL: test_fmul_lane_dd2D
; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = fmul double %a, %tmp1;
@@ -54,71 +54,71 @@ define double @test_fmul_lane_dd2D(doubl
define double @test_fmul_lane_dd2D_swap(double %a, <2 x double> %v) {
- ; CHECK: test_fmul_lane_dd2D_swap
+ ; CHECK-LABEL: test_fmul_lane_dd2D_swap
; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = fmul double %tmp1, %a;
ret double %tmp2;
}
-declare float @llvm.aarch64.neon.vmulx.f32(float, float)
+declare float @llvm.arm64.neon.fmulx.f32(float, float)
define float @test_fmulx_lane_f32(float %a, <2 x float> %v) {
- ; CHECK: test_fmulx_lane_f32
+ ; CHECK-LABEL: test_fmulx_lane_f32
; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp1 = extractelement <2 x float> %v, i32 1
- %tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
+ %tmp2 = call float @llvm.arm64.neon.fmulx.f32(float %a, float %tmp1)
ret float %tmp2;
}
define float @test_fmulx_laneq_f32(float %a, <4 x float> %v) {
- ; CHECK: test_fmulx_laneq_f32
+ ; CHECK-LABEL: test_fmulx_laneq_f32
; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
- %tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
+ %tmp2 = call float @llvm.arm64.neon.fmulx.f32(float %a, float %tmp1)
ret float %tmp2;
}
define float @test_fmulx_laneq_f32_swap(float %a, <4 x float> %v) {
- ; CHECK: test_fmulx_laneq_f32_swap
+ ; CHECK-LABEL: test_fmulx_laneq_f32_swap
; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
- %tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %tmp1, float %a)
+ %tmp2 = call float @llvm.arm64.neon.fmulx.f32(float %tmp1, float %a)
ret float %tmp2;
}
-declare double @llvm.aarch64.neon.vmulx.f64(double, double)
+declare double @llvm.arm64.neon.fmulx.f64(double, double)
define double @test_fmulx_lane_f64(double %a, <1 x double> %v) {
- ; CHECK: test_fmulx_lane_f64
- ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+ ; CHECK-LABEL: test_fmulx_lane_f64
+ ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+.d\[0]|d[0-9]+}}
%tmp1 = extractelement <1 x double> %v, i32 0
- %tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
+ %tmp2 = call double @llvm.arm64.neon.fmulx.f64(double %a, double %tmp1)
ret double %tmp2;
}
define double @test_fmulx_laneq_f64_0(double %a, <2 x double> %v) {
- ; CHECK: test_fmulx_laneq_f64_0
+ ; CHECK-LABEL: test_fmulx_laneq_f64_0
; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
%tmp1 = extractelement <2 x double> %v, i32 0
- %tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
+ %tmp2 = call double @llvm.arm64.neon.fmulx.f64(double %a, double %tmp1)
ret double %tmp2;
}
define double @test_fmulx_laneq_f64_1(double %a, <2 x double> %v) {
- ; CHECK: test_fmulx_laneq_f64_1
+ ; CHECK-LABEL: test_fmulx_laneq_f64_1
; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
- %tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
+ %tmp2 = call double @llvm.arm64.neon.fmulx.f64(double %a, double %tmp1)
ret double %tmp2;
}
define double @test_fmulx_laneq_f64_1_swap(double %a, <2 x double> %v) {
- ; CHECK: test_fmulx_laneq_f64_1_swap
+ ; CHECK-LABEL: test_fmulx_laneq_f64_1_swap
; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
- %tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %tmp1, double %a)
+ %tmp2 = call double @llvm.arm64.neon.fmulx.f64(double %tmp1, double %a)
ret double %tmp2;
}
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