[llvm] r206797 - ARM64: Extended addressing mode source reg is 64-bit.

[Jim Grosbach]

Author: grosbach
Date: Mon Apr 21 16:45:44 2014
New Revision: 206797

URL: http://llvm.org/viewvc/llvm-project?rev=206797&view=rev
Log:
ARM64: Extended addressing mode source reg is 64-bit.

The canonical form for the extended addressing mode (e.g.,
"[x1, w2, uxtw #3]" is for the MCInst to have the second register be the
full 64-bit GPR64 register class. The instruction printer cleans up
the output for display to show the 32-bit register instead, per the
specification.

This simplifies 205893 now that the aliasing is handled in the printer
in 206495 so that the codegen path and the disassembler path give the
same MCInst form.

Modified:
    llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp

Modified: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=206797&r1=206796&r2=206797&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp Mon Apr 21 16:45:44 2014
@@ -1182,11 +1182,7 @@ static DecodeStatus DecodeRegOffsetLdStI
   }
 
   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
-
-  if ((extendHi & 0x3) == 0x3)
-    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
-  else
-    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
+  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
 
   Inst.addOperand(MCOperand::CreateImm(extend));
   return Success;