[llvm] r206609 - ARM64: add extra NEG pattern.

[Tim Northover]

Author: tnorthover
Date: Fri Apr 18 09:54:35 2014
New Revision: 206609

URL: http://llvm.org/viewvc/llvm-project?rev=206609&view=rev
Log:
ARM64: add extra NEG pattern.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
    llvm/trunk/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll
    llvm/trunk/test/CodeGen/ARM64/vshift.ll

Modified: llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td?rev=206609&r1=206608&r2=206609&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td Fri Apr 18 09:54:35 2014
@@ -2664,6 +2664,8 @@ defm UQXTN  : SIMDTwoScalarMixedBHS<1, 0
 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
                                     int_arm64_neon_usqadd>;
 
+def : Pat<(ARM64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
+
 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
           (FCVTASv1i64 FPR64:$Rn)>;
 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),

Modified: llvm/trunk/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll?rev=206609&r1=206608&r2=206609&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll Fri Apr 18 09:54:35 2014
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+; arm64 has all tests not involving v1iN.
 
 define <8 x i8> @shl.v8i8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: shl.v8i8:

Modified: llvm/trunk/test/CodeGen/ARM64/vshift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vshift.ll?rev=206609&r1=206608&r2=206609&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vshift.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vshift.ll Fri Apr 18 09:54:35 2014
@@ -1907,3 +1907,11 @@ declare <16 x i8> @llvm.arm64.neon.vsli.
 declare <8 x i16> @llvm.arm64.neon.vsli.v8i16(<8 x i16>, <8 x i16>, i32) nounwind readnone
 declare <4 x i32> @llvm.arm64.neon.vsli.v4i32(<4 x i32>, <4 x i32>, i32) nounwind readnone
 declare <2 x i64> @llvm.arm64.neon.vsli.v2i64(<2 x i64>, <2 x i64>, i32) nounwind readnone
+
+define <1 x i64> @ashr_v1i64(<1 x i64> %a, <1 x i64> %b) {
+; CHECK-LABEL: ashr_v1i64:
+; CHECK: neg d{{[0-9]+}}, d{{[0-9]+}}
+; CHECK: sshl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+  %c = ashr <1 x i64> %a, %b
+  ret <1 x i64> %c
+}