[llvm] r206289 - AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed
Tim Northover
tnorthover at apple.com
Tue Apr 15 07:00:15 PDT 2014
Author: tnorthover
Date: Tue Apr 15 09:00:15 2014
New Revision: 206289
URL: http://llvm.org/viewvc/llvm-project?rev=206289&view=rev
Log:
AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed
Sometimes we need emit the bits that would actually be a MOVN when producing a
relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got
wrong until now.
Modified:
llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
llvm/trunk/test/CodeGen/AArch64/large-consts.ll
llvm/trunk/test/MC/ARM64/large-relocs.s
Modified: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp?rev=206289&r1=206288&r2=206289&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp Tue Apr 15 09:00:15 2014
@@ -550,6 +550,22 @@ unsigned ARM64MCCodeEmitter::fixMOVZ(con
if (UImm16MO.isImm())
return EncodedValue;
+ const ARM64MCExpr *A64E = cast<ARM64MCExpr>(UImm16MO.getExpr());
+ switch (A64E->getKind()) {
+ case ARM64MCExpr::VK_DTPREL_G2:
+ case ARM64MCExpr::VK_DTPREL_G1:
+ case ARM64MCExpr::VK_DTPREL_G0:
+ case ARM64MCExpr::VK_GOTTPREL_G1:
+ case ARM64MCExpr::VK_TPREL_G2:
+ case ARM64MCExpr::VK_TPREL_G1:
+ case ARM64MCExpr::VK_TPREL_G0:
+ return EncodedValue & ~(1u << 30);
+ default:
+ // Nothing to do for an unsigned fixup.
+ return EncodedValue;
+ }
+
+
return EncodedValue & ~(1u << 30);
}
Modified: llvm/trunk/test/CodeGen/AArch64/large-consts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/large-consts.ll?rev=206289&r1=206288&r2=206289&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/large-consts.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/large-consts.ll Tue Apr 15 09:00:15 2014
@@ -1,13 +1,19 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -o - %s -code-model=large -show-mc-encoding | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -o - %s -code-model=large -show-mc-encoding | FileCheck %s --check-prefix=CHECK-AARCH64
+; RUN: llc -mtriple=arm64-linux-gnu -o - %s -code-model=large -show-mc-encoding | FileCheck %s --check-prefix=CHECK-ARM64
; Make sure the shift amount is encoded into the instructions by LLVM because
; it's not the linker's job to put it there.
define double @foo() {
-; CHECK: movz [[CPADDR:x[0-9]+]], #:abs_g3:.LCPI0_0 // encoding: [A,A,0xe0'A',0xd2'A']
-; CHECK: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [A,A,0xc0'A',0xf2'A']
-; CHECK: movk [[CPADDR]], #:abs_g1_nc:.LCPI0_0 // encoding: [A,A,0xa0'A',0xf2'A']
-; CHECK: movk [[CPADDR]], #:abs_g0_nc:.LCPI0_0 // encoding: [A,A,0x80'A',0xf2'A']
+; CHECK-AARCH64: movz [[CPADDR:x[0-9]+]], #:abs_g3:.LCPI0_0 // encoding: [A,A,0xe0'A',0xd2'A']
+; CHECK-AARCH64: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [A,A,0xc0'A',0xf2'A']
+; CHECK-AARCH64: movk [[CPADDR]], #:abs_g1_nc:.LCPI0_0 // encoding: [A,A,0xa0'A',0xf2'A']
+; CHECK-AARCH64: movk [[CPADDR]], #:abs_g0_nc:.LCPI0_0 // encoding: [A,A,0x80'A',0xf2'A']
+
+; CHECK-ARM64: movz [[CPADDR:x[0-9]+]], #:abs_g3:.LCPI0_0 // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
+; CHECK-ARM64: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b110AAAAA,0xf2]
+; CHECK-ARM64: movk [[CPADDR]], #:abs_g1_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b101AAAAA,0xf2]
+; CHECK-ARM64: movk [[CPADDR]], #:abs_g0_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b100AAAAA,0xf2]
ret double 3.14159
}
Modified: llvm/trunk/test/MC/ARM64/large-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/large-relocs.s?rev=206289&r1=206288&r2=206289&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/large-relocs.s (original)
+++ llvm/trunk/test/MC/ARM64/large-relocs.s Tue Apr 15 09:00:15 2014
@@ -3,7 +3,7 @@
movz x2, #:abs_g0:sym
movk w3, #:abs_g0_nc:sym
-// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0x92]
+// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2]
// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_arm64_movw
// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72]
// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_arm64_movw
@@ -13,7 +13,7 @@
movz x4, #:abs_g1:sym
movk w5, #:abs_g1_nc:sym
-// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0x92]
+// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2]
// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_arm64_movw
// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72]
// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_arm64_movw
@@ -23,7 +23,7 @@
movz x6, #:abs_g2:sym
movk x7, #:abs_g2_nc:sym
-// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0x92]
+// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2]
// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_arm64_movw
// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2]
// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_arm64_movw
@@ -32,7 +32,7 @@
// CHECK-OBJ: 14 R_AARCH64_MOVW_UABS_G2_NC sym
movz x8, #:abs_g3:sym
-// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0x92]
+// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw
// CHECK-OBJ: 18 R_AARCH64_MOVW_UABS_G3 sym
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