[llvm] r206198 - [ARM64] Port over missing subtarget features, and CPU definitions from AArch64.

[James Molloy]

Author: jamesm
Date: Mon Apr 14 12:38:00 2014
New Revision: 206198

URL: http://llvm.org/viewvc/llvm-project?rev=206198&view=rev
Log:
[ARM64] Port over missing subtarget features, and CPU definitions from AArch64.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64.td
    llvm/trunk/lib/Target/ARM64/ARM64Subtarget.cpp
    llvm/trunk/lib/Target/ARM64/ARM64Subtarget.h

Modified: llvm/trunk/lib/Target/ARM64/ARM64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64.td?rev=206198&r1=206197&r2=206198&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64.td Mon Apr 14 12:38:00 2014
@@ -20,6 +20,15 @@ include "llvm/Target/Target.td"
 // ARM64 Subtarget features.
 //
 
+def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
+  "Enable ARMv8 FP">;
+
+def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
+  "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
+
+def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
+  "Enable cryptographic instructions">;
+
 /// Cyclone has register move instructions which are "free".
 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
                                         "Has zereo-cycle register moves">;
@@ -49,9 +58,31 @@ def ARM64InstrInfo : InstrInfo;
 //
 include "ARM64SchedCyclone.td"
 
-def : ProcessorModel<"arm64-generic", NoSchedModel, []>;
+def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
+                                   "Cortex-A53 ARM processors",
+                                   [FeatureFPARMv8,
+                                   FeatureNEON,
+                                   FeatureCrypto]>;
+
+def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
+                                   "Cortex-A57 ARM processors",
+                                   [FeatureFPARMv8,
+                                   FeatureNEON,
+                                   FeatureCrypto]>;
+
+def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
+                                   "Cyclone",
+                                   [FeatureFPARMv8,
+                                   FeatureNEON,
+                                   FeatureCrypto,
+                                   FeatureZCRegMove, FeatureZCZeroing]>;
+
+def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8, FeatureNEON]>;
+
+def : ProcessorModel<"cortex-a53", NoSchedModel, [ProcA53]>;
+def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>;
 
-def : ProcessorModel<"cyclone", CycloneModel, [FeatureZCRegMove, FeatureZCZeroing]>;
+def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 
 //===----------------------------------------------------------------------===//
 // Assembly parser

Modified: llvm/trunk/lib/Target/ARM64/ARM64Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64Subtarget.cpp?rev=206198&r1=206197&r2=206198&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64Subtarget.cpp Mon Apr 14 12:38:00 2014
@@ -26,12 +26,15 @@ using namespace llvm;
 
 ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU,
                                const std::string &FS)
-    : ARM64GenSubtargetInfo(TT, CPU, FS), HasZeroCycleRegMove(false),
-      HasZeroCycleZeroing(false), CPUString(CPU), TargetTriple(TT) {
+    : ARM64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
+      HasFPARMv8(false), HasNEON(false), HasCrypto(false),
+      HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
+      CPUString(CPU), TargetTriple(TT) {
   // Determine default and user-specified characteristics
 
+  // FIXME: Make this darwin-only.
   if (CPUString.empty())
-    // We default to Cyclone for now.
+    // We default to Cyclone for now, on Darwin.
     CPUString = "cyclone";
 
   ParseSubtargetFeatures(CPUString, FS);

Modified: llvm/trunk/lib/Target/ARM64/ARM64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64Subtarget.h?rev=206198&r1=206197&r2=206198&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64Subtarget.h (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64Subtarget.h Mon Apr 14 12:38:00 2014
@@ -27,6 +27,15 @@ class StringRef;
 
 class ARM64Subtarget : public ARM64GenSubtargetInfo {
 protected:
+  enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
+
+  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
+  ARMProcFamilyEnum ARMProcFamily;
+
+  bool HasFPARMv8;
+  bool HasNEON;
+  bool HasCrypto;
+
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove;
 
@@ -51,6 +60,10 @@ public:
 
   bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
 
+  bool hasFPARMv8() const { return HasFPARMv8; }
+  bool hasNEON() const { return HasNEON; }
+  bool hasCrypto() const { return HasCrypto; }
+
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
 
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }