[PATCH] R600/SI: Refactor SOPC classes slightly.

Tom Stellard tom at stellard.net
Fri Apr 11 12:22:41 PDT 2014 

LGTM.

On Fri, Apr 11, 2014 at 10:41:52AM -0700, Matt Arsenault wrote:
> Better match what is done for VOPC to eventually prefer selecting these.
> 
> 
> http://reviews.llvm.org/D3358
> 
> Files:
>   lib/Target/R600/SIInstrInfo.cpp
>   lib/Target/R600/SIInstrInfo.td
>   lib/Target/R600/SIInstructions.td
> 
> Index: lib/Target/R600/SIInstrInfo.cpp
> ===================================================================
> --- lib/Target/R600/SIInstrInfo.cpp
> +++ lib/Target/R600/SIInstrInfo.cpp
> @@ -538,6 +538,12 @@
>    case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
>    case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
>    case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
> +  case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
> +  case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
> +  case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
> +  case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
> +  case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
> +  case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
>    }
>  }
>  
> Index: lib/Target/R600/SIInstrInfo.td
> ===================================================================
> --- lib/Target/R600/SIInstrInfo.td
> +++ lib/Target/R600/SIInstrInfo.td
> @@ -196,15 +196,17 @@
>    opName#" $dst, $src0, $src1", pattern
>  >;
>  
> -class SOPC_32 <bits<7> op, string opName, list<dag> pattern> : SOPC <
> -  op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
> -  opName#" $dst, $src0, $src1", pattern
> ->;
>  
> -class SOPC_64 <bits<7> op, string opName, list<dag> pattern> : SOPC <
> -  op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
> -  opName#" $dst, $src0, $src1", pattern
> ->;
> +class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
> +                    string opName, PatLeaf cond> : SOPC <
> +  op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
> +  opName#" $dst, $src0, $src1", []>;
> +
> +class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
> +  : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
> +
> +class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
> +  : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
>  
>  class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
>    op, (outs SReg_32:$dst), (ins i16imm:$src0),
> Index: lib/Target/R600/SIInstructions.td
> ===================================================================
> --- lib/Target/R600/SIInstructions.td
> +++ lib/Target/R600/SIInstructions.td
> @@ -1026,18 +1026,18 @@
>  >;
>  ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
>  ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
> -def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>;
> -def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>;
> -def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>;
> -def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>;
> -def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>;
> -def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>;
> -def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>;
> -def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>;
> -def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>;
> -def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>;
> -def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>;
> -def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>;
> +def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
> +def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
> +def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
> +def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
> +def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
> +def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
> +def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
> +def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
> +def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
> +def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
> +def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
> +def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
>  ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
>  ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
>  ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;

> Index: lib/Target/R600/SIInstrInfo.cpp
> ===================================================================
> --- lib/Target/R600/SIInstrInfo.cpp
> +++ lib/Target/R600/SIInstrInfo.cpp
> @@ -538,6 +538,12 @@
>    case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
>    case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
>    case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
> +  case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
> +  case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
> +  case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
> +  case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
> +  case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
> +  case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
>    }
>  }
>  
> Index: lib/Target/R600/SIInstrInfo.td
> ===================================================================
> --- lib/Target/R600/SIInstrInfo.td
> +++ lib/Target/R600/SIInstrInfo.td
> @@ -196,15 +196,17 @@
>    opName#" $dst, $src0, $src1", pattern
>  >;
>  
> -class SOPC_32 <bits<7> op, string opName, list<dag> pattern> : SOPC <
> -  op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
> -  opName#" $dst, $src0, $src1", pattern
> ->;
>  
> -class SOPC_64 <bits<7> op, string opName, list<dag> pattern> : SOPC <
> -  op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
> -  opName#" $dst, $src0, $src1", pattern
> ->;
> +class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
> +                    string opName, PatLeaf cond> : SOPC <
> +  op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
> +  opName#" $dst, $src0, $src1", []>;
> +
> +class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
> +  : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
> +
> +class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
> +  : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
>  
>  class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
>    op, (outs SReg_32:$dst), (ins i16imm:$src0),
> Index: lib/Target/R600/SIInstructions.td
> ===================================================================
> --- lib/Target/R600/SIInstructions.td
> +++ lib/Target/R600/SIInstructions.td
> @@ -1026,18 +1026,18 @@
>  >;
>  ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
>  ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
> -def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>;
> -def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>;
> -def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>;
> -def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>;
> -def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>;
> -def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>;
> -def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>;
> -def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>;
> -def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>;
> -def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>;
> -def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>;
> -def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>;
> +def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
> +def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
> +def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
> +def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
> +def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
> +def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
> +def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
> +def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
> +def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
> +def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
> +def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
> +def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
>  ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
>  ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
>  ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;

> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

More information about the llvm-commits mailing list