[PATCH] AArch64: big endian constant vector pools

[Tim Northover]

Hi Christian,

Sorry for the delay, I was at the conference.

I'm afraid this patch is going in the wrong direction.

LLVM's IR puts the lowest addressed element of a vector in index 0
(regardless of endianness), and I think this applies equally to the
BUILD_VECTORs you're analysing so reversing them will give an
incorrect constant pool.

E.g.

@var = global <4 x i16> <i16 32, i16 33, i16 34, i16 35>
define <4 x i16> @foo() {
  %val = load <4 x i16>* @var
  %diff = sub <4 x i16> %val, <4 x i16> < i16 32, i16 33, i16 34, i16 35 >
  ret <4 x i16> %val
}

With this patch (+ the one to disable LD1) this code will no longer
produce a vector of zeroes. And to maintain compatibility with the LDR
choice, that's because *neither* needs reversing, rather than because
*both* do.

Can you tell us what C-level problem you're trying to solve? I can
hopefully suggest a more consistent change.

Cheers.

Tim.