[llvm] r205731 - R600: Match 24-bit arithmetic patterns in a Target DAGCombine

[Tom Stellard]

On Wed, Apr 09, 2014 at 02:20:17PM -0700, Matt Arsenault wrote:
> On 04/07/2014 12:45 PM, Tom Stellard wrote:
> > +      if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
> > +        N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
> > +        N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
> > +        Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
> > +      } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
> > +        N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
> > +        N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
> > +        Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
> > +      } else {
> > +        break;
> > +      }
> > +
> > +      SDValue Reg = DAG.getSExtOrTrunc(Mul, DL, VT);
> Using sext for the u24 case for the final result doesn't look right

You are right, I will fix this.

-Tom

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