[LLVMdev] 3.4.1 Release Plans
Tom Stellard
tom at stellard.net
Wed Apr 9 08:47:03 PDT 2014
On Wed, Apr 09, 2014 at 01:43:46AM -0500, Hal Finkel wrote:
> ----- Original Message -----
> > From: "Hal Finkel" <hfinkel at anl.gov>
> > To: "Tom Stellard" <tom at stellard.net>
> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>
> > Sent: Wednesday, April 9, 2014 1:28:23 AM
> > Subject: Re: [LLVMdev] 3.4.1 Release Plans
> >
> > ----- Original Message -----
> > > From: "Tom Stellard" <tom at stellard.net>
> > > To: "Hal Finkel" <hfinkel at anl.gov>
> > > Cc: "Andrew Trick" <atrick at apple.com>, "Owen Anderson"
> > > <owen at apple.com>, "Evan Cheng" <evan.cheng at apple.com>, "nadav"
> > > <nadav at apple.com>, "Ben Pope" <benpope81 at gmail.com>,
> > > llvmdev at cs.uiuc.edu, "Erik Verbruggen" <erik.verbruggen at me.com>
> > > Sent: Tuesday, April 8, 2014 7:28:01 PM
> > > Subject: Re: [LLVMdev] 3.4.1 Release Plans
> > >
> > > Hi Hal,
> > >
> > > > Nadav Rotem:
> > > > r199570 - LoopVectorizer: A reduction that has multiple uses of
> > > > the
> > > > reduction value is not
> > > >
> > > > r199291 - LoopVectorize: Only strip casts from integer types when
> > > > replacing symbolic
> > >
> > > This commit changes the functions
> > > replaceSymbolicStrideSCEV() and
> > > InnerLoopVectorizer::addStrideCheck(),
> > > which were both added in r198950, so when I apply it to 3.4 nothing
> > > changes. If the bug fixed by this commit is present in 3.4, you
> > > may
> > > need to come up with a different patch to fix it.
> >
> > I'm sorry, you're right. There is nothing to fix there in 3.4.
> >
> > >
> > > > Also, please include the following patches in 3.4.1. I am the
> > > > code
> > > > owner, and I approve ;)
> > > >
> > > > r205630 - [PowerPC] Add a full condition code register to make
> > > > the
> > > > "cc" clobber work
> > >
> > > The test case for this fails on the 3.4 branch, so I was not able
> > > to
> > > merge it. The problem is that cmpld instructions are generated
> > > instead of
> > > cmpd. Can you take a look?
> >
> > Will do shortly (but I'll cc llvm-commits instead of llvmdev).
>
> I've attached an updated patch to apply against 3.4. As it turns out, it does not matter whether cmpd or cmpld is used for the equality comparison, and a post-3.4 code change has altered which one will be chosen.
>
Hi Hal,
I just merged this patch.
-Tom
> >
> > -Hal
> >
> > >
> > > > r204155 - Fix PR19144: Incorrect offset generated for int-to-fp
> > > > conversion at -O0
> > > > r203054 - The PPC global base register cannot be r0
> > > > r199832 - Fix pr18515.
> > > > r200288 - Handle spilling the PPC GPRC_NOR0 register class
> > > > r199763 - Fix pointer info on PPC byval stores
> > > > r202192 - Account for 128-bit integer operations in PPCCTRLoops
> > > >
> > > > r198425 - Fix loop rerolling pass failure with non-consant loop
> > > > lower bound
> > > >
> > >
> > > The rest of the patches approved by you and Nadav have been merged.
> > >
> > > -Tom
> > >
> > > > I apologize the delay; I've not had a chance to refine my list
> > > > until this morning.
> > > >
> > > > Thanks again,
> > > > Hal
> > > >
> > > > ----- Original Message -----
> > > > > From: "Hal Finkel" <hfinkel at anl.gov>
> > > > > To: "Tom Stellard" <tom at stellard.net>
> > > > > Cc: "Ben Pope" <benpope81 at gmail.com>, llvmdev at cs.uiuc.edu,
> > > > > "Erik
> > > > > Verbruggen" <erik.verbruggen at me.com>
> > > > > Sent: Thursday, March 27, 2014 7:49:36 AM
> > > > > Subject: Re: [LLVMdev] 3.4.1 Release Plans
> > > > >
> > > > > ----- Original Message -----
> > > > > > From: "Tom Stellard" <tom at stellard.net>
> > > > > > To: llvmdev at cs.uiuc.edu
> > > > > > Cc: "Renato Golin" <renato.golin at linaro.org>, "Sylvestre
> > > > > > Ledru"
> > > > > > <sylvestre at debian.org>, "Sebastian Dreßler"
> > > > > > <sebastian.dressler at gmail.com>, "Hal Finkel"
> > > > > > <hfinkel at anl.gov>,
> > > > > > "Ben Pope" <benpope81 at gmail.com>, "Arnaud Allard de
> > > > > > Grandmaison" <arnaud.adegm at gmail.com>, "Erik Verbruggen"
> > > > > > <erik.verbruggen at me.com>
> > > > > > Sent: Wednesday, March 26, 2014 11:10:43 AM
> > > > > > Subject: 3.4.1 Release Plans
> > > > > >
> > > > > > Hi,
> > > > > >
> > > > > > We are now about halfway between the 3.4 and 3.5 releases,
> > > > > > and
> > > > > > I
> > > > > > would
> > > > > > like to start preparing for a 3.4.1 release. Here is my
> > > > > > proposed
> > > > > > release
> > > > > > schedule:
> > > > > >
> > > > > > Mar 26 - April 9: Identify and backport additional bug fixes
> > > > > > to
> > > > > > the
> > > > > > 3.4 branch.
> > > > > > April 9 - April 18: Testing Phase
> > > > > > April 18: 3.4.1 Release
> > > > > >
> > > > > > How you can help:
> > > > > >
> > > > > > - If you have any bug fixes you think should be included to
> > > > > > 3.4.1,
> > > > > > send
> > > > > > me an email with the SVN revision in trunk and also cc the
> > > > > > code
> > > > > > owner
> > > > > > and llvm-commits (or cfe-commits if it is a clang patch).
> > > > > >
> > > > > > - Start integrating the 3.4 branch into your project or OS
> > > > > > distribution
> > > > > > to and check for any issues.
> > > > > >
> > > > > > - Volunteer as a tester for the testing phase.
> > > > >
> > > > > I'll go through the commit list shortly; also I'll help with
> > > > > testing
> > > > > on (X86 and PPC64).
> > > > >
> > > > > Thanks again for working on this!
> > > > >
> > > > > -Hal
> > > > >
> > > > > >
> > > > > > Thank you,
> > > > > >
> > > > > > Tom
> > > > > >
> > > > >
> > > > > --
> > > > > Hal Finkel
> > > > > Assistant Computational Scientist
> > > > > Leadership Computing Facility
> > > > > Argonne National Laboratory
> > > > >
> > > > > _______________________________________________
> > > > > LLVM Developers mailing list
> > > > > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> > > > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> > > > >
> > > >
> > > > --
> > > > Hal Finkel
> > > > Assistant Computational Scientist
> > > > Leadership Computing Facility
> > > > Argonne National Laboratory
> > >
> >
> > --
> > Hal Finkel
> > Assistant Computational Scientist
> > Leadership Computing Facility
> > Argonne National Laboratory
> >
> > _______________________________________________
> > LLVM Developers mailing list
> > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> >
>
> --
> Hal Finkel
> Assistant Computational Scientist
> Leadership Computing Facility
> Argonne National Laboratory
> Index: test/CodeGen/PowerPC/cc.ll
> ===================================================================
> --- test/CodeGen/PowerPC/cc.ll (revision 0)
> +++ test/CodeGen/PowerPC/cc.ll (revision 0)
> @@ -0,0 +1,70 @@
> +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
> +target datalayout = "E-m:e-i64:64-n32:64"
> +target triple = "powerpc64-unknown-linux-gnu"
> +
> +define i64 @test1(i64 %a, i64 %b) {
> +entry:
> + %c = icmp eq i64 %a, %b
> + br label %foo
> +
> +foo:
> + call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a)
> + br i1 %c, label %bar, label %end
> +
> +bar:
> + ret i64 %b
> +
> +end:
> + ret i64 %a
> +
> +; CHECK-LABEL: @test1
> +; CHECK: mfcr [[REG1:[0-9]+]]
> +; CHECK-DAG: cmpld
> +; CHECK-DAG: mfocrf [[REG2:[0-9]+]],
> +; CHECK-DAG: stw [[REG1]], 8(1)
> +; CHECK-DAG: stw [[REG2]], -4(1)
> +
> +; CHECK: sc
> +; CHECK: lwz [[REG3:[0-9]+]], -4(1)
> +; CHECK: mtocrf 128, [[REG3]]
> +
> +; CHECK: lwz [[REG4:[0-9]+]], 8(1)
> +; CHECK-DAG: mtocrf 32, [[REG4]]
> +; CHECK-DAG: mtocrf 16, [[REG4]]
> +; CHECK-DAG: mtocrf 8, [[REG4]]
> +; CHECK: blr
> +}
> +
> +define i64 @test2(i64 %a, i64 %b) {
> +entry:
> + %c = icmp eq i64 %a, %b
> + br label %foo
> +
> +foo:
> + call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc}" (i64 %a)
> + br i1 %c, label %bar, label %end
> +
> +bar:
> + ret i64 %b
> +
> +end:
> + ret i64 %a
> +
> +; CHECK-LABEL: @test2
> +; CHECK: mfcr [[REG1:[0-9]+]]
> +; CHECK-DAG: cmpld
> +; CHECK-DAG: mfocrf [[REG2:[0-9]+]],
> +; CHECK-DAG: stw [[REG1]], 8(1)
> +; CHECK-DAG: stw [[REG2]], -4(1)
> +
> +; CHECK: sc
> +; CHECK: lwz [[REG3:[0-9]+]], -4(1)
> +; CHECK: mtocrf 128, [[REG3]]
> +
> +; CHECK: lwz [[REG4:[0-9]+]], 8(1)
> +; CHECK-DAG: mtocrf 32, [[REG4]]
> +; CHECK-DAG: mtocrf 16, [[REG4]]
> +; CHECK-DAG: mtocrf 8, [[REG4]]
> +; CHECK: blr
> +}
> +
> Index: lib/Target/PowerPC/PPCRegisterInfo.td
> ===================================================================
> --- lib/Target/PowerPC/PPCRegisterInfo.td (revision 205830)
> +++ lib/Target/PowerPC/PPCRegisterInfo.td (working copy)
> @@ -144,6 +144,13 @@
> def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
> }
>
> +// The full condition-code register. This is not modeled fully, but defined
> +// here primarily, for compatibility with gcc, to allow the inline asm "cc"
> +// clobber specification to work.
> +def CC : PPCReg<"cc">, DwarfRegAlias<CR0> {
> + let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7];
> +}
> +
> // Link register
> def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
> //let Aliases = [LR] in
> @@ -234,3 +241,8 @@
> def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
> let CopyCost = -1;
> }
> +
> +def CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> {
> + let isAllocatable = 0;
> +}
> +
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