[llvm] r205895 - [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.

[Bradley Smith]

Author: brasmi01
Date: Wed Apr  9 09:44:44 2014
New Revision: 205895

URL: http://llvm.org/viewvc/llvm-project?rev=205895&view=rev
Log:
[ARM64] Flag setting logical/add/sub immediate instructions don't use SP.

Modified:
    llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt
    llvm/trunk/test/MC/Disassembler/ARM64/logical.txt

Modified: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=205895&r1=205894&r2=205895&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp Wed Apr  9 09:44:44 2014
@@ -1417,13 +1417,17 @@ static DecodeStatus DecodeAddSubERegInst
     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
     break;
   case ARM64::ADDXrx64:
-  case ARM64::ADDSXrx64:
   case ARM64::SUBXrx64:
-  case ARM64::SUBSXrx64:
     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
     break;
+  case ARM64::SUBSXrx64:
+  case ARM64::ADDSXrx64:
+    DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
   }
 
   Inst.addOperand(MCOperand::CreateImm(extend));
@@ -1439,13 +1443,19 @@ static DecodeStatus DecodeLogicalImmInst
   unsigned imm;
 
   if (Datasize) {
-    DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
+    if (Inst.getOpcode() == ARM64::ANDSXri)
+      DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+    else
+      DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
     imm = fieldFromInstruction(insn, 10, 13);
     if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 64))
       return Fail;
   } else {
-    DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+    if (Inst.getOpcode() == ARM64::ANDSWri)
+      DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+    else
+      DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
     imm = fieldFromInstruction(insn, 10, 12);
     if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 32))

Modified: llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt?rev=205895&r1=205894&r2=205895&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt Wed Apr  9 09:44:44 2014
@@ -49,11 +49,13 @@
 0x83 0x00 0x50 0x31
 0x83 0x00 0x10 0xb1
 0x83 0x00 0x50 0xb1
+0xff 0x83 0x00 0xb1
 
 # CHECK: adds w3, w4, #1024
 # CHECK: adds w3, w4, #4194304
 # CHECK: adds x3, x4, #1024
 # CHECK: adds x3, x4, #4194304
+# CHECK: cmn  sp, #32
 
 0x83 0x00 0x10 0x51
 0x83 0x00 0x50 0x51
@@ -71,11 +73,13 @@
 0x83 0x00 0x50 0x71
 0x83 0x00 0x10 0xf1
 0x83 0x00 0x50 0xf1
+0xff 0x83 0x00 0xf1
 
 # CHECK: subs w3, w4, #1024
 # CHECK: subs w3, w4, #4194304
 # CHECK: subs x3, x4, #1024
 # CHECK: subs x3, x4, #4194304
+# CHECK: cmp  sp, #32
 
 #==---------------------------------------------------------------------------==
 # Add/Subtract register with (optional) shift

Modified: llvm/trunk/test/MC/Disassembler/ARM64/logical.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/logical.txt?rev=205895&r1=205894&r2=205895&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/logical.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/logical.txt Wed Apr  9 09:44:44 2014
@@ -13,6 +13,7 @@
 0x00 0x00 0x40 0xf2
 0x41 0x0c 0x00 0x72
 0x41 0x0c 0x40 0xf2
+0x5f 0x0c 0x40 0xf2
 
 # CHECK: and  w0, w0, #0x1
 # CHECK: and  x0, x0, #0x1
@@ -23,18 +24,23 @@
 # CHECK: ands x0, x0, #0x1
 # CHECK: ands w1, w2, #0xf
 # CHECK: ands x1, x2, #0xf
+# CHECK: tst x2, #0xf
 
 0x41 0x00 0x12 0x52
 0x41 0x00 0x71 0xd2
+0x5f 0x00 0x71 0xd2
 
 # CHECK: eor w1, w2, #0x4000
 # CHECK: eor x1, x2, #0x8000
+# CHECK: eor sp, x2, #0x8000
 
 0x41 0x00 0x12 0x32
 0x41 0x00 0x71 0xb2
+0x5f 0x00 0x71 0xb2
 
 # CHECK: orr w1, w2, #0x4000
 # CHECK: orr x1, x2, #0x8000
+# CHECK: orr sp, x2, #0x8000
 
 #==---------------------------------------------------------------------------==
 # 5.5.3 Logical (shifted register)